WO2004112124A3 - Procede perfectionne de recuit de stabilisation - Google Patents

Procede perfectionne de recuit de stabilisation Download PDF

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Publication number
WO2004112124A3
WO2004112124A3 PCT/FR2004/001449 FR2004001449W WO2004112124A3 WO 2004112124 A3 WO2004112124 A3 WO 2004112124A3 FR 2004001449 W FR2004001449 W FR 2004001449W WO 2004112124 A3 WO2004112124 A3 WO 2004112124A3
Authority
WO
WIPO (PCT)
Prior art keywords
stabilisation
annealing method
temperature
improved annealing
improved
Prior art date
Application number
PCT/FR2004/001449
Other languages
English (en)
Other versions
WO2004112124A2 (fr
Inventor
Walter Schwarzenbach
Jean-Marc Waechter
Original Assignee
Soitec Silicon On Insulator
Walter Schwarzenbach
Jean-Marc Waechter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Walter Schwarzenbach, Jean-Marc Waechter filed Critical Soitec Silicon On Insulator
Priority to EP04767314A priority Critical patent/EP1639633A2/fr
Priority to JP2006516283A priority patent/JP4949021B2/ja
Publication of WO2004112124A2 publication Critical patent/WO2004112124A2/fr
Publication of WO2004112124A3 publication Critical patent/WO2004112124A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Laminated Bodies (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

L'invention concerne un procédé de traitement thermique de stabilisation d'une tranche multicouche élaborée à partir de matériaux choisis parmi les matériaux semiconducteurs et comprenant deux tranches solidaires par l'intermédiaire d'une interface de collage, le procédé comprenant une montée en température jusqu'à une température de fin de traitement, caractérisé en ce que ladite montée en température est effectuée avec au moins un palier.
PCT/FR2004/001449 2003-06-10 2004-06-10 Procede perfectionne de recuit de stabilisation WO2004112124A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04767314A EP1639633A2 (fr) 2003-06-10 2004-06-10 Procede perfectionne de recuit de stabilisation
JP2006516283A JP4949021B2 (ja) 2003-06-10 2004-06-10 改良された安定化アニール方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0306920A FR2856194B1 (fr) 2003-06-10 2003-06-10 Procede perfectionne de recuit de stabilisation
FR03/06920 2003-06-10

Publications (2)

Publication Number Publication Date
WO2004112124A2 WO2004112124A2 (fr) 2004-12-23
WO2004112124A3 true WO2004112124A3 (fr) 2005-05-12

Family

ID=33484295

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2004/001449 WO2004112124A2 (fr) 2003-06-10 2004-06-10 Procede perfectionne de recuit de stabilisation

Country Status (4)

Country Link
EP (1) EP1639633A2 (fr)
JP (1) JP4949021B2 (fr)
FR (1) FR2856194B1 (fr)
WO (1) WO2004112124A2 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0328817A2 (fr) * 1988-02-18 1989-08-23 Nortel Networks Corporation Procédé et appareil pour la fabrication de substrats du type SOI
EP0506416A2 (fr) * 1991-03-27 1992-09-30 Mitsubishi Denki Kabushiki Kaisha Procédé de fabrication d'un substrat du type SOI comportant une couche monocristalline en silicium sur une couche isolante
JPH0845946A (ja) * 1994-08-01 1996-02-16 Hitachi Ltd シリコン半導体単結晶基板の熱処理方法及び熱処理装置、半導体装置
US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
FR2777115A1 (fr) * 1998-04-07 1999-10-08 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP2003022975A (ja) * 2001-07-09 2003-01-24 Sumitomo Electric Ind Ltd エピタキシャルウエハとその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437922A (en) * 1982-03-26 1984-03-20 International Business Machines Corporation Method for tailoring oxygen precipitate particle density and distribution silicon wafers
JPH03166733A (ja) * 1989-11-27 1991-07-18 Olympus Optical Co Ltd 半導体装置の製造方法
JP3956271B2 (ja) * 2000-10-26 2007-08-08 株式会社Ｓｕｍｃｏ シリコンウェーハの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0328817A2 (fr) * 1988-02-18 1989-08-23 Nortel Networks Corporation Procédé et appareil pour la fabrication de substrats du type SOI
EP0506416A2 (fr) * 1991-03-27 1992-09-30 Mitsubishi Denki Kabushiki Kaisha Procédé de fabrication d'un substrat du type SOI comportant une couche monocristalline en silicium sur une couche isolante
JPH0845946A (ja) * 1994-08-01 1996-02-16 Hitachi Ltd シリコン半導体単結晶基板の熱処理方法及び熱処理装置、半導体装置
US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
FR2777115A1 (fr) * 1998-04-07 1999-10-08 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP2003022975A (ja) * 2001-07-09 2003-01-24 Sumitomo Electric Ind Ltd エピタキシャルウエハとその製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 06 28 June 1996 (1996-06-28) *
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 05 12 May 2003 (2003-05-12) *

Also Published As

Publication number Publication date
FR2856194A1 (fr) 2004-12-17
JP4949021B2 (ja) 2012-06-06
FR2856194B1 (fr) 2005-08-26
JP2006527493A (ja) 2006-11-30
WO2004112124A2 (fr) 2004-12-23
EP1639633A2 (fr) 2006-03-29

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