Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7391—Gated diode structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the invention relates to a semiconductor diode, an electronic component and a voltage intermediate circuit converter.
• the invention further relates to a control method for a voltage intermediate circuit converter.
• DC link converters use for forming
• the AC input current is first rectified.
• the DC voltage is smoothed in the DC link and converted into AC with a different voltage and frequency in the inverter.
• Inverters can also be used for forming systems
• Active semiconductor switches (can be switched off) are used as components in voltage DC link converters in power electronics.
• 25 right power semiconductors e.g. MOSFET (metal oxide semicon- ductor field effect transistor), IGBT (isolated gate bipolar transistor), bipolar transistors, GTO (gate turn-off thyristor), IGCT (integrated gate commutated thyristor) ) and freewheeling diodes are used.
• MOSFET metal oxide semicon- ductor field effect transistor
• IGBT isolated gate bipolar transistor
• bipolar transistors bipolar transistors
• GTO gate turn-off thyristor
• IGCT integrated gate commutated thyristor
• Freewheeling diodes are diodes that are used in
• the switch-on speed of the power semiconductors that can be switched off is limited by the time it takes the freewheeling diode to can record. This in turn is limited by state delays due to finite charge carrier speeds. This occurs particularly when the current and voltage change very quickly.
• the state delay results in particular from the fact that the diode is flooded with charge carriers in the current carrying phase, which must first be removed from the diode before a phase change, ie switching in the reverse direction, and the commutation associated therewith, ie changing the current direction the diode can absorb voltage.
• the charge carriers still to be cleared out when the diode is switched over are also referred to as storage charging and the associated behavior of the diode is known as reverse recovery behavior.
• Free-wheeling diode can be guaranteed.
• the resulting power loss must be taken into account when dimensioning the converter. This leads to an increased cooling effort or to an increased chip area of the power semiconductors or limits the operating frequency of the converter.
• MOS Metal Oxide Semiconduc- gate
• MCD Metal Oxide Semiconduc- gate
• Schröder, Dierk “Electrical drives 3 - power electronic components ⁇ , Springer-Verlag, Berlin, 1996, pages 373 to 377) known.
• MCD Metal Oxide Semiconduc- gate
• a MOS control head ie a gate electrode mounted insulated above the semiconductor material, is used to switch between two states of the component. These states can be characterized as follows: .0
• Blocking capacity state 2 high forward resistance, low or none
• the MCDs described behave like a switched-on MOSFET or like one, depending on the embodiment
• All of the MCDs described are constructed in such a way that a p- or n-doped semiconductor region is bridged by an n- or p-conducting channel when a gate voltage is applied. Switching over the MCD thus causes an assembly or disassembly
• state 2 the pn junction is "bypassed" by an alternative current path.
• the pn junction is therefore not lockable in state 2.
• the state 2 of the MCD is therefore characterized by no or - in the behavior like a Schottky diode - by only a small blocking capacity.
• state 1 Since state 1 has the lower forward resistance, this state should be set in the forward case.
• the MCD can only be in state 1, since state 2 has no or only a small blocking capacity and can therefore absorb no or only a small voltage.
• this state has no or only a small storage charge.
• the MCD should - first of all - be in state 1, then switch to state 2, change the current direction, and then switch to state 1 - in order to achieve optimal behavior of the MCD done in order to realize the blocking.
• a disadvantage of these MCDs described in Schröder is that the method described above for realizing the optimal transition of the MCD from the open to the blocking case is very complex and reacts critically to the chronological sequence of the control pulses.
• the invention is therefore based on the object of specifying a new semiconductor diode in which it is possible to switch between states of different forward resistance and different storage charge, but the optimum transition of the semiconductor diode from forward to blocking is simplified and thus less critical with regard to the chronological sequence the control impulse is.
• Another object of the invention is to integrate this semiconductor diode into an electronic component.
• a voltage intermediate circuit converter is to be specified in which the storage charge to be cleared from the freewheeling diode during a commutation process and thus the switching loss energy is reduced, in order thereby to enable a higher switch-on speed of the voltage intermediate circuit converter.
• the object of the invention is also to specify a control method for such a voltage intermediate circuit converter.
• the invention with regard to the semiconductor diode is based on the consideration of specifying a semiconductor diode with at least one pn junction, which can be switched between a first state and a second state, wherein - The second state has a larger forward resistance compared to the first state and
• the second state has a smaller storage charge compared to the first state
• the pn transition can be blocked both in the first state and in the second state, each with at least one predetermined blocking capacity.
• L5 is the sequence of the control impulses.
• the blocking capacity is understood to mean that the diode in the event of blocking, i.e. in the event that voltage is applied to the diode in the reverse direction, can absorb voltage and only a very small reverse current flows.
• the size of the blocking assets can be
• 25 can be defined in the event of a lock.
• the blocking capacity of the semiconductor diode is characterized in that in the blocking case the breakdown voltage in the first state and in the second state 30 of the semiconductor diode is at least 100 V, preferably at least 1000 V.
• An expedient embodiment of the invention provides that the blocking capacity, characterized by the breakdown voltage 35 in the blocking case, in the first and in the second state of the semiconductor diode is of the same order of magnitude, ie the fertilizing to the nearest power of ten leads to the same result.
• An advantageous embodiment of the invention provides that the semiconductor diode comprises a gate electrode and a first electrode, and the switchover between the first state and the second state of the semiconductor diode takes place by changing a voltage present between the gate electrode and the first electrode.
• the invention is further based on the consideration, according to claim 5, of specifying a semiconductor diode with a first region of predetermined conduction type, a second region with opposite conduction type compared to the first region, a pn junction formed between the first region and the second region, a first electrode that is in direct electrical contact with the first area, ie in particular forms an ohmic contact with this, a second electrode which is in direct electrical contact with the second region, i.e.
• a gate electrode which is arranged separated from the first region and / or second region in the region of the pn junction and / or first region by an insulation layer, the majority charge carrier concentration being applied by applying a voltage between the first electrode and the gate electrode changeable in the first area, ie can be increased or decreased.
• a predetermined conductivity type in the first region is understood to mean that the first region consists of a p-doped or an n-doped semiconductor material.
• the opposite type of conduction in the second area means that the second area is opposite to the first area is, ie if the first region is p-doped, the second region is n-doped and vice versa.
• the first electrode, second electrode and gate electrode can be made of metal.
• the gate electrode, insulation layer and the semiconductor material of the first and second regions form an MIS (Metal-I-Insulator-Semiconductor) contact. Since the voltage applied between the gate electrode and the first electrode controls the majority charge carrier concentration in the first region, the MIS contact is also referred to as an MIS control head. Overall, it is an MIS-controlled diode. In addition to controlling the majority carrier concentration by the MIS control head in the first region, the carrier concentration in the second region is also automatically set.
• MIS Metal-I-Insulator-Semiconductor
• This MIS-controlled semiconductor diode according to the invention has, in particular, the states specified in claim 1 and can therefore be regarded as an advantageous embodiment of the semiconductor diode according to one of claims 1 to 4.
• the states can be characterized as follows:
• the difference with the processes known from the prior art MOS-controlled diode is, in particular, that the di- to the invention ode mutandis, in the second state, the Anson ⁇ th state 2 according to the prior art corresponds to a pn junction with barrier property having.
• the Current direction ie during the transition from pass-through to blocking, should therefore - in order to achieve optimal behavior of the MIS-controlled diode - the MIS-controlled diode according to the invention initially as for the MOS-controlled diode according to the prior art in the first State (state 1 in the prior art) and then switched to the second state (state 2 in the prior art). Now the current direction changes.
• the immediate switchover to state 1 according to the prior art is now dispensed with, since, in contrast to the prior art, the MI-controlled diode according to the invention also has a pn junction with blocking capacity in the second state and therefore also in the second state the blocking is realized.
• the optimal transition of the semiconductor diode from the open to the blocking case is simplified and thus less critical with regard to the chronological sequence of the control pulses.
• state 2 in contrast to state 1, is determined by the construction of a conductive channel and the resulting opening of a current path past the pn junction
• the states are defined in the MIS - Controlled semiconductor diode according to the invention by a different majority carrier concentration in the first area.
• the pn junction is not “bypassed” by an alternative current path.
• the blocking capacity of the pn junction of the diode is present in both states.
• the gate electrode does not cover the first region up to the first electrode or the second region up to the second electrode.
• An advantageous embodiment of the invention provides that the first region and / or the second region of the semiconductor diode is / are designed as a layer. It can also be provided that the insulation layer between the gate electrode and the first and / or second region is an oxide layer.
• the MIS contact of the semiconductor diode is thus a MOS contact in this specific embodiment.
• the first region consists of a first partial region, which adjoins the first electrode, and a second partial region, which adjoins the second region and forms the pn junction therewith, the doping in first sub-area is higher than the doping in the second sub-area.
• the gate electrode is arranged only in the region of the first partial region of the first region.
• the second region consists of a first sub-region which is adjacent to the first region and forms the pn junction with it, and a second sub-region which is connected to the second
• the doping in the first sub-area is lower than the doping in the second sub-area.
• Structures of this type are common in components of power electronics in order to obtain the required breakdown strength. According to an expedient embodiment,
• the first partial area and / or the second partial area of the second area can be formed as a layer.
• a first embodiment variant of the invention provides that the doping in the first region is smaller than the doping 30 in the second sub-region of the second region.
• a further development of this first embodiment variant provides that the second partial area of the second area in the area between the second electrode and the first partial area of the second area is interspersed with islands whose charge type is opposite to the charge type of the second area.
• the doping in the first region is greater than the doping in the second sub-region of the second region.
• the semiconductor diode provides that the first region is an n-doped region.
• the second area is therefore p-doped.
• the first sub-region is thus a p-minus-doped sub-region and the second sub-region is a p-plus-doped sub-region.
• the first electrode is a cathode
• the second electrode is an anode.
• the first region is a p-doped region.
• the second area is therefore n-doped. If the second region is divided into two, the first sub-region is thus an n-minus-doped sub-region and the second sub-region is an n-plus-doped sub-region.
• the first electrode is an anode
• the second electrode is a cathode.
• a voltage applied between the gate electrode and the first electrode can therefore be referred to as the gate anode voltage uGA.
• such a semiconductor diode is in the second state defined above without the application of a gate-anode voltage, ie it is characterized in relation to the first state due to a high forward resistance and a low storage charge.
• the doping profile and the charge carrier lifespan are expediently set such that the diode has a soft reverse recovery behavior in this state, ie the tail current decays relatively gently.
• a negative gate anode voltage By applying a negative gate anode voltage, the hole concentration in the p-doped first region is raised, the diode is then in the first state, ie it has a low forward resistance and a high storage charge in relation to the second state. Switching between the states of the diode is thus carried out by switching a negative gate anode voltage on or off.
• the second sub-region of the second region is highly n-doped compared to the first sub-region.
• This highly n-doped second sub-region is interspersed with p-islands. This has the advantage that when the semiconductor diode changes from the first to the second state, the holes in the low n-doped first sub-region of the second region are cleared out more quickly.
• the p-doping in the first region is greater than the n-doping in the second sub-region of the second region.
• the semiconductor diode is in the first state defined above, which is characterized in comparison to the second state by a low on resistance and a high storage charge.
• the hole concentration in the p-doped first region is lowered, the diode then has a high forward resistance and a low storage charge and is therefore in the second state.
• the semiconductor diode according to the invention is implemented in a planar structure.
• the diode is implemented in one Trench structure, ie as a trench element, or in a MESA structure.
• the first and / or the second area of the semiconductor diode according to the invention can be produced on the basis of silicon or silicon carbide or gallium arsenide GaAs.
• the insulating layer between the gate electrode and the first and / or 'second region may be composed of silicon oxide.
• the semiconductor diode is assigned a control device for applying a voltage between the first electrode and the gate electrode.
• a control means enables' by controlling the voltage applied to the controlled switching of the semiconductor diode between the first and second state.
• the invention with respect to the electronic component is based on the consideration of specifying an electronic component with at least one chip which comprises a plurality of the semiconductor diodes according to the invention as cells.
• This chip is referred to as the first type of chip.
• the electronic component it is provided to integrate at least one chip of the first type and at least one chip, which comprises a plurality of power semiconductors which can be switched off, as cells, in a module housing.
• Chips with a plurality of power semiconductors that can be switched off are referred to as chips of the second type.
• two or more chips of the first type can be connected in parallel in the module housing.
• one or more chips of the first type can also be connected in the module housing with one or more chips of the second type to form a single switch and / or a half bridge (phase) and / or several phases.
• An advantageous embodiment of the electronic component with a module housing provides that the gate connection of each semiconductor diode of the chips of the first type is led out of the module housing separately from the gate connection of the switchable power semiconductor of the chips of the second type associated with this diode and is each provided with a contact point ,
• each semiconductor diode of the first type of chip and the gate connection of the switchable power semiconductor of the second type of chip associated with this diode are already connected within the module housing, so that it is available to the user , ie to the outside, there is only one contact point.
• a further development provides that an auxiliary emitter connection or an auxiliary cathode connection and / or an auxiliary anode connection or an auxiliary collector connection is provided in the electronic component with module housing for the power semiconductor which can be switched off.
• An embodiment is then advantageous in which the auxiliary emitter connection or the auxiliary cathode connection of the switchable power semiconductor is connected to the auxiliary anode connection of the semiconductor diode assigned to this switchable power semiconductor.
• Auxiliary connections are understood to mean connections in which, in contrast to power connections, only a small control current flows.
• the control circuits or parts of the control circuits for the semiconductor diodes of the chips of the first type and / or those that can be switched off Power semiconductors of the second type integrated into the module housing are based on the consideration of specifying a voltage intermediate circuit converter which comprises at least one semiconductor diode according to the invention and at least one power semiconductor. Any of the described design variants and developments can be used as the semiconductor diode.
• the use of the semiconductor diodes according to the invention offers the advantage that by switching between the first and second states, the advantages of the respective state can be used in a targeted manner in accordance with the different switching phases of the voltage intermediate circuit converter.
• the semiconductor diodes are connected in such a way that they are each assigned to a power semiconductor that can be switched off as a freewheeling diode.
• This combination offers the advantage that the storage charge to be cleared during a commutation process from the freewheeling diode to the power semiconductor that can be switched off and thus the switching loss energy can be reduced with appropriate control of the states of the semiconductor diode. This leads to a reduced power loss of the converter and thus enables smaller power semiconductor areas and less cooling effort.
• the voltage intermediate circuit converter comprises at least one subsystem for converting a phase of the output AC system, which comprises two semiconductor diodes according to the invention and two power semiconductors which can be switched off.
• the power semiconductors that can be switched off can be MOSFET and / or IGBT and / or bipolar transistors and / or GTO and / or IGCT.
• the voltage intermediate circuit converter according to the invention can be a two-point converter or a three-point converter or another multi-point converter. The number of phases is arbitrary.
• a particularly advantageous development provides that the power semiconductors which can be switched off are connected in series.
• the reduced storage charge of the MIS-controlled diodes leads to a simplified voltage symmetry between the power semiconductors.
• Both the power semiconductor that can be switched off and the associated freewheeling diode generally require a control circuit.
• the control functions of a power semiconductor and the respectively associated semiconductor diode are integrated in a common control circuit. This integration of the control functions can be implemented for one or more power semiconductors that can be switched off.
• the common control circuit is characterized by a common voltage supply.
• the common voltage supply can take place through an AC voltage source, a subsequent transformer (transformer) and a subsequent rectification.
• the common control circuit is characterized by a common control signal transmission.
• the common control signal transmission can be carried out by optocouplers and / or optical fibers and / or pulse transmitters, i.e. small transformers for signal transmission.
• the invention is based on the control method for the voltage intermediate circuit according to the invention Converters on the consideration of coordinating the timing of the activation of the power semiconductors which can be switched off and the associated semiconductor diodes according to the invention. This means that the switching of the semiconductor diode between the first and second state is in a defined temporal relationship for switching the associated switchable power semiconductor on and off. Furthermore, in the case of a plurality of power semiconductors and semiconductor diodes which can be switched off, in a voltage intermediate circuit converter
• the semiconductor diodes are switched between the first and second states in a time connection with the switching off and / or with the switching on of the associated switchable power semiconductors.
• the 35 power semiconductor is turned off, the second power semiconductor that can be turned off is turned on at a third point in time, and at a fourth point in time the second semiconductor diode is switched from the second state to the first state.
• the first switchable power semiconductor is thus switched off, the second switchable power semiconductor is switched on, the first semiconductor diode in the second state and the second semiconductor diode in the first state.
• the first point in time before the second point in time or the second point in time before the first point in time can be in the chronological sequence of the individual steps.
• the third point in time before the fourth point in time or the fourth point in time before the third point in time can be in the chronological sequence of the individual steps. Furthermore, in this first variant, in the chronological sequence of the individual steps, the first point in time and the second point in time lie before the third point in time and the fourth point in time, i.e. the later from the first and second times is before the earlier from the third and fourth times.
• a blocking capacity of the semiconductor diodes in the first state is not absolutely necessary, i.e. this variant of the control method can also be carried out with other types of semiconductor diodes.
• the control procedure is based on the chronological sequence of the individual steps, the fourth time before the second time.
• the semiconductor diodes are switched between the first and second states in a time connection with the switching off of the associated switchable power semiconductors. On Switching the semiconductor diodes is not necessary when switching on the associated switchable power semiconductors in the case of the second embodiment.
• this second embodiment of the control method provides that in a voltage intermediate circuit converter with a first switchable power semiconductor and a second switchable power semiconductor as well as a first semiconductor diode assigned to the first switchable power semiconductor according to the invention and a second switchable power semiconductor second semiconductor diode according to the invention, in which the first switchable power semiconductor is first switched on, the second switchable power semiconductor is switched off, the first semiconductor diode is in the first state and the second semiconductor diode is in the first state, the first semiconductor diode from the first state to the first second state is switched, the first switchable power semiconductor is switched off at a second point in time, the second switchable power semiconductor is switched on at a third point in time et is, and - at a fourth time, the first semiconductor diode is switched back from the second state to the first state.
• the first switchable power semiconductor is thus switched off, the second switchable power semiconductor is switched on and the first semiconductor diode is in the first state as at the beginning.
• the second semiconductor diode remains unchanged in the first state during the entire control process.
• the chronological sequence of the individual steps the first time and the second time before the third time and the third time before the fourth time.
• the first point in time can be before the second point in time or the second point in time can be in front of the first point in time.
• the chronological sequence of the individual steps is the first point in time before the second point in time.
• L0 ner in this second variant lies in the chronological sequence of the individual steps, the fourth point in time before the third point in time. If the first switchable power semiconductor is live, it is further provided that the fourth point in time before the
• a blocking capacity of the semiconductor diodes in the second state is not absolutely necessary, i.e. this variant of the control method can also be carried out with other types of semiconductor diodes.
• 25 device semiconductors then switch back from the second switchable power semiconductor to the first switchable power semiconductor according to the switching process from the first switchable power semiconductor to the second switchable power semiconductor.
• FIG. 1 shows a comparison of the charge carrier distribution in a conventional diode with the charge carrier distribution in an exemplary embodiment of the semiconductor diode according to the invention
• FIG. 2 shows a specific exemplary embodiment of a semiconductor diode according to the invention implemented as a trench element, FIG the invention,
• FIG 4 shows the switching sequence of a control method according to the first embodiment
• FIG 5 shows the switching sequence of a control method according to the second embodiment.
• the p-doped region 6 is the first region.
• the n-minus-doped region 7 is the first sub-region and the n-plus-doped region 8 is the second sub-region of the second region 7, 8.
• Shown in the lower portion of Figure 1 is a schematic sectional shear is by a diode 10.
• the-.p-doped region 6. This is in the case of the first embodiment illustrated here, relative to the n -plus doped area 8 low doped.
• Adjacent to this p-doped region 6 is an n-minus-doped region 7 that is broad compared to the other regions.
• “N-minus * means that this region is low-doped relative to the n-plus doped region 8.
• the n-plus doped region 8 is adjacent to the n-minus-doped region 7 on the right.
• the charge carrier distribution n, p is shown in FIG. 1 in the form of an x-y diagram above this schematic section through a diode 10.
• the x-axis represents the position in the diode 10 shown schematically below, the y-axis shows the size of the charge carrier concentration n, p.
• the curve denoted by Kl represents the charge carrier distribution in a conventional PIN diode
• the curve denoted by K2 the charge carrier distribution in a three-layer semiconductor diode according to the invention, p-doped in the first region 6, according to the first embodiment variant with no gate anode.
• Voltage uGA (uGA 0 V) and the curve labeled K3 the charge carrier distribution in the same semiconductor diode according to the invention with a negative gate-anode voltage uGA (uGA ⁇ 0 V).
• Negative gate-anode voltage means that the gate of the diode has a negative polarity with respect to the anode of the diode.
• the semiconductor diode according to the invention has a negative gate-anode voltage uGA (uGA ⁇ 0 V) in the example shown the same forward resistance as the conventional PIN diode (comparison of curves K1 and K3).
• uGA negative gate-anode voltage
• uGA 0 V
• the storage charge in the diode according to the invention is thus significantly reduced compared to the storage charge of the conventional PIN diode.
• FIG. 1 also shows that by applying the gate-anode voltage in the diode according to the invention not only the majority carrier concentration in the p-region 6 (not shown), but also the charge carrier concentration n, p on the anode side of the n-minus-doped region 7 can be set. This is shown by the comparison of curve K2 with curve K3.
• the anode side of the n-minus-doped region 7 is the side adjoining the p-doped region 6, in FIG. 1 the left side of the n-minus-doped region 7.
• the charge carrier concentration in both states of the diode according to the invention i.e.
• charge carrier distributions can also be set in other exemplary embodiments of the semiconductor diode according to the invention with p-doped first region 6.
• the primary aim By setting the gate-anode voltage, the primary aim, the change in the majority charge carrier concentration in the p-doped region 6, and the associated influence on the storage charge, also change the charge carrier concentration in the anode-side region of the n-minus-doped region 7. This also affects the storage charge of the diode, analogously to the influence in the p-doped region, i.e. Reducing the storage charge in the p-doped region 6 also results in a reduction in the storage charge in the n-minus doped region 7 and vice versa.
• the diode 9 is implemented as a trench element.
• the illustrated diode 9 according to the invention is composed of a p-doped region 6, an adjoining n-minus-doped region 7 and an n-plus adjoining the side of the n-minus-doped region 7 opposite the p-doped region 6 Region 8.
• the diode also includes the cathode, which is arranged on the n-plus-doped region 8 on the side opposite the n-minus-doped region 7 and extends over the entire side, and the anode, which on the p-doped region 6 is arranged on the side opposite the n-minus-doped region 7.
• the p-doped region 6 and the part of the n-minus-doped region adjoining the p-doped region have a significantly smaller area than the remaining region of the n-minus-doped region 7 and the adjacent n-plus-doped region 8.
• the free surface of the n-minus doped region 7 due to the reduced area and the free sides of the p-doped region 6 are completely covered by an oxide layer 4. Outside the oxide layer 4 is in the area of the transition between p doped region 6 and n-minus doped region 7 arranged the gate 5. Gate 5, oxide layer 4 and p-doped region 6 and n-minus-doped region 7 thus form a MOS contact. By applying a voltage between gate 5 and anode 2, the charge carrier concentration in the p-doped region can be reduced 6 influence. Different states of the semiconductor diode 9 can thus be set. The semiconductor diode shown is thus a MOS-controlled diode.
• Silicon can be used as the semiconductor material for all areas; the oxide layer then consists of silicon oxide.
• Anode 2, cathode 3 and gate 5 are made of metal.
• FIG. 3 shows the circuit diagram of a voltage intermediate-circuit converter, here as a half-bridge, with power semiconductors which can be switched off and semiconductor diodes according to the invention.
• the circuit diagram contains two power semiconductors which can be switched off and are denoted by T1 and T2, and two semiconductor diodes which are denoted by Dl and D2.
• FIG. 4 and 5 show an example of a possible embodiment for a control method for the voltage intermediate circuit converter shown in FIG. 3 as a circuit diagram.
• the semiconductor diodes D1 and D2 and the power semiconductors T1 and T2 that can be switched off are specified as individual components of the voltage intermediate circuit converter.
• Dl is the freewheeling diode assigned to T1
• D2 is the freewheeling diode assigned to T2.
• the two states are given, between which switching takes place in the course of the control process.
• ZI denotes the state of the semiconductor diode with low forward resistance and high storage charge
• Z2 denotes the state of the semiconductor diode with high forward resistance and low storage charge.
• the semiconductor diodes D1 and D2 have blocking capacity in both states.
• the two power semiconductors T1 and T2 that can be switched off can be switched on and off his.
• the switched-on state is designated with "on *, the switched-off state with" off * .
• the respective switching status is shown to the right in the course of time by corresponding lines.
• the control process when switching from T1 to T2 is shown in the switching phase designated by P1 and the control process when switching from T2 to Tl in the switching phase designated by P2.
• the switching times for the individual components are shown in the
• Switching phase Pl i. when switching from Tl to T2, designated in FIG. 4 with tl, t2, t3 and t4, in FIG. 5 with sl, s2, s3 and s4.
• the control process in the switching phase designated P2, i.e. when switching from T2 to T1, both in FIG. 4 and in FIG. 5 takes place in accordance with the switching process from T1 to T2 (phase P1).
• phase P1 Only the switching states of the individual components Dl and D2 as well as Tl and T2 are interchanged, i.e. the switching states of D1 in phase P2 correspond in time to the switching states of D2 in phase P1 and vice versa.
• the switching states of T1 in phase P2 correspond in time to the switching states of T2 in phase P1 and vice versa.
• the control method shown in FIG. 4 illustrates the control method already described as the first embodiment. It is provided that the switching of the semiconductor diodes D1, D2 between the first state ZI and the second state Z2 takes place in a time connection with the switching off and with the switching on of the associated switchable power semiconductors T1, T2.
• phase P1 The individual steps in phase P1 shown in FIG. 4 look as follows:
• Time t1 D1 is switched from state ZI to state Z2;
• Time t3 T2 is turned on; (4) Time t4: D2 is switched from state Z2 to state ZI.
• the two times t1 and t2 lie before the times t3 and t4 in the chronological sequence of the individual steps.
• the time t2 can be before or after the time tl.
• the time t3 can be before .0 or after the time t4 in the chronological sequence of the individual steps.
• the time sequence of the individual steps is the time t4 before the time t2.
• the time t2 can also be here before or after the time t1.
• the control method shown in FIG. 5 illustrates the control method already described as the second embodiment. It is provided that the time of switching each of the semiconductor diodes D1 and D2 between state ZI and
• 25 state Z2 is in a defined temporal connection with the switching off of the associated switchable power semiconductor T1 or T2.
• the power semiconductor T1 or T2 which can be switched off is switched on, the associated semiconductor diode D1 or D2 is not switched over.
• phase P1 The individual steps in phase P1 shown in FIG. 5 look as follows:
• Time s2 T1 is switched off; (3) Time s3: T2 is switched on; (4) Time s4: D1 is switched from state Z2 to state ZI and is thus again in the initial state.
• Dl was thus switched twice in the defined time context when Tl was switched off, while freewheeling diode D2 assigned to T2 was not switched in time connection when T2 was switched on; it is in state ZI during the entire phase P1.
• the two points in time sl and s2 lie before the points in time s3 and s4 in the chronological sequence of the individual steps.
• the time s2, however, can be before or after the time sl.
• the time s3 must be before the time s4 in the chronological sequence of the individual steps. 5 specifically applies to an example of the second embodiment sl ⁇ s2 ⁇ s3 ⁇ s4, i.e. sl is before s2, s2 is before s3 and s3 is before s4.
• the time sequence of the individual steps is the time s4 before the time s3 and the time sl before the time s2.
• the time s4 must be before the time s2 when T1 is live.

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• Microelectronics & Electronic Packaging (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
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• Ceramic Engineering (AREA)
• Computer Hardware Design (AREA)
• Electronic Switches (AREA)
• Power Conversion In General (AREA)
• Inverter Devices (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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• 2003
  • 2003-02-26 DE DE10308313A patent/DE10308313B4/de not_active Expired - Fee Related
• 2004
  • 2004-02-18 CN CNB2004800052034A patent/CN100483736C/zh not_active Expired - Fee Related
  • 2004-02-18 WO PCT/EP2004/001541 patent/WO2004077573A2/de active Search and Examination
  • 2004-02-18 JP JP2006501876A patent/JP2006519485A/ja active Pending
  • 2004-02-18 US US10/547,175 patent/US7582939B2/en not_active Expired - Fee Related
  • 2004-02-18 EP EP04712009A patent/EP1597771A2/de not_active Withdrawn

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