EP1565990A1 - Generateur de frequence - Google Patents

Generateur de frequence

Info

Publication number
EP1565990A1
EP1565990A1 EP02781335A EP02781335A EP1565990A1 EP 1565990 A1 EP1565990 A1 EP 1565990A1 EP 02781335 A EP02781335 A EP 02781335A EP 02781335 A EP02781335 A EP 02781335A EP 1565990 A1 EP1565990 A1 EP 1565990A1
Authority
EP
European Patent Office
Prior art keywords
signal
oscillator
control
value
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02781335A
Other languages
German (de)
English (en)
Inventor
Niels Christoffers
Bedrich Hosticka
Rainer Kokozinski
Peter Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP1565990A1 publication Critical patent/EP1565990A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/12—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a scanning signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/20—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it

Definitions

  • the present invention relates to frequency generators, such as those used for transceivers for UMTS, GSM or Bluetooth.
  • a central task within transceivers used for wireless data transmission is the generation of local, periodic signals that are used for frequency conversion of signals received or to be transmitted.
  • the local periodic signal generated must have different frequencies in different operating states, e.g. depending on whether there is a transmission or reception process.
  • FIG. 6 Since, according to the current state of the art, high-resolution analog / digital and digital / analog converters are available as embedded integrated circuits, the circuit structure shown in FIG. 6, consisting of a ROM memory 900, a digital / analog, would be desirable for frequency generation Converter 902 and a voltage-controlled oscillator 904. Depending on the desired transmission channel, which is to be used for data conversion or transmission for frequency conversion, a digitized control value is taken from the ROM 900. This is converted into an analog value by the digital / analog converter 902 and input into a control input of the VCO 904. The latter would then output the local periodic signal at the desired frequency by appropriately setting the digital control values stored in the EEPROM 900 in advance. 6 would be particularly desirable because the specified would change frequency almost immediately after a new channel was selected, so that only a short settling time would have to be waited before data could be transmitted or received by the transceiver containing the circuitry of FIG.
  • Possible frequency generators are constructed as shown in FIG. 1 and include a phase and frequency detector 910, a loop filter 912, a VCO 914 and a frequency divider 916.
  • a highly accurate one, of a quartz (not shown) generated reference signal S ref (t) is applied to a first input of the phase and frequency detector 910.
  • the loop filter 912 then generates a control signal S L oc (t) from the output signal S d (t) of the latter and outputs the same to the VCO 914.
  • the VCO 914 generates an output signal S out (t) with a frequency dependent on the control signal S L oc (t), which represents the output signal of the frequency generator.
  • the output signal S out (t) of the VCO 914 is converted via the frequency divider 916 into a two- feedback of the PFD 910.
  • the frequency divider 916 generates a signal with an N times lower frequency from the signal S out (t).
  • the PFD 916 compares the frequency divided signal from the frequency divider 916 with the highly accurate reference signal S ref (t) and outputs as the signal S d a signal corresponding to the phase and frequency difference, whereby a control loop through the PFD 910, the loop filter 912, the VCO 914 and the frequency divider 916 with a feedback loop from the frequency divider 916, the PFD 910 and the loop filter 912 is formed.
  • a disadvantage of the frequency divider of FIG. 7 is that the frequency divider 916 is very difficult and expensive to implement. Since it has to be dimensioned for a very high input signal bandwidth, it consumes a great deal of current.
  • Another disadvantage of the frequency generator of Fig. 7 is its high inertia. After a change in the frequency ratio N at the frequency divider 916, a long settling time elapses until the output frequency S out matches the desired one with sufficient accuracy.
  • the object of the present invention is therefore to provide a frequency generation scheme which enables less complex, more accurate and / or less sluggish frequency generation.
  • a frequency generator according to the invention comprises a controllable oscillator which has a control input and an oscillator output, the controllable oscillator being designed to output an oscillator signal at the oscillator output with an oscillator frequency which depends on a control signal at the control input, a sampling device for sampling the oscillator signal or one of the same derived signal from the controllable oscillator at a reference frequency to obtain a sampling signal and a low-pass filter for low-pass filtering the sampling signal or a signal derived therefrom to obtain the control signal or a signal underlying the control signal.
  • a method for frequency generation by means of a controllable oscillator which has a control input and an oscillator output, the controllable oscillator being designed to output an oscillator signal at the oscillator output with an oscillator frequency which depends on a control signal at the control input comprises sampling the oscillator signal or a signal of the controllable oscillator derived therefrom with a reference frequency to obtain a sampling signal, and low-pass filtering the sampling signal or a signal derived therefrom to obtain the control signal or a signal underlying the control signal.
  • a determination of the control signal-oscillator frequency characteristic of a controllable oscillator having a control input and an oscillator output is provided, the controllable oscillator being designed to output an oscillator signal with an oscillator frequency at the oscillator output depends on a control signal from the control input.
  • a sampling device samples the oscillator signal or a signal of the controllable oscillator derived therefrom with a reference frequency to get a scanning signal.
  • a low-pass filter low-pass filters the sampling signal or a signal derived therefrom to obtain an underlying signal. Means are provided to selectively prevent or enable the oscillator signal to pass through the scanner and the low pass filter to the control input.
  • control device ensures that the device for preventing or enabling subsequently enables the oscillator signal to pass through the scanning device and the low-pass filter continuously to the control input, and then the detector detects the value of the control signal which adjusts itself to enable one to obtain a control value assigned to a predetermined multiple of the reference frequency via the control signal oscillator frequency characteristic.
  • the control device also causes these processes to be repeated for different test values.
  • the present invention thus creates a completely new principle for frequency generation, which differs fundamentally from the PLL-based principle described in the introduction to the description.
  • the adjustability of the steady frequency is quickly possible, since by interrupting a feedback path comprising the scanning device and the low-pass filter between the oscillator output and the control input, rough adjustments of the control signal the transient process can be started with a roughly preset value based on a stored control value and a new closing of the feedback path. Long settling processes of a frequency divider are avoided. Due to the less complex structure, in particular the lack of a frequency divider, and the quicker adjustability of the currently generated frequency, frequency-saving frequency generation can be obtained according to the invention.
  • FIG. 1 shows a schematic block diagram of a frequency generator according to a simplified exemplary embodiment of the present invention
  • FIG. 2 shows a spectral distribution of the sampling signal obtained by sampling from the oscillator signal of the controllable oscillator of the frequency generator of FIG. 1;
  • 3a and 3b show exemplary waveforms of the oscillator signal, the scanning signal and the control signal in the frequency generator of FIG. 1 for two different steady-state or stationary states, namely for a divider ratio between the reference frequency and the oscillator frequency of two in the case of FIG 3a and one in the case of Figure 3b;
  • FIG. 4 shows a schematic block diagram of a frequency generator according to a further exemplary embodiment
  • 5 shows an exemplary control signal-oscillator frequency characteristic of a controllable oscillator
  • 6 shows a desired, ideal circuit structure for a frequency generator for generating signals with different frequencies
  • FIG. 7 is a block circuit diagram of a conventional PLL-based frequency generator.
  • FIG. 1 shows a simplified embodiment of a frequency generator according to the present invention, the frequency generator being generally indicated at 10 in FIG. 1.
  • the frequency generator 10 comprises a scanner 12, a low-pass filter 14 and a voltage-controlled oscillator (VCO) 16.
  • the voltage-controlled oscillator 16 comprises a control input and an oscillator output and outputs an output signal S out (t) with an oscillator frequency f ou t or at its oscillator output. an angular frequency ⁇ ou t, which in turn depends on the control signal, which the VCO 16 receives at the control input.
  • the output of the VCO 16 simultaneously corresponds to the output 18 of the frequency generator 10. Accordingly, the output signal S out of the VCO 16 is also the signal output by the frequency generator 10.
  • the oscillator output of the VCO 16 is also connected to an input of the scanner 12.
  • the sampler 12 samples the output signal S out from the VCO 16 at a frequency f ref and outputs a sampling signal S d (t) at its output, which is connected to an input of the low-pass filter 14.
  • the scanner 12 receives a highly accurate reference signal with the reference frequency f ref from an oscillator 20, such as a quartz oscillator, at a frequency input.
  • the scanner 12 includes, for example, a switch, such as an FET.
  • the low-pass filter 14 is connected at its output to the control input of the VCO 16, and outputs the scanning signal S d thereon in a low-pass filtered form as the control signal S L0C (t).
  • Sampler 12, low-pass filter 14 and VCO 16 together form a control loop which, as will be explained in the following, regulates the output signal S out (t) to a frequency which is in an integer ratio to the reference frequency.
  • the feedback path comprising the scanner 12 and the low-pass filter 14 between the oscillator output and the control input of the VCO 16 ensures that the control signal received by the VCO is regulated to a value which is in accordance with the control signal-oscillator frequency characteristic of the VCOs 16 corresponds to an oscillator frequency which is an integer ratio to the reference frequency.
  • the VCO 16 always produces an essentially monofequent signal at its output with a frequency which depends on the level of the control signal S L oc.
  • the sampling signal S in the frequency domain comprises a series of Dirac surges at the frequencies +/- ⁇ out + n- ⁇ ref , where n is a natural number and co ref is the angular or angular frequency of the reference signal from the Oscillator 20 is.
  • the numbers above each Dirac shock in Fig. 2 each indicate the value of n which corresponds to the respective Dirac shock.
  • the scanning signal S d the spectral representation S d in
  • the low-pass filter 14 is low-pass filtered.
  • the cut-off frequency of the low-pass filter 14 is set in such a way that only the two lowest-frequency ones of the frequency are among the Dirac surges of the scanning signal S d
  • the low-pass filter 14 has, for example, a rectangular pass function.
  • the cut-off frequency of the low-pass filter 14 is preferably ⁇ ref / 2.
  • S corresponds to 0C ( ⁇ ) thus S H ( ⁇ ) 'rect 7w 2 m UJ ref ( ⁇ ), where rect / i / 2, ⁇ -ref ( ⁇ ) is a function that is between - ⁇ ref / 2 and ⁇ ref / 2 one and otherwise zero is.
  • the resulting signal S L oc (t) is entered in the VCO 16 for control purposes or used to control the same.
  • Theoretical considerations show that the frequency generator 10 controls the control signal Soc (t) in such a way that a static state occurs in which the output frequency ⁇ out of the output signal S out (t) is N ⁇ ref , where N is an integer.
  • Both figures merely show examples of the time profiles of the signals S out / S LO c and S d in two mutually aligned graphs in which the time t along the x-axis and the voltage along the y-axis are arbitrary Units is applied.
  • the temporal profiles of the output signal S are each 0ut (solid line) and in the lower graph, the temporal "patterns of the sampling signal S (solid line) and the control signal S L oc (dashed line) ones shown, provides.
  • the samplings by the sampler 12 always take place with a constant phase difference ⁇ i or ⁇ 2 with respect to the output signal S out to be sampled.
  • the scanning by the scanner 12 always takes place at corresponding points on the, in the present case, falling edge of the sinusoidal output signal S out of the oscillator 16, namely every N-th period, the period T is.
  • the Control signal S L oc must be constant and must have a value that corresponds to the frequency ⁇ out according to the control signal oscillator frequency characteristic of the VCO 16.
  • the sampling pulses of the sampling signal S d must have a certain voltage level U ab - t ast in the static state.
  • This voltage level U a btast is determined from the fact that, in the static state, through the low-pass filtering through the low-pass filter 14, it must lead to a control signal S d (presently exaggeratedly constant) with a constant “effective value”, which is Ui or U 2
  • S d presently exaggeratedly constant
  • the output signal S 0 u t has become a little faster.
  • the signal S out assumes the value Uabt ast earlier than at the sampling time t 2 .
  • the value of S out is slightly lower. Accordingly, the value of the low-pass filtered control signal S L oc also decreases in order to become a little lower than U 2 , as a result of which the VCO 16, which has become too fast, is “braked” again due to the decreasing control signal.
  • the sampled value at time t 2 is greater than U ab t a s t? So that the effective value of the control signal S LO c resulting from the low-pass filtering also increases, as a result of which the slower VCO 16 is "accelerated” with a higher control signal.
  • the sampling times in the static state regulate themselves only to a different phase value or to different sampling times compared to the example of FIGS. 3a and 3b, at which the output signal S out has such a value that by filtering through the low-pass filter 14 results in an effective value that only corresponds to the deviation of the offset from the setpoint U x or U 2 of the control signal for the VCO 16.
  • an amplifier could be provided in the feedback path.
  • the signal generated by the low-pass filter 14 thus represents a control signal for the VCO, which, depending on the application, can still be subjected to constant manipulations, ie addition and multiplication, before it is input into the VCO.
  • the oscillator signal sampled by the sampling device and the sampling signal filtered by the low-pass filter can also have been manipulated beforehand, ie provided with an offset or an amplification.
  • FIG. 4 An exemplary embodiment of a frequency generator according to the present invention is described below with reference to FIG. 4, which is suitable for generating a selected one of predetermined oscillator frequencies, all of which have an integer division ratio to the reference frequency.
  • the frequency generator of FIG. 4 is indicated generally at 30.
  • the frequency generator 30 of FIG. 4 After the structure of the frequency generator 30 of FIG. 4 has been described above, its operation will be described below. For ease of understanding, it is assumed that the frequency generator is integrated in a transmission / reception circuit which uses different frequencies per channel for transmission during transmission and reception.
  • the control device 42 can also be part of the transmission / reception circuit (not shown).
  • a different frequency is assigned to each channel of the transceiver, which is an integral multiple of the reference frequency ⁇ ref , ie N- ⁇ ref (Ne
  • a channel assignment table is stored in the EEPROM 38, which assigns a digital value to each channel which is approximately that Corresponds to the desired value of the control signal which, according to the control signal-oscillator frequency characteristic curve, corresponds approximately to the frequency assigned to the respective channel.
  • 5 shows an example of a control signal-oscillator frequency characteristic of the VCO 16 in a graph in which the control signal is plotted in arbitrary voltage units along the x-axis and the frequency ⁇ in arbitrary Hertz units along the y-axis.
  • the characteristic curve intersects the ordinate frequency values ⁇ ref , 2 ⁇ ref and 3 ⁇ re f on the abscissa voltage values Ui, U 2 and U 3 .
  • three digital values would be stored in the EEPROM 38, namely the digitized values of Ui, U 2 or U 3 , in each case in association with the channels with the frequencies ⁇ ref , 2 ⁇ ref and 3 ⁇ re f -
  • control device 42 accesses the EEPROM 38 with the selected channel as an index, whereupon the EEPROM 38 outputs the corresponding digital value to the D / A converter 36.
  • the digital value remains unchanged or constant until the next channel change.
  • the D / A converter 36 converts the digital value into the analog voltage value S DAC and outputs the same to the second input of the adder 34.
  • control device 42 controls the sequence of the frequency generator 30 as follows: the switch 32 initially remains open in order to interrupt the feedback loop and the control loop.
  • the controller 42 selects a channel and accesses the EEPROM 38 with the selected channel as an index.
  • the digital value assigned to the selected channel corresponds, for example, to the value U 2 .
  • the D / A converter 36 uses this to generate the analog offset signal S DA C and applies the same to the second input of the adder 34. There is still no signal at the first input of the adder because the switch 32 has interrupted the feedback branch. Therefore, only the signal S DA c is present at the control input of the VCO 16.
  • the VCO 16 therefore outputs at its output an oscillator signal S ou t with a frequency ⁇ out which corresponds with an accuracy to the frequency 2 ⁇ ref , which, as has been described in the introduction to the description, by fluctuations in temperature or age is not precise enough for a transmitting or receiving operation.
  • the control device 42 closes the switch 32 and thus also the feedback path or the control loop. As described with reference to FIGS .
  • the control loop regulates the oscillator frequency ⁇ out to the nearest frequency, which has an integer ratio to the reference frequency ⁇ r ⁇ f .
  • the control loop will adjust itself to the desired frequency, namely 2 ⁇ ref , since this is the closest frequency at the start of the control process after the switch 32 is closed.
  • the output frequency of the VCO 16 after the control signal has been advanced before the switch 32 is closed is known “inaccurately”, the output frequency after the settling after the switch 32 is closed is also known. The process is repeated when the channel is changed.
  • the control device 42 first opens the switch 32, selects a new channel, and closes the switch 32 again.
  • the settling time to the new frequency is shorter than in the case of a control circuit comprising a frequency divider, as was described with reference to FIG. 7.
  • control signal oscillator characteristic of the VCO 16 is subject to changes which could lead to the fact that the formerly digitized values, such as U 3 -U 3 , differ from the target control values according to the control signal oscillator.
  • VCO 16 characteristic curve deviate. If the control signal of the VCO 16 is preset in the manner described above, these stored, digitized values deviating from the setpoints could, in their function as a starting value for the control process, result in the control loop adjusting itself to an undesired neighboring frequency which is another integer multiple is the reference frequency.
  • a dashed line 43 shows an example of a modified characteristic curve of the VCO 16, such as has arisen after a temperature change.
  • the control device 42 selects the channel which is assigned to the frequency 2 ⁇ ref
  • the VCO 16 is preset with the value U 2 , which leads to a frequency which leads to an exact lies between the frequencies 2 ⁇ ref and ⁇ ref .
  • the switch 32 is closed, it is consequently not ensured that the control loop adjusts itself to the desired frequency value 2 ⁇ re f and not to the adjacent value ⁇ re f.
  • the control device 42 determines that a renewed measurement of the control signal-oscillator frequency characteristic of the oscillator 16 is necessary, the control device 42 takes the following steps to obtain a new, for each channel or for each frequency a multiple of the reference frequency to obtain the corrected digitized value: the control device 42 opens the switch 32, selects a first of the channels to preset the VCO 16, closes the switch 32 again, waits for a certain settling time of the control loop until a static state has arisen, and then reads, using the A / D converter 40 as a detection device, a digitized value of the signal S TP , which is the deviation or the difference between the true setpoint S L oc (t) of the VCO 16 at the control input thereof and the analog control value of the DAC 36, S DAC , which has resulted from the above-mentioned characteristic fluctuation.
  • the control device 42 then corrects the value stored in the EEPROM 38 with the newly detected value, namely S L oc (t), by adding the detected value S TP to the previously stored value of S DAC .
  • the control device 42 repeats these steps for each channel or each frequency N- ⁇ re f. In this way, all the values stored in the EEPROM 38 are again adapted to the characteristic curve which may have changed. The process is also not so time-consuming, since the old stored digitized values lead to fast settling times due to their use as control start values for the control value of the VCO.
  • the control device 42 In the event that the channel generator 30 is not operated for a long time, or in the event that the frequency generator 30 the first time it is used, there are no suitable sufficiently precisely predetermined digital values in the EEPROM for the characteristic curve determination, so that the control device 42 must scan the characteristic curve of the VCO 16 by an algorithm other than that described above. In this case, the control device 42 must find, by finely varying the value output by the DAC 36, the one at which the difference between the control signal of the VCO 16 and the output voltage of the DAC 36 becomes zero, in order to digitize the latter and into the assignment table in the Filing EEPROM 38.
  • the control device 42 opens the switch 32, sets the VCO 16 in advance with a first test value S DAC , closes the switch 32 and detects the value of S TP after the required settling time.
  • the first trial value is, for example, a voltage value, wherein the control signal oscillator frequency characteristic of the VCO is the slightest changes subjected to due to ambient fluctuations *, and will thus lead to a predetermined, known Einregelfrequenz despite environmental variations with high probability. In the example of FIG. 5, this would be a value close to Ui.
  • the control device 42 stores the value of S TP + S DAC in, for example EEPROM 38 or other suitable memory. Thereafter, the control device 42 repeats this process for further test values which increase or decrease from test value to test value by, for example, a constant value.
  • the algorithm can of course also effect the variation of the test value differently, for example by changing the test value by a higher amount after a test process in which the control loop has adjusted itself to a next control value.
  • controller 42 stores the value S TP + S DAC as the next digital value for the next channel. In this way, the control device 42 receives a complete scan of the characteristic of the VCO 16 at the ordinate positions N ⁇ r ⁇ f . After the controller 42 determines all digital values for all channels, it stores them in the EEPROM 38.
  • the control device 42 can either be connected directly to the second input of the adder 34 via the DAC 36 or another DAC, or the control device 42 stores a digitized test value before each test or sampling process in a memory location specially provided for this purpose in the EEPROM 38 and then accesses the same.
  • a specially provided entry may be provided in the channel assignment table of the EEPROM 38 which does not correspond to any of the channels used by the transmission / reception circuit. In this case, it would be possible for the control device 42 to store the successively found or determined digital values directly in the EEPROM 38 for each channel.
  • the switch 32 can also be switched in the feedback path at a different location than between the oscillator output and the scanner.
  • the A / D converter 40 could also be provided in order to have its input connected to the output of the adder 34. It would also be possible to prefer the adder between the scanner and the filter.
  • the control device can be implemented in software or hardware or a combination thereof. Instead of a voltage-controlled oscillator, a current-controlled oscillator could also be used.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

La présente invention concerne un générateur de fréquence comprenant un oscillateur commandable (16) qui présente une entrée de commande et une sortie d'oscillateur. Cet oscillateur commandable (16) est conçu pour fournir un signal d'oscillateur (Sout) avec une fréquence d'oscillateur à la sortie d'oscillateur, ce signal dépendant d'un signal de commande (SLOC) à l'entrée de commande. Le générateur de fréquence comprend également un système de balayage (12) conçu pour balayer le signal d'oscillateur (Sout) ou un signal de l'oscillateur commandable (16) dérivé de celui-ci avec une fréquence de référence, afin d'obtenir un signal de balayage (Sd), ainsi qu'un filtre passe-bas (14) conçu pour assurer un filtrage passe-bas du signal de balayage (Sd) ou d'un signal dérivé de celui-ci, afin d'obtenir le signal de commande (SLOC) ou un signal (STP) basé sur le signal de commande (SLOC). Cette invention permet de produire une fréquence avec une faible consommation de courant, en raison de la construction moins complexe, notamment l'absence d'un diviseur de fréquence, et de la capacité d'adaptation plus rapide de la fréquence couramment produite.
EP02781335A 2002-11-28 2002-11-28 Generateur de frequence Withdrawn EP1565990A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2002/013455 WO2004049574A1 (fr) 2002-11-28 2002-11-28 Generateur de frequence

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EP1565990A1 true EP1565990A1 (fr) 2005-08-24

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US (1) US20050277397A1 (fr)
EP (1) EP1565990A1 (fr)
JP (1) JP2006508572A (fr)
AU (1) AU2002349049A1 (fr)
CA (1) CA2507098A1 (fr)
WO (1) WO2004049574A1 (fr)

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US7667545B2 (en) * 2008-03-04 2010-02-23 Freescale Semiconductor, Inc. Automatic calibration lock loop circuit and method having improved lock time
US7595699B1 (en) * 2008-03-04 2009-09-29 Freescale Semiconductor, Inc. Look loop circuit and method having improved lock time
FR2946488B1 (fr) * 2009-06-03 2012-05-04 St Ericsson Sa Correction de decalage de frequence
JP5171906B2 (ja) * 2010-09-13 2013-03-27 株式会社東芝 位相同期回路

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JP2006508572A (ja) 2006-03-09
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CA2507098A1 (fr) 2004-06-10
WO2004049574A1 (fr) 2004-06-10

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