EP1565825A2 - Procede et dispositif pour analyser des systemes encastres - Google Patents

Procede et dispositif pour analyser des systemes encastres

Info

Publication number
EP1565825A2
EP1565825A2 EP03782193A EP03782193A EP1565825A2 EP 1565825 A2 EP1565825 A2 EP 1565825A2 EP 03782193 A EP03782193 A EP 03782193A EP 03782193 A EP03782193 A EP 03782193A EP 1565825 A2 EP1565825 A2 EP 1565825A2
Authority
EP
European Patent Office
Prior art keywords
memory
cpu
data
analysis device
embedded system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03782193A
Other languages
German (de)
English (en)
Inventor
Adrian Traskov
Andreas Kirschbaum
Thorsten Ehrenberg
Tasso Kirsch
Burkart Voss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Continental Teves AG and Co OHG
Original Assignee
Continental Teves AG and Co OHG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Continental Teves AG and Co OHG filed Critical Continental Teves AG and Co OHG
Publication of EP1565825A2 publication Critical patent/EP1565825A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units

Definitions

  • the invention relates to an analysis device according to the preamble of claim 1, an embedded system according to the preamble of claim 12 and a method for analyzing an embedded system with an analysis device.
  • test operations can be carried out using a "boundary scan” test method.
  • This method enables processing of the processor (Smglesteppmg), the setting of breakpoints and the setting of so-called atchpoints.
  • BESTATIGUNGSKOPIE Also known is the so-called trace interface, in which the use of a bond-out chip for real-time analysis enables the forwarding of all relevant CPU bus signals (address, data and control signals) via housing pins, for example to an external logic analysis device.
  • a bond-out chip is a microcontroller (MCU) in another housing, in which the processor bus (data, address and control signals) is bonded to the outside.
  • MCU microcontroller
  • the object of the present invention is therefore to provide an analysis device for embedded systems which can also be used in the fast embedded systems which are customary today.
  • the invention is based on the following considerations: On the one hand, the internal system state of an embedded system can be described or analyzed by its current data memory content (RAM). It follows from this that if this memory content can be copied to an external data memory in real time, there is a possibility of further processing and evaluating the system state from there by a downstream evaluation unit.
  • RAM current data memory content
  • a copy of the internal system status is preferably written to an external memory in real time.
  • the analysis device is preferably part of an embedded system, which is used in particular in electronic control units for motor vehicle brake systems.
  • essential components of the system such as e.g. one or more CPU 's and memory partially or fully redundant. This increases the operational security of the embedded system.
  • the data is preferably not logged in such a way that the entire memory content or the content of an entire memory area is transmitted, but only the changes in the memory, in particular all write accesses of the CPU and / or the periphery, are transmitted. In this way, the bandwidth required for data output can be reduced.
  • the system also preferably includes means for direct data output by the CPU.
  • means for direct data output there are in particular means for automatic replication of the data in the background by the Analysis module provided. This has the advantage of increased flexibility in data output.
  • a universal data input and output module is proposed according to the invention, which is set up in such a way that data exchange with an embedded system can be carried out in real time without this (even temporarily) having to be stopped (non -intrusive).
  • the analysis device Compared to the software debugging devices known from the prior art, the analysis device according to the invention has the advantage that when developing control algorithms such. B. for motor vehicle brake systems, the dynamic system behavior, in particular the control variables can be tracked during debugging. It is also advantageous that for the use of an embedded system in a hardware-in-the-loop simulator or in a rapid prototyping system, data can be entered into the embedded system.
  • the invention further relates to a method for analyzing an embedded system described above with an analysis device according to claim 12.
  • the method has the advantage that the processing speed of the embedded system is not reduced by the debugging processes running in the background. This enables real-time processing of the data even during debugging.
  • the method according to the invention preferably also comprises steps for real-time output of the complete data storage content. Further preferred embodiments result from the subclaims.
  • FIG 1 shows an embedded system 9 with an analysis device 4 according to the invention.
  • Embedded system 9 comprises one or more CPU's 1, a RAM 3, an analysis device 4 and a debugging interface 5. To simplify the block diagram, other common functional elements of the embedded system, such as ROM, clock generation, 10, etc., are not shown ,
  • the analysis device has three functional modes, which are described below.
  • function mode 1 the analysis device also reads all write accesses of the CPU 1 from the data memory 3. All write accesses of the CPU 1 to data memory 3 are thus automatically written to the external data memory 6 via a parallel interface 5 via a parallel interface 5 by the proposed extended data output / input unit 4 (EDP, enhanced data port) via CPU bus 2.
  • EDP extended data output / input unit 4
  • the controller must have at least the same bandwidth as the memory 3 used.
  • the controller also has, in particular, a connection to the control bus and to the address bus, so that, according to a preferred embodiment of the method, only specially selected address areas and / or specially selected data types can be tracked for analysis. For the tap of the data and the As a result, data transfer does not have to be executed by CPU 1.
  • the external data memory 6 is preferably designed as a dual-port memory and generally contains an exact image of the memory areas observed in RAM 3 or of the entire memory content of RAM 3.
  • Memory 6 can also be a ring memory which receives the incoming memory Stores data stream for later (offline) analysis.
  • External interface 5 preferably has a bandwidth that is smaller than the bandwidth of the CPU bus.
  • FIFO memory 8 which is arranged within the data output unit 4, ensures that the tapped data is buffered over time. In this way, accesses to interface 5 can also be output in which a cache line or a CPU register dump is written back when the function begins.
  • analysis device 4 also reads all read accesses from CPU 1 to the data memory. This mode largely corresponds to function mode 1, but there are the following differences: All read accesses are automatically output via interface 5. Analysis unit 4 registers all processes, such as read cycles, write cycles, etc., which are visible on the CPU bus (read along). In function mode 2, CPU 1 actively performs a memory dump, which, however, is accompanied by a slight tolerable loss of runtime. By reading the analysis unit 4, the number of clock cycles that are required for the output of data words for analysis are reduced or even avoided entirely. CPU 1 reads the data memory contents into the non-drawn registers of the CPU. The data present in the registers can then be written in analysis unit 4. The mode of operation described here essentially corresponds to function mode 3 described below.
  • CPU 1 reads the data memory content into the CPU registers.
  • the data output unit 4 which overhears the data bus, automatically outputs the corresponding data, i.e. no explicit write cycle is required for data output for analysis.
  • function mode 3 there is a direct write to the data output unit or a direct read from the data output unit.
  • Function mode 3 thus corresponds to function mode 1, except for the fact that the data are actively output externally by the CPU 1 to the analysis unit 4 or actively read in from there, which, however, requires additional clock cycles.
  • the analysis unit can transmit data from the external memory 6 to typical debugging applications, such as e.g. Real-time monitoring of system status 10, offline analysis to create a complete data memory image via module 11, flash download via communication channel 12 (programming the program memory), parameter variation during operation of the embedded system, transmission of system stimuli, rapid prototyping and hardware-in-the -Loop simulation will be transmitted.
  • typical debugging applications such as e.g. Real-time monitoring of system status 10, offline analysis to create a complete data memory image via module 11, flash download via communication channel 12 (programming the program memory), parameter variation during operation of the embedded system, transmission of system stimuli, rapid prototyping and hardware-in-the -Loop simulation will be transmitted.

Abstract

L'invention concerne un dispositif pour analyser un système encastré (9) comprenant une carte UC (1), un bus de carte UC (2) et une mémoire (3). Ce système encastré comporte au moins un module de communication (4) pour l'entrée et la sortie de données d'analyse via une interface d'essai (5). Le module de communication permet de surveiller la mémoire interne et les accès entrée et sortie du système encastré et/ou d'établir un protocole à ce sujet sans faire appel à la fréquence d'horloge de la carte UC (1).
EP03782193A 2002-11-22 2003-11-12 Procede et dispositif pour analyser des systemes encastres Withdrawn EP1565825A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10254788 2002-11-22
DE10254788 2002-11-22
PCT/EP2003/012630 WO2004049159A2 (fr) 2002-11-22 2003-11-12 Procede et dispositif pour analyser des systemes encastres

Publications (1)

Publication Number Publication Date
EP1565825A2 true EP1565825A2 (fr) 2005-08-24

Family

ID=32335768

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03782193A Withdrawn EP1565825A2 (fr) 2002-11-22 2003-11-12 Procede et dispositif pour analyser des systemes encastres

Country Status (5)

Country Link
US (1) US20060150021A1 (fr)
EP (1) EP1565825A2 (fr)
JP (1) JP2006507586A (fr)
DE (1) DE10393102D2 (fr)
WO (1) WO2004049159A2 (fr)

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DE102005055229A1 (de) * 2004-11-26 2006-06-08 Continental Teves Ag & Co. Ohg Festverdrahteter elektronischer Digitalschaltkreis
DE102005020899A1 (de) * 2005-05-04 2006-11-16 Siemens Ag Verfahren und Vorrichtung zur Messung der Testabdeckung bei Multithreading-Programmen
US7725922B2 (en) * 2006-03-21 2010-05-25 Novell, Inc. System and method for using sandboxes in a managed shell
US7702400B2 (en) 2006-05-22 2010-04-20 Ideal Aerosmith, Inc. Motion controllers and simulation systems including motion controllers
EP2027514A2 (fr) 2006-05-22 2009-02-25 Ideal Aerosmith Inc. Dispositifs de commande de mouvement et systèmes de simulation comprenant des dispositifs de commande de mouvement
US7743414B2 (en) * 2006-05-26 2010-06-22 Novell, Inc. System and method for executing a permissions recorder analyzer
US7805707B2 (en) * 2006-07-21 2010-09-28 Novell, Inc. System and method for preparing runtime checks
US7739735B2 (en) * 2006-07-26 2010-06-15 Novell, Inc. System and method for dynamic optimizations using security assertions
US7856654B2 (en) * 2006-08-11 2010-12-21 Novell, Inc. System and method for network permissions evaluation
US7823186B2 (en) * 2006-08-24 2010-10-26 Novell, Inc. System and method for applying security policies on multiple assembly caches
US20080056139A1 (en) * 2006-09-06 2008-03-06 Mentor Graphics Corporation Network traffic monitoring using embedded target-side analyzer during embedded software development
JP4856023B2 (ja) * 2007-08-08 2012-01-18 パナソニック株式会社 リアルタイムウォッチ装置及びその方法
JP2010538338A (ja) * 2007-08-31 2010-12-09 エアバス オペラシオン シミュレーション・システムからの命令と診断モジュールからの命令を実行できる電子機器ボードと、それに関連するシミュレーション方法
TWI388979B (zh) * 2009-09-18 2013-03-11 Asustek Comp Inc 電腦系統及監控裝置
DE102011007437A1 (de) 2010-11-15 2012-05-16 Continental Teves Ag & Co. Ohg Verfahren und Schaltungsanrodnung zur Datenübertragung zwischen Prozessorbausteinen
CN104090833B (zh) * 2014-06-20 2016-10-05 英业达科技有限公司 服务器及其讯号解析装置
EP3227790A4 (fr) 2014-12-05 2018-12-26 Honeywell International Inc. Système de surveillance et de commande utilisant des services en nuage
CN107102921B (zh) * 2017-03-23 2020-05-12 北京航天自动控制研究所 一种面向带I/O型数字量异步端口SoC的数字量监测方法

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Also Published As

Publication number Publication date
JP2006507586A (ja) 2006-03-02
US20060150021A1 (en) 2006-07-06
WO2004049159A3 (fr) 2005-05-19
DE10393102D2 (de) 2005-07-21
WO2004049159A2 (fr) 2004-06-10

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