EP1565825A2 - Device and method for analysing embedded systems - Google Patents
Device and method for analysing embedded systemsInfo
- Publication number
- EP1565825A2 EP1565825A2 EP03782193A EP03782193A EP1565825A2 EP 1565825 A2 EP1565825 A2 EP 1565825A2 EP 03782193 A EP03782193 A EP 03782193A EP 03782193 A EP03782193 A EP 03782193A EP 1565825 A2 EP1565825 A2 EP 1565825A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- cpu
- data
- analysis device
- embedded system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims description 20
- 230000015654 memory Effects 0.000 claims abstract description 61
- 238000004458 analytical method Methods 0.000 claims abstract description 51
- 238000004891 communication Methods 0.000 claims abstract description 12
- 238000012360 testing method Methods 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 2
- 230000006870 function Effects 0.000 description 10
- 238000001514 detection method Methods 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000010223 real-time analysis Methods 0.000 description 1
- 230000010076 replication Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
Definitions
- the invention relates to an analysis device according to the preamble of claim 1, an embedded system according to the preamble of claim 12 and a method for analyzing an embedded system with an analysis device.
- test operations can be carried out using a "boundary scan” test method.
- This method enables processing of the processor (Smglesteppmg), the setting of breakpoints and the setting of so-called atchpoints.
- BESTATIGUNGSKOPIE Also known is the so-called trace interface, in which the use of a bond-out chip for real-time analysis enables the forwarding of all relevant CPU bus signals (address, data and control signals) via housing pins, for example to an external logic analysis device.
- a bond-out chip is a microcontroller (MCU) in another housing, in which the processor bus (data, address and control signals) is bonded to the outside.
- MCU microcontroller
- the object of the present invention is therefore to provide an analysis device for embedded systems which can also be used in the fast embedded systems which are customary today.
- the invention is based on the following considerations: On the one hand, the internal system state of an embedded system can be described or analyzed by its current data memory content (RAM). It follows from this that if this memory content can be copied to an external data memory in real time, there is a possibility of further processing and evaluating the system state from there by a downstream evaluation unit.
- RAM current data memory content
- a copy of the internal system status is preferably written to an external memory in real time.
- the analysis device is preferably part of an embedded system, which is used in particular in electronic control units for motor vehicle brake systems.
- essential components of the system such as e.g. one or more CPU 's and memory partially or fully redundant. This increases the operational security of the embedded system.
- the data is preferably not logged in such a way that the entire memory content or the content of an entire memory area is transmitted, but only the changes in the memory, in particular all write accesses of the CPU and / or the periphery, are transmitted. In this way, the bandwidth required for data output can be reduced.
- the system also preferably includes means for direct data output by the CPU.
- means for direct data output there are in particular means for automatic replication of the data in the background by the Analysis module provided. This has the advantage of increased flexibility in data output.
- a universal data input and output module is proposed according to the invention, which is set up in such a way that data exchange with an embedded system can be carried out in real time without this (even temporarily) having to be stopped (non -intrusive).
- the analysis device Compared to the software debugging devices known from the prior art, the analysis device according to the invention has the advantage that when developing control algorithms such. B. for motor vehicle brake systems, the dynamic system behavior, in particular the control variables can be tracked during debugging. It is also advantageous that for the use of an embedded system in a hardware-in-the-loop simulator or in a rapid prototyping system, data can be entered into the embedded system.
- the invention further relates to a method for analyzing an embedded system described above with an analysis device according to claim 12.
- the method has the advantage that the processing speed of the embedded system is not reduced by the debugging processes running in the background. This enables real-time processing of the data even during debugging.
- the method according to the invention preferably also comprises steps for real-time output of the complete data storage content. Further preferred embodiments result from the subclaims.
- FIG 1 shows an embedded system 9 with an analysis device 4 according to the invention.
- Embedded system 9 comprises one or more CPU's 1, a RAM 3, an analysis device 4 and a debugging interface 5. To simplify the block diagram, other common functional elements of the embedded system, such as ROM, clock generation, 10, etc., are not shown ,
- the analysis device has three functional modes, which are described below.
- function mode 1 the analysis device also reads all write accesses of the CPU 1 from the data memory 3. All write accesses of the CPU 1 to data memory 3 are thus automatically written to the external data memory 6 via a parallel interface 5 via a parallel interface 5 by the proposed extended data output / input unit 4 (EDP, enhanced data port) via CPU bus 2.
- EDP extended data output / input unit 4
- the controller must have at least the same bandwidth as the memory 3 used.
- the controller also has, in particular, a connection to the control bus and to the address bus, so that, according to a preferred embodiment of the method, only specially selected address areas and / or specially selected data types can be tracked for analysis. For the tap of the data and the As a result, data transfer does not have to be executed by CPU 1.
- the external data memory 6 is preferably designed as a dual-port memory and generally contains an exact image of the memory areas observed in RAM 3 or of the entire memory content of RAM 3.
- Memory 6 can also be a ring memory which receives the incoming memory Stores data stream for later (offline) analysis.
- External interface 5 preferably has a bandwidth that is smaller than the bandwidth of the CPU bus.
- FIFO memory 8 which is arranged within the data output unit 4, ensures that the tapped data is buffered over time. In this way, accesses to interface 5 can also be output in which a cache line or a CPU register dump is written back when the function begins.
- analysis device 4 also reads all read accesses from CPU 1 to the data memory. This mode largely corresponds to function mode 1, but there are the following differences: All read accesses are automatically output via interface 5. Analysis unit 4 registers all processes, such as read cycles, write cycles, etc., which are visible on the CPU bus (read along). In function mode 2, CPU 1 actively performs a memory dump, which, however, is accompanied by a slight tolerable loss of runtime. By reading the analysis unit 4, the number of clock cycles that are required for the output of data words for analysis are reduced or even avoided entirely. CPU 1 reads the data memory contents into the non-drawn registers of the CPU. The data present in the registers can then be written in analysis unit 4. The mode of operation described here essentially corresponds to function mode 3 described below.
- CPU 1 reads the data memory content into the CPU registers.
- the data output unit 4 which overhears the data bus, automatically outputs the corresponding data, i.e. no explicit write cycle is required for data output for analysis.
- function mode 3 there is a direct write to the data output unit or a direct read from the data output unit.
- Function mode 3 thus corresponds to function mode 1, except for the fact that the data are actively output externally by the CPU 1 to the analysis unit 4 or actively read in from there, which, however, requires additional clock cycles.
- the analysis unit can transmit data from the external memory 6 to typical debugging applications, such as e.g. Real-time monitoring of system status 10, offline analysis to create a complete data memory image via module 11, flash download via communication channel 12 (programming the program memory), parameter variation during operation of the embedded system, transmission of system stimuli, rapid prototyping and hardware-in-the -Loop simulation will be transmitted.
- typical debugging applications such as e.g. Real-time monitoring of system status 10, offline analysis to create a complete data memory image via module 11, flash download via communication channel 12 (programming the program memory), parameter variation during operation of the embedded system, transmission of system stimuli, rapid prototyping and hardware-in-the -Loop simulation will be transmitted.
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10254788 | 2002-11-22 | ||
DE10254788 | 2002-11-22 | ||
PCT/EP2003/012630 WO2004049159A2 (en) | 2002-11-22 | 2003-11-12 | Device and method for analysing embedded systems |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1565825A2 true EP1565825A2 (en) | 2005-08-24 |
Family
ID=32335768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03782193A Withdrawn EP1565825A2 (en) | 2002-11-22 | 2003-11-12 | Device and method for analysing embedded systems |
Country Status (5)
Country | Link |
---|---|
US (1) | US20060150021A1 (en) |
EP (1) | EP1565825A2 (en) |
JP (1) | JP2006507586A (en) |
DE (1) | DE10393102D2 (en) |
WO (1) | WO2004049159A2 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005055229A1 (en) * | 2004-11-26 | 2006-06-08 | Continental Teves Ag & Co. Ohg | Hard wired electronic digital circuit e.g. field programmable gate array, for motor vehicle`s brushless motor, has embedded system with register, where data from register and/or I/O access is logged by measuring circuit by using interface |
DE102005020899A1 (en) * | 2005-05-04 | 2006-11-16 | Siemens Ag | Method for preparing test coverage analysis involves testing of a program with several threads of error, which results e.g. from lack of synchronization between the threads with an conflicting access on common resources |
US7725922B2 (en) * | 2006-03-21 | 2010-05-25 | Novell, Inc. | System and method for using sandboxes in a managed shell |
US7702400B2 (en) | 2006-05-22 | 2010-04-20 | Ideal Aerosmith, Inc. | Motion controllers and simulation systems including motion controllers |
WO2007139733A2 (en) | 2006-05-22 | 2007-12-06 | Ideal Aerosmith Inc. | Simulation system including motion controller |
US7743414B2 (en) * | 2006-05-26 | 2010-06-22 | Novell, Inc. | System and method for executing a permissions recorder analyzer |
US7805707B2 (en) * | 2006-07-21 | 2010-09-28 | Novell, Inc. | System and method for preparing runtime checks |
US7739735B2 (en) * | 2006-07-26 | 2010-06-15 | Novell, Inc. | System and method for dynamic optimizations using security assertions |
US7856654B2 (en) * | 2006-08-11 | 2010-12-21 | Novell, Inc. | System and method for network permissions evaluation |
US7823186B2 (en) * | 2006-08-24 | 2010-10-26 | Novell, Inc. | System and method for applying security policies on multiple assembly caches |
US20080056139A1 (en) * | 2006-09-06 | 2008-03-06 | Mentor Graphics Corporation | Network traffic monitoring using embedded target-side analyzer during embedded software development |
JP4856023B2 (en) * | 2007-08-08 | 2012-01-18 | パナソニック株式会社 | Real-time watch apparatus and method |
JP2010538338A (en) * | 2007-08-31 | 2010-12-09 | エアバス オペラシオン | Electronic device board capable of executing instructions from simulation system and instructions from diagnostic module, and related simulation method |
TWI388979B (en) * | 2009-09-18 | 2013-03-11 | Asustek Comp Inc | Computer system and monitoring device |
DE102011007437A1 (en) | 2010-11-15 | 2012-05-16 | Continental Teves Ag & Co. Ohg | Method and circuit arrangement for data transmission between processor modules |
CN104090833B (en) * | 2014-06-20 | 2016-10-05 | 英业达科技有限公司 | Server and signal resolver thereof |
WO2016089416A1 (en) | 2014-12-05 | 2016-06-09 | Honeywell International Inc. | Monitoring and control system using cloud services |
CN107102921B (en) * | 2017-03-23 | 2020-05-12 | 北京航天自动控制研究所 | Digital quantity monitoring method for SoC (system on chip) with I/O (input/output) type digital quantity asynchronous port |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5771240A (en) * | 1996-11-14 | 1998-06-23 | Hewlett-Packard Company | Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin |
US6142683A (en) * | 1997-04-08 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including data steering between a processor, an input/output port, and a trace logic |
US6769076B1 (en) * | 2000-02-07 | 2004-07-27 | Freescale Semiconductor, Inc. | Real-time processor debug system |
US6732311B1 (en) * | 2000-05-04 | 2004-05-04 | Agere Systems Inc. | On-chip debugger |
US6748558B1 (en) * | 2000-05-10 | 2004-06-08 | Motorola, Inc. | Performance monitor system and method suitable for use in an integrated circuit |
JP2002163127A (en) * | 2000-11-27 | 2002-06-07 | Mitsubishi Electric Corp | Trace control circuit |
DE10119265A1 (en) * | 2001-04-20 | 2002-10-31 | Infineon Technologies Ag | Program controlled unit |
US6834360B2 (en) * | 2001-11-16 | 2004-12-21 | International Business Machines Corporation | On-chip logic analyzer |
-
2003
- 2003-11-12 WO PCT/EP2003/012630 patent/WO2004049159A2/en not_active Application Discontinuation
- 2003-11-12 EP EP03782193A patent/EP1565825A2/en not_active Withdrawn
- 2003-11-12 JP JP2004554338A patent/JP2006507586A/en not_active Withdrawn
- 2003-11-12 US US10/535,598 patent/US20060150021A1/en not_active Abandoned
- 2003-11-12 DE DE10393102T patent/DE10393102D2/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
See references of WO2004049159A2 * |
Also Published As
Publication number | Publication date |
---|---|
JP2006507586A (en) | 2006-03-02 |
WO2004049159A2 (en) | 2004-06-10 |
DE10393102D2 (en) | 2005-07-21 |
WO2004049159A3 (en) | 2005-05-19 |
US20060150021A1 (en) | 2006-07-06 |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: KIRSCH, TASSO Inventor name: VOSS, BURKART Inventor name: KIRSCHBAUM, ANDREAS Inventor name: TRASKOV, ADRIAN Inventor name: EHRENBERG, THORSTEN |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: EHRENBERG, THORSTEN Inventor name: KIRSCH, TASSO Inventor name: TRASKOV, ADRIAN Inventor name: KIRSCHBAUM, ANDREAS Inventor name: VOSS, BURKART |
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Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
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18W | Application withdrawn |
Effective date: 20070215 |