EP1554751A1 - Isolation par tranchee dans des tranches de substrat comprenant des semi-conducteurs de logique et de puissance - Google Patents

Isolation par tranchee dans des tranches de substrat comprenant des semi-conducteurs de logique et de puissance

Info

Publication number
EP1554751A1
EP1554751A1 EP03757692A EP03757692A EP1554751A1 EP 1554751 A1 EP1554751 A1 EP 1554751A1 EP 03757692 A EP03757692 A EP 03757692A EP 03757692 A EP03757692 A EP 03757692A EP 1554751 A1 EP1554751 A1 EP 1554751A1
Authority
EP
European Patent Office
Prior art keywords
trench
layers
layer
isolation
filling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03757692A
Other languages
German (de)
English (en)
Inventor
Ralf Lerner
Uwe Eckoldt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Publication of EP1554751A1 publication Critical patent/EP1554751A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H10P90/1906—
    • H10W10/061—
    • H10W10/181—
    • H10W10/014—
    • H10W10/041—
    • H10W10/17—
    • H10W10/40—

Definitions

  • the invention relates to an improved trench insulation and a production method for producing this insulation in a system composed of a substrate wafer or active silicon layer for the introduction of closely adjacent high-voltage power components and low-voltage logic elements. These trench isolations are introduced into the substrate wafer or between the active silicon regions for the power component or logic component.
  • Both components belong to the same circuit and are integrated.
  • the integration of logic elements in the low voltage range and power elements in the high voltage range on one and the same silicon circuit requires a separation of the potentials. These potentials must be insulated from one another or from one another to the extent that the maximum voltage present as a potential difference between these two potentials assigned to the active silicon regions mentioned requires.
  • One possibility is a so-called dielectric trench insulation.
  • vertical insulation between the respective component (the active silicon region) and the substrate is realized by a buried layer, which usually consists of silicon oxide (SiO 2 ).
  • Other types of insulating layers are also conceivable.
  • a laterally effective insulation is produced by a trench, in the simplest case by etching the trench between the two “active silicon regions”.
  • the trench extends as far as or into the buried, insulating layer (up to the layer) and is filled up again with insulating material. This creates the isolation barrier or trench isolation.
  • trench insulations are known in which only a part of the trench is filled with insulating material, a remaining volume being filled or filled with filling material that could also be electrically conductive.
  • Polysilicon is proposed. Due to different thermal expansion coefficients of the materials usually used, such as silicon active layer, SiO 2 as insulator and polysilicon as filler layer, the thickness of the insulating layer cannot be as large as desired. Due to the different thermal expansion, there would otherwise be an intolerable bending of the silicon wafer, which would impair its processability to such an extent that it could hardly be realized. For these reasons, the thickness of the insulating layer in the trenches of the prior art is limited.
  • the invention is based on the object of saving expensive chip area (wafer area) and reducing the trench width (overall width) of an insulating trench system. At the same time, the reliability of the trench insulation against laterally applied high voltages is to be increased.
  • the stated problem is solved as a technical problem in that an alternating sequence of a plurality of insulator layers and filler layers is arranged in a widened trench, the composition of the layers (filler layers and insulator layers) being selected such that the trench region is suitable averaged over all layers results in a total thermal expansion that is close to that thermal expansion that the semiconductor wafer, as a rule has the silicon (claim 1, claim 9, claim 10).
  • the available multiple filler layers and several insulator layers make it possible to adjust the thermal expansion of the overall structure in the trench and to at least approximate the thermal expansion of the silicon as the preferred semiconductor. In other words, the thermal expansion capability of the trench filled with the vertical layer sequence and of the surrounding semiconductor are essentially the same, in any case are so close that there is no harmful bending of the substrate wafer (claim 5).
  • Layers of silicon oxide or SiN can be used as the insulating layer (claim 2). Layers which have polysilicon in their basic substance can be used as filler layers (claim 3).
  • the insulating layers in the trench can preferably consist of different materials (claim 21).
  • the filling of this trench corresponds to the structure according to the invention (claim 1, claim 9).
  • the manufacture results from the successive introduction of layers which lie essentially vertically or parallel to the trench walls and which consist of more than two insulating layers and at least two, preferably also more filling layers. In the case of two opposite trench walls, an even number of insulating layers are provided and an odd number of filling layers, which results in the sequence of insulating layers and filling layers which alternate with one another. This alternating sequence of layers offers the possibility of better adaptation of the thermal expansion to that of the silicon wafer or the material silicon. If another semiconductor material is provided for the pane, the invention is correspondingly too transferred to the other semiconductor crystal or the other semiconductor material that is used as a substrate.
  • the procedure can be such that the trench is first created with the aid of a structured photo lacquer layer, for example by plasma etching.
  • the designation or terminology is based on this trench.
  • a first insulating layer, for example made of SiO 2 is then introduced by, for example, a CVD process or by thermal oxidation.
  • a first filling layer is then deposited between the insulating layers formed, for example also by means of a CVD process.
  • the first filling layer which occupies the space between the two insulating layers and initially completely fills the trench, is deposited, a part of this layer is removed again in order to expose a section of the bottom of the trench, which preferably consists of the buried insulating layer, which is used for vertical insulation of the opposite active silicon areas.
  • the filling layer on the bottom is removed to the extent that a new, narrower trench is created, which can be used again to accommodate further insulation layers, which are deposited or grown vertically on the newly formed walls of the narrowed trench.
  • a conductive channel at the bottom of the trench is prevented, which would short circuit the subsequently applied insulating layers.
  • Removing the portion of the fill layer can e.g. can be easily achieved by a conventional, anisotropically attacking etching process. With this anisotropic etching process, the filling layer on the surface of the silicon wafer can also be removed.
  • an oxide which serves to apply the further insulating layer, which as such extends both on the horizontal extent and also into the newly created, narrowed trench.
  • the further insulating layer which as such extends both on the horizontal extent and also into the newly created, narrowed trench.
  • it forms two parallel layer sections, which are essentially vertical, that is to say parallel to the trench walls.
  • the introduction of this further insulating layer, based on the trench walls, the introduction of the two opposite sections of insulating layers, also referred to as “layers”, can be produced by thermal oxidation of the polysilicon which is exposed on the inside (as opposing layers).
  • the newly formed oxide layer which also extends in the horizontal direction above the trench, can take on a further function. It can be used as a stop layer for a final leveling of the surface or a smoothing.
  • this smoothing or leveling only takes place after a further filler layer has been filled in between the last formed, essentially vertical trench walls and on the current trench walls, which are again closer to one another, in a similar manner as previously described (Chemical Vapor Deposition, CVD). If it also reaches a horizontal extent above the trench, this extent can be removed by the ablation process during the leveling, if necessary also with the stop layer underneath, whereby the etching rate is greatly reduced as a result of the ablation process when smoothing through the stop layer.
  • CVD Chemical Vapor Deposition
  • this insulation oxide layer can finally be removed in a conventional way, so that the layer sequence in the trench is immediately visible and the alternating sequence of alternating electrically insulating insulation layers and filling layers takes up the entire original trench width to create an increased one Insulation strength in an original trench widened compared to the prior art.
  • the order in which the layers are introduced can also be reversed, starting with the filling layer, opening (limiting) it and then inserting insulator layers on the inner walls of the (wide) limited filling layers.
  • FIG. 1 is a cross section through a known isolation trench arrangement as trench isolation with three layers running vertically in the trench.
  • the isolating trench is symbolically highlighted with 8 in a circle.
  • FIG. 2 is a cross section through a first step of an exemplary embodiment of the invention, in the stage after a first filling layer has been introduced.
  • Figure 3 is a further stage of the manufacturing process at the stage after
  • Figure 4 is a further step of the manufacturing process in the post-stage
  • FIG. 5 is a cross section through the trench arrangement after a further step of the manufacturing process, namely that of the planarization of the surface.
  • a buried, electrically insulating layer 2 for example made of silicon oxide (SiO 2 ), as a "buried oxide” (box).
  • Two active silicon regions at a first potential 1 and a second potential 2 are denoted by 6, 7, wherein they can be provided for a low-voltage logic element in region 6 and a high-voltage power element in region 7. They are provided in an active silicon layer 3, only a section of the wafer being shown in order to clarify the arrangement and structure of the trench 8 (trench).
  • They can be an integral part of a circuit made in silicon (“silicon circuit”), which is not shown separately.
  • FIG. 2 illustrates a stage of the formation of an isolation trench or a trench isolation, in which several process steps have already been carried out, but which are readily apparent from the result shown.
  • substrate wafer 1 for example silicon
  • the buried electrically insulating layer 2 for example SiO 2 as box
  • the active silicon layer 3 above it as “device wafer”.
  • active silicon region of the first potential which is denoted by 6 on the left
  • second active silicon region which is denoted by 7 on the right, which, after completion of the semiconductor and in operation, will be at different potentials which are to be isolated from one another.
  • a first trench T was already introduced in FIG. 2 between the two active silicon regions 6, 7, which has the width which can be seen from the trench bottom B, the trench T extending as far as the buried electrically insulating layer 2.
  • the trench can have been produced with the aid of a structured photoresist layer by plasma etching.
  • a first insulating layer must be introduced in succession, for example made of SiO 2 , for example using a CVD process or thermal oxidation. This insulating layer is designated 4c in the horizontal portion (on the active silicon regions 6, 7) and is shown opposite in the two vertical portions, which cover the original trench walls, as layers 4a, 4b, which extend to the trench bottom B, from the surface the buried insulating layer 2 is formed.
  • a first filler layer has been formed, which is symbolically designated 5, for example also by means of a CVD method.
  • the deposition filled up the entire trench T between the two insulating layers 4a, 4b and covers the bottom surface of the remaining trench bottom B0, which has a width that corresponded to the original width of the bottom B, minus the thicknesses of the two insulating layers 4a, 4b.
  • the filler layer 5 was removed to the bottom of the trench, whereby an opening is created which is again named T in FIG. 2 as a new trench which is open at the top. This can prevent a conductive channel on the trench bottom B1 would short circuit subsequent insulation layers. This can be achieved, for example, by a conventional anisotropically attacking etching process.
  • FIG. 2 Shown in FIG. 2 is a delimitation of the first introduced filler layer 5, so that two lateral surface sections 5a, 5b result as layers that are shown to run parallel to the original and new trench walls. Their width is smaller - seen in total - than the original width of the filling layer 5.
  • the original filling layer 5 is therefore no longer present in an area of the trench floor, which is now designated B1, this new trench floor B1 being smaller (narrower) than the previous trench floor BO and also smaller than the original trench floor B.
  • the width ratios the respective bottoms of T can easily be read from FIG. 2.
  • FIG. 3 shows a cross section at a further stage in the production process, after the introduction of a second insulating layer.
  • the second insulating layer contains several sections, two horizontal sections 9a ', 9b' and two vertical sections 9a, 9b.
  • the horizontal sections adjoin the previous horizontal insulating layer 4c and lie above the filler layers 5a, 5b from FIG. 2, alternatively they are oxidized a bit into these filler layers, as are the vertical layers 9a, 9b in the trench, which are also a bit far may have been oxidized into the filling layer 5a, 5b from FIG. This reduces the height and the width of the filler layers 5a, 5b shown in FIG.
  • the second insulating layer is applied by this further oxide deposition 9a ', 9a, 9b, 9b'.
  • the oxidation is a thermal oxidation of the polysilicon used, for example, for the first filling layer with its remaining layers 5a, 5b.
  • a second filling layer 10, 10a, 10b is provided, which can also have polysilicon.
  • This filler layer has horizontal portions 10a, 10b above the aforementioned insulator layer 4c, 9a ', 9b', and a vertical section 10 which completely fills the trench residue, so that the entire trench T has been filled.
  • An insulator layer is arranged under the horizontal section of the second filling layer, that is to say the surface to be covered, this can be used as a stop layer for a final surface leveling or such smoothing. The stop layer ensures that an erosion process during the smoothing process drops sharply in its etching rate.
  • the second insulator layer 4c, 9a ', 9b' can also be removed in a known (usual) way, so that a stage of the manufacturing process is reached, which is represented in FIG. 5.
  • the isolation trench structure after the planarization is shown, with an alternating sequence of isolation layers and filler layers, which are each arranged vertically in the trench and have a width that is smaller than the original trench width of the original trench floor B according to FIG. 2. It is striking that an odd number of filling layers is provided and an even number of insulating layers. There are at least seven alternating layers.
  • the dependence on the voltage to be blocked later determines the width of the trench on the one hand and the number of layers used (insulating layer and fill layer) on the other.
  • the last filling layer 10 introduced inside the trench is opened from above until it is no longer present on a trench floor that has a smaller lateral extent than the trench floor that existed before the filling layer was introduced.
  • the layers in an alternating sequence of filling layer, insulating layer, filling layer, ... can have different thicknesses (in the trench transverse direction), depending on the width of the trench. They can also have different substances, for example the insulating layers made of silicon oxide and / or silicon nitride, SiN. It is understood from the sequence of figures in FIGS. 2 to 4 that, in each case, the exposed trench floor, starting from the original width via the trench floor sections, BO, B1,... Is reduced further and further until the trench floor is completely covered by the last filling layer 10 introduced on the inside. In this connection, the trench T is reduced piecewise in its width.
  • the trench T which has different trench widths (x-direction) in the course of the manufacturing process, and accordingly also different widths of the trench floor which is in each case exposed.
  • the trench walls are also each other, which approach each other in the course of the process steps in order to take up new vertical layers, which are created either by an insulator layer or by introducing a filler layer and subsequently delimiting this filler layer.
  • Two further insulator layers are introduced with each new process sequence according to FIGS. 2, 3 and 4 and one further filler layer in each case.
  • Each delimitation extends to the bottom of the trench formed by the box layer, and the new trench walls are located further to the center of the trench than the previously existing trench walls which were covered with the previous insulator layers.

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  • Element Separation (AREA)

Abstract

La présente invention concerne un système en couches (4b, 5b, 9b, 10, 9a, 5a, 4a) situé à l'intérieur d'une tranchée d'isolation (trench) afin d'assurer une isolation de circuits avec peu de déformation et d'assurer une isolation électrique de composants de puissance haute tension (7) par rapport à des éléments de puissance basse tension (6) qui sont intégrés sur la même puce (1, 2, 3). La présente invention concerne également un procédé de production au moyen de couches verticales successives dans la tranchée (T). Cette invention permet d'améliorer la rigidité diélectrique pour des hautes puissances et d'inhiber l'influence de défauts induits par des déformations des tranches de substrat.
EP03757692A 2002-10-08 2003-10-08 Isolation par tranchee dans des tranches de substrat comprenant des semi-conducteurs de logique et de puissance Withdrawn EP1554751A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10246949A DE10246949B4 (de) 2002-10-08 2002-10-08 Verbesserte Trench-Isolation und Herstellungsverfahren
DE10246949 2002-10-08
PCT/DE2003/003332 WO2004034462A1 (fr) 2002-10-08 2003-10-08 Isolation par tranchee dans des tranches de substrat comprenant des semi-conducteurs de logique et de puissance

Publications (1)

Publication Number Publication Date
EP1554751A1 true EP1554751A1 (fr) 2005-07-20

Family

ID=32038344

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03757692A Withdrawn EP1554751A1 (fr) 2002-10-08 2003-10-08 Isolation par tranchee dans des tranches de substrat comprenant des semi-conducteurs de logique et de puissance

Country Status (5)

Country Link
US (1) US7271074B2 (fr)
EP (1) EP1554751A1 (fr)
AU (1) AU2003273747A1 (fr)
DE (2) DE10246949B4 (fr)
WO (1) WO2004034462A1 (fr)

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US20070224772A1 (en) * 2006-03-21 2007-09-27 Freescale Semiconductor, Inc. Method for forming a stressor structure
US8304322B2 (en) * 2006-04-18 2012-11-06 Micron Technology, Inc. Methods of filling isolation trenches for semiconductor devices and resulting structures
DE102006031539B4 (de) * 2006-07-07 2011-09-29 Infineon Technologies Austria Ag Integrierter Halbleiterchip mit lateraler Wärmedämmung und Substratkontakt
US7705440B2 (en) * 2007-09-07 2010-04-27 Freescale Semiconductor, Inc. Substrate having through-wafer vias and method of forming
KR100971532B1 (ko) * 2008-05-27 2010-07-21 삼성전자주식회사 구동 트랜지스터를 포함하는 반도체 소자

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Also Published As

Publication number Publication date
AU2003273747A1 (en) 2004-05-04
US20070105338A1 (en) 2007-05-10
WO2004034462A1 (fr) 2004-04-22
US7271074B2 (en) 2007-09-18
DE10246949B4 (de) 2012-06-28
DE10393917D2 (de) 2005-08-25
DE10246949A1 (de) 2004-04-22

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