EP1487012A2 - Verfahren zur Herstellung einer Heterogenen struktur und eine damit erzeugte Struktur - Google Patents

Verfahren zur Herstellung einer Heterogenen struktur und eine damit erzeugte Struktur Download PDF

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Publication number
EP1487012A2
EP1487012A2 EP04291267A EP04291267A EP1487012A2 EP 1487012 A2 EP1487012 A2 EP 1487012A2 EP 04291267 A EP04291267 A EP 04291267A EP 04291267 A EP04291267 A EP 04291267A EP 1487012 A2 EP1487012 A2 EP 1487012A2
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EP
European Patent Office
Prior art keywords
substrate
substrates
layer
assembly
silicon
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04291267A
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English (en)
French (fr)
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EP1487012A3 (de
Inventor
Muriel Martinez
Alice Boussagol
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Soitec SA
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Soitec SA
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Publication date
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Publication of EP1487012A2 publication Critical patent/EP1487012A2/de
Publication of EP1487012A3 publication Critical patent/EP1487012A3/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Definitions

  • the invention relates to the field of heterogeneous structures, combining two substrates with different coefficients of thermal expansion.
  • Such a structure is shown schematically in the figure 1, comprises a substrate 12 having a first coefficient of expansion thermal and a film or layer 15 having a second coefficient of thermal expansion.
  • quartz system on silicon which can be used in optical applications, such as realization of screens.
  • silicon on sapphire or silicon on glass or carbide system silicon on glass or germanium on glass or germanium on silicon.
  • silicon has a coefficient of thermal expansion of 3.59. 10 -6 / C, and quartz 6.10 -7 / C.
  • temperature rise phases can take place, for example to strengthen the bonding interface.
  • the variations in behavior of one of the two substrates by relation to the other can then result in a break of at least one of the two substrates, by a phenomenon of relaxation of constraints, and this as soon as the temperature reaches a few hundred degrees (for example a temperature between 200 ° C and 600 ° C).
  • variations in temperature may, due to the differences coefficient of thermal expansion, cause stress, but also delamination or detachment of substrates or layers in presence, and / or plastic deformations and / or fractures and / or a breakage of one or more substrates or layers present.
  • a ion implantation is first performed in a substrate 10, from from which layer 15 will be produced. This implantation forms a thin weakened layer 13 which extends substantially parallel to the surface 16 of substrate 10.
  • the two substrates 10 and 12 thus prepared are of thickness comparable or similar. They are then assembled, face 16 against face 18, by a “wafer bonding” type technique or by contact-type contact or by molecular bonding and / or by bonding anodic.
  • a pre-baking is then carried out at a given temperature and at thermal limit budget, lower than the budget allowing to realize a thermal fracture of the substrate 10.
  • the thermal budget is in fact given by the product of the duration of the heat treatment by the temperature of the heat treatment.
  • the detachment of the substrate 10 is carried out mechanically, by example using a blade that provides additional energy necessary.
  • thinning of the substrate 10 is achieved mechanically and / or chemical.
  • Mechanical thinning is achieved by lapping and polishing.
  • Chemical thinning uses a product such as TMAH (Tetramethyl-ammonium-hydroxide).
  • anodic deposition on a substrate, for example a glass substrate, used as an anode.
  • This process allows bonding at a temperature data which then activates the transfer process to temperatures lower than that required by molecular bonding and eliminate thermal stress in layers.
  • This process makes it possible to produce a layer of the first material on the substrate of the second material, the substrate consisting of the third material is then removed.
  • the fracture made in the thickness of the first substrate can be a thermal type fracture, for example at a temperature included between 250 ° C and 600 ° C.
  • a step of temperature rise for example, up to more than 900 ° C, for reinforce the assembly of the first and second substrates.
  • the use of the third substrate on either of the two substrates significantly reduce the curvature generated due to the differences in the coefficients of thermal expansion between the first and second substrate. This concerns, in particular, the curvatures generated during a rise in temperature to achieve the fracture of the two substrates or to improve the quality of the contact between the first and second substrates.
  • the third substrate has a thickness such that the sum of the thicknesses of the third substrate and of the substrate against which it is positioned is greater than the thickness of the substrate against which it is not positioned. If the third substrate, and the one against which it is positioned, are made of quartz, we can use a total thickness between 700 ⁇ m and 1200 ⁇ m or between 1800 ⁇ m and 2500 ⁇ m.
  • FIGS. 3A to 3C A first embodiment of the invention will be given in connection with FIGS. 3A to 3C.
  • the reference 20 designates a first substrate, in a first material, and the reference 22 a second substrate, (thickness between 500 ⁇ m and 1200 ⁇ m) in a second material, with a thermal expansion coefficient different from the first, the relative difference between the two coefficients being for example greater than or equal to about 10% or 20% at room temperature.
  • the first substrate is made of silicon and the second is quartz.
  • an atomic implantation or ionic is produced in the substrate 20, forming a layer 23 constituting an area of weakness or fracture.
  • the volume of the substrate 20 is therefore separated into a lower region 25 (of thickness included between 50 nm and 500 nm) intended to constitute the layer to be formed on the material 22, and an upper region 24 constituting the mass of the substrate 20.
  • the implantation is a hydrogen implantation, but can also be carried out using other species, or with a co-location of two species, for example hydrogen / helium.
  • a weakening or fracture layer or plane 23 can also be achieved by forming a porous layer, as by example described in the article by K. Sataguchi et al. «ELTRAN by Splitting Porous Si Layers ”, Proceedings of the 9th Int. Symposium on Silicon-on-Insulator Tech. and Device, 99-3, The Electrochemical Society, Seattle, p.117 - 121 (1999).
  • the two substrates 20 and 22 thus prepared are then assembled, face 16 against face 18, by a “wafer” type technique bonding "(assembly of slices by any technique known in the art microelectronics) or by adherent type contact or by molecular bonding or by a chemical process (one of the two is activated surfaces to make it hydrophilic or hydrophobic), or by surface activation by polishing.
  • the two substrates are placed simple contact, mechanically assisted to reduce the distance between two substrates and initiate adhesion.
  • Such techniques are by example described in the book by Q.Y. Tong and U. Gösele “Semiconductor Wafer Bonding” (Science and Technology), Wiley Interscience Publications.
  • the substrate 22 is then brought into contact and assembled with a substrate 26, of thickness such as the sum of the thicknesses of the substrates 22 and 26 is greater than the thickness of the substrate 20.
  • the assembly takes place for example by molecular adhesion or else using glue.
  • the coefficient of expansion of this substrate 26 is close to that of substrate 22, the relative difference between their coefficients of expansion thermal being less than 10% at room temperature.
  • the substrate 26 is made of a material identical to that of the substrate 22, both are for example made of quartz.
  • the part 24 of the substrate 20 is removed, for example by heat treatment and / or by application of mechanical stress (blade or jet of water under pressure) causing a fracture along the embrittlement plane 23.
  • Treatment thermal implements a rise in temperature for example between 350 ° C and 500 ° C or 650 ° C.
  • the substrate 26 keeps the system flat and avoids curvatures of the two substrates 20 and 22, despite the differences between the coefficients of thermal expansion of substrate 20 and substrate 22 during of this temperature rise, and despite the fact that layer 25 then absorbs more stresses than in the absence of a counter plate 26 of quartz.
  • the assembled structure 25-substrate thin layer 22 could break during the transfer of this thin layer 25 on this substrate 22.
  • risk of separation at the bonding interface between the two substrates 20 and 22 risk of detachment also linked to stresses and bends induced due to differences in coefficients of thermal expansion.
  • the substrate 26 is then separated from the assembly constituted by the layer 25 deposited or formed on the substrate 22 (FIG. 3C).
  • the substrates 26 and 22 were assembled by adhesion molecular, their separation can be achieved through the insertion of a blade at the interface of the two substrates. If they are assembled by glue we may use a solvent to separate them.
  • the part 24 of the substrate 20 can then be recovered to be reused, and this although the initial structure is heterogeneous.
  • the layer 25 has qualities (absence of plane of slippage or dislocation in the material) greater than that of layers obtained by the known techniques already described.
  • the layer 25 has on its surface a thin oxide layer, for example with a thickness between 50 nm and 400 nm.
  • the function of the substrate 26 remains similar to what has been described above.
  • FIG. 4 represents a variant, in which the substrate 26 is positioned (for example by molecular adhesion or using glue) on the substrate 20 before assembly with the substrate 22. Again, the substrate 26 prevents expansion and deformation due to differences coefficient of thermal expansion between substrates 20 and 22. The sum of the thicknesses of the substrates 26 and 20 is preferably greater or much greater than that of the substrate 22. The coefficients of thermal expansion of the substrates 20 and 26 are close to one of the other, in the sense already indicated above (relative deviation less than 10%).
  • the substrate 26 has a coefficient of close expansion identical to that of substrate 20.
  • the substrate 26 will for example itself be a substrate made of silicon and will be deposited on the side of substrate 20.
  • the use of the plate 26 makes it possible to use a substrate 22 thicker than the usual thicknesses.
  • a quartz substrate 22 of similar thickness or equal to 800 ⁇ m undergoes a break during the heat treatment allowing the transfer of the layer 25 from the substrate 20. It is then necessary to use substrates of thickness substantially equal to 1000 ⁇ m, or more.
  • the invention makes it possible to use substrates of lower thickness, less than 800 ⁇ m, in particular between 500 ⁇ m and 800 ⁇ m, for example quartz substrates with a thickness of 525 ⁇ .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Combinations Of Printed Boards (AREA)
EP04291267A 2003-06-11 2004-05-18 Verfahren zur Herstellung einer Heterogenen struktur und eine damit erzeugte Struktur Withdrawn EP1487012A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0307027 2003-06-11
FR0307027A FR2856192B1 (fr) 2003-06-11 2003-06-11 Procede de realisation de structure heterogene et structure obtenue par un tel procede

Publications (2)

Publication Number Publication Date
EP1487012A2 true EP1487012A2 (de) 2004-12-15
EP1487012A3 EP1487012A3 (de) 2005-11-16

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EP04291267A Withdrawn EP1487012A3 (de) 2003-06-11 2004-05-18 Verfahren zur Herstellung einer Heterogenen struktur und eine damit erzeugte Struktur

Country Status (4)

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US (1) US6858517B2 (de)
EP (1) EP1487012A3 (de)
JP (1) JP4800593B2 (de)
FR (1) FR2856192B1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1873823A1 (de) * 2006-06-26 2008-01-02 SUMCO Corporation Verfahren zur Herstellung eines gebundenen Wafers
FR2942911A1 (fr) * 2009-03-09 2010-09-10 Soitec Silicon On Insulator Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique
US9136113B2 (en) 2009-01-22 2015-09-15 Soitec Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type

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US7772088B2 (en) * 2005-02-28 2010-08-10 Silicon Genesis Corporation Method for manufacturing devices on a multi-layered substrate utilizing a stiffening backing substrate
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US20070029043A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
US7427554B2 (en) * 2005-08-12 2008-09-23 Silicon Genesis Corporation Manufacturing strained silicon substrates using a backing material
US7268051B2 (en) * 2005-08-26 2007-09-11 Corning Incorporated Semiconductor on glass insulator with deposited barrier layer
JP5041714B2 (ja) * 2006-03-13 2012-10-03 信越化学工業株式会社 マイクロチップ及びマイクロチップ製造用ｓｏｉ基板
US7863157B2 (en) * 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
EP2002484A4 (de) 2006-04-05 2016-06-08 Silicon Genesis Corp Verfahren und struktur für die herstellung von solarzellen mittels schichtübertragungsverfahren
US8153513B2 (en) * 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
FR2919960B1 (fr) 2007-08-08 2010-05-21 Soitec Silicon On Insulator Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation
US20090206275A1 (en) * 2007-10-03 2009-08-20 Silcon Genesis Corporation Accelerator particle beam apparatus and method for low contaminate processing
US7781308B2 (en) * 2007-12-03 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
FR2942910B1 (fr) * 2009-03-06 2011-09-30 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneur
US8216945B2 (en) * 2009-04-09 2012-07-10 Texas Instruments Incorporated Wafer planarity control between pattern levels
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
FR2948318B1 (fr) * 2009-07-22 2011-08-19 Commissariat Energie Atomique Procede de realisation d'un dispositif a element graphique
JP5866088B2 (ja) * 2009-11-24 2016-02-17 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
WO2013011415A1 (en) * 2011-07-15 2013-01-24 Koninklijke Philips Electronics N.V. Method of bonding a semiconductor device to a support substrate
EP2960925B1 (de) 2013-02-19 2018-04-25 NGK Insulators, Ltd. Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements
JP6371143B2 (ja) * 2014-07-08 2018-08-08 イビデン株式会社 ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び黒鉛炭化珪素複合基板
JP6371142B2 (ja) * 2014-07-08 2018-08-08 イビデン株式会社 ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び炭化珪素複合基板
CN110838463A (zh) * 2018-08-17 2020-02-25 胡兵 一种半导体衬底、将衬底层与其上功能层分离的方法
FR3042647B1 (fr) * 2015-10-20 2017-12-01 Soitec Silicon On Insulator Structure composite et procede de fabrication associe
FR3068508B1 (fr) 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
CN111834520B (zh) * 2020-06-29 2021-08-27 中国科学院上海微系统与信息技术研究所 一种表面均匀性优化的压电单晶薄膜制备方法
CN113394338A (zh) * 2021-04-28 2021-09-14 上海新硅聚合半导体有限公司 一种异质单晶薄膜的制备方法及异质单晶薄膜
CN117597008A (zh) * 2024-01-19 2024-02-23 苏州达波新材科技有限公司 一种改善注入晶圆翘曲的方法和压电单晶薄膜及其制备方法

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EP0703609A1 (de) * 1994-09-22 1996-03-27 Commissariat A L'energie Atomique Verfahren zur Herstellung einer Struktur mit einer dünnen Halbleiterschicht auf einem Substrat
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1873823A1 (de) * 2006-06-26 2008-01-02 SUMCO Corporation Verfahren zur Herstellung eines gebundenen Wafers
US7507641B2 (en) 2006-06-26 2009-03-24 Sumco Corporation Method of producing bonded wafer
US9136113B2 (en) 2009-01-22 2015-09-15 Soitec Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type
FR2942911A1 (fr) * 2009-03-09 2010-09-10 Soitec Silicon On Insulator Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique
WO2010102686A1 (en) * 2009-03-09 2010-09-16 S.O.I.Tec Silicon On Insulator Technologies A method of producing a heterostructure with local adaptation of the thermal expansion coefficient
US8754505B2 (en) 2009-03-09 2014-06-17 Soitec Method of producing a heterostructure with local adaptation of the thermal expansion coefficient

Also Published As

Publication number Publication date
US6858517B2 (en) 2005-02-22
US20040253795A1 (en) 2004-12-16
JP2005005708A (ja) 2005-01-06
FR2856192B1 (fr) 2005-07-29
EP1487012A3 (de) 2005-11-16
FR2856192A1 (fr) 2004-12-17
JP4800593B2 (ja) 2011-10-26

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