EP1467377B1 - Leseverfahren eines nichtflüchtigen Halbleiterspeichers und zugehörige Vorrichtung - Google Patents

Leseverfahren eines nichtflüchtigen Halbleiterspeichers und zugehörige Vorrichtung Download PDF

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EP1467377B1
EP1467377B1 EP03425224A EP03425224A EP1467377B1 EP 1467377 B1 EP1467377 B1 EP 1467377B1 EP 03425224 A EP03425224 A EP 03425224A EP 03425224 A EP03425224 A EP 03425224A EP 1467377 B1 EP1467377 B1 EP 1467377B1
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Prior art keywords
cell
current
latch
memory cells
memory
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French (fr)
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EP1467377A1 (de
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Daniele Vimercati
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STMicroelectronics SRL
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STMicroelectronics SRL
SGS Thomson Microelectronics SRL
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Priority to DE60317768T priority Critical patent/DE60317768T2/de
Priority to EP03425224A priority patent/EP1467377B1/de
Priority to US10/820,458 priority patent/US7054197B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Definitions

  • the present invention relates to a method for reading a nonvolatile memory device and to a nonvolatile memory device implementing the reading method.
  • a logic state is stored by programming the threshold voltage of the memory cells through the definition of the amount of electrical charge stored in the floating-gate region.
  • two-level memory cells are distinguished between erased memory cells (logic value stored "1"), wherein the floating-gate region does not store any electrical charge, and written or programmed memory cells (logic value stored "0"), wherein the floating-gate region stores an electrical charge sufficient for determining a sensible increase in the threshold voltage of the memory cells.
  • Reading of two-level memory cells is performed by comparing an electrical quantity correlated to the current flowing through the memory cells with a similar electrical quantity correlated to the current flowing through a reference memory cell of known contents.
  • the gate terminal of the memory cell is fed with a reading voltage having a value comprised between the threshold voltage of an erased memory cell and the threshold voltage of a written memory cell, so that, if the memory cell is written, the reading voltage is lower than its threshold voltage and consequently no current flows in the memory cell, while if the memory cell is erased, the reading voltage is higher than its threshold voltage and current flows in the cell.
  • n -bit data In multilevel memory cells, storage of n -bit data requires, instead, programming of threshold voltages that may assume 2 n different values, each associated to a respective n-bit datum, while reading of multilevel memory cells is performed by comparing an electrical quantity correlated to the current flowing through the memory cells with 2 n distinct reference intervals (defined by 2 n-1 distinct reference levels), each associated to a respective n -bit datum, and then by determining the datum associated to the range of values within which the electrical quantity is comprised.
  • the multilevel approach may be applied both to volatile memories (such as DRAMs) and to nonvolatile memories (such as EEPROMs and flash memories).
  • volatile memories such as DRAMs
  • nonvolatile memories such as EEPROMs and flash memories.
  • the increase in the number of bits per memory cell renders more critical the tolerance to disturbance, retention of information, and accuracy of reading and writing operations.
  • Figure 1 shows for example a graph representing the current flowing in a multilevel memory cell storing two bits and the reference currents defining reference intervals used for reading the contents of the memory cell.
  • Figure 1 shows with dashed line the current I CELL flowing in a memory cell storing the bits "10", and a solid line represents the three reference currents I REF1 , I REF2 , I REF3 that define the four reference intervals.
  • Figure 1 also represents the two bits associated to each of the four reference intervals and, with a dashed-and-dotted line, the current flowing in a virgin cell, which, as known, is higher than the highest reference current (I REF3 ).
  • sense amplifier also used hereinafter
  • sense amplifiers of so-called parallel or flash type
  • sense amplifiers of so-called synchronous-serial-dichotomic or successive-approximations type are used for reading multilevel memory cells: sense amplifiers of so-called parallel or flash type, and sense amplifiers of so-called synchronous-serial-dichotomic or successive-approximations type.
  • Figure 2 illustrates, by way of example, the circuit architecture of a known sense amplifier of parallel type for reading a two-bit memory cell.
  • reading of the contents of the memory cell is performed by comparing the cell current I CELL simultaneously with the three reference currents I REF1 , I REF2, I REF3 using three distinct comparator stages operating in parallel, one for each reference current, the outputs whereof are connected to a decoding stage supplying the two bits stored in the memory cell to be read according to the logic level assumed by the outputs of the comparator stages.
  • Figure 3 instead, shows the dichotomic algorithm implemented by sense amplifiers of synchronous-serial-dichotomic type for reading the contents of a multilevel memory cell storing two bits
  • Figure 4 illustrates the circuit architecture of a known sense amplifier of a synchronous-serial-dichotomic type.
  • the current I CELL is compared with the reference current I REF3 , while if in the first dichotomic step the current I CELL is lower than the reference current I REF2 , then in the second dichotomic step the current I CELL is compared with the reference current I REF1 .
  • each dichotomic step one of the two bits is then decoded; in particular, in the first dichotomic step the most significant bit (MSB) is decoded, while in the second dichotomic step the least significant bit (LSB) is decoded.
  • MSB most significant bit
  • LSB least significant bit
  • reading of the contents of the memory cell is performed using a single comparator stage which, in the first dichotomic step, compares the cell current I CELL with the reference current I REF2 , and, in the second dichotomic step, compares the current I CELL with the reference current I REF1 or I REF3 according to the outcome of the comparison in the first dichotomic step.
  • the selection of the reference current I REF1 , I REF2 , I REF3 to be compared with the cell current I CELL is performed through a multiplexer stage controlled by a control circuit, which is also connected to two registers or latches storing the two bits read.
  • sense amplifiers of parallel type and sense amplifiers of synchronous-serial-dichotomic type have a number of drawbacks that do not enable an adequate exploitation of all their qualities.
  • sense amplifiers of parallel type require a comparator stage for each of the bits stored in the memory cells, which, as is known, occupies a non-negligible area, so that the use of this type of sense amplifier becomes in effect disadvantageous as the number of bits stored in the memory cells increases.
  • Sense amplifiers of synchronous-serial-dichotomic type although using just one comparator stage, require registers for storing the bits read in each dichotomic step, a multiplexer stage, and a control stage.
  • this type of sense amplifier requires an accurate management of the various dichotomic steps so that the circuit complexity of the control stage, and hence its bulk, increases significantly as the number of bits stored in the memory cells increases.
  • the reading speed of synchronous-serial-dichotomic sense amplifiers is not very high; in particular, the total time for reading the contents of a nonvolatile memory cell has on average, in this type of sense amplifier, rather high values of the order of 20-25 ns, which, in some applications, are not acceptable.
  • EP-A-1249841 European patent application No. 01830248.9 , published as EP-A-1249841 , in the name of the present applicant, teaches a sense amplifier of the asynchronous-serial-dichotomic type, the circuit architecture whereof is illustrated in Figure 5 in the case of reading of two-bit memory cells.
  • the sense amplifier is basically made up of a first and a second comparator, and a two-way multiplexer for selecting the reference current with which the cell current must be compared in the second dichotomic step.
  • Reading of the contents of the memory cell is performed in two dichotomic steps similarly to what described previously with reference to sense amplifiers of the synchronous-serial-dichotomic type, except that the two dichotomic steps are asynchronous to each other.
  • the cell current I CELL is compared with the reference current I REF2
  • the cell current I CELL is compared with the reference current I REF1 if the cell current I CELL is lower than the reference current I REF2
  • the reference current I REF3 if the cell current I CELL is higher than the reference current I REF2 .
  • One of the two bits is decoded in each dichotomic step; in particular, in the first dichotomic step the most significant bit (MSB) is decoded, while in the second dichotomic step the least significant bit (LSB) is decoded.
  • MSB most significant bit
  • LSB least significant bit
  • the second dichotomic step starts as soon as the comparison between the cell current I CELL and the reference current I REF2 is terminated, contrary to sense amplifiers of the synchronous-serial-dichotomic type wherein, due to the duration of each dichotomic step being established a priori for the worst case, the second dichotomic step starts after a preset time interval from the start of the first dichotomic step, irrespective of when the first comparator stage has terminated the comparison between the cell current I CELL and the reference current I REF2.
  • an asynchronous configuration using a comparator stage for each dichotomic step, also enables saving of silicon area, which, in a synchronous configuration, is occupied by the control circuit and by the registers.
  • a first of such problems is, for example, represented by the so-called apparent displacement of the distributions of the threshold voltages of the memory cells caused by the datum to be read.
  • the outcome of reading a datum stored in a block of memory cells belonging to a same sector may also depend, to a non-negligible extent, upon the datum itself; i.e., the reading of the contents of a given memory cell is influenced by the reading of the contents of the adjacent memory cells, and this influence is particularly significant in multilevel memory cells, so much so as possibly to lead to reading errors.
  • the memory array is generally divided into sectors, each of which is made up of a group of memory cells having source terminals connected to a common node to enable reading and programming of individual memory cells of the sector and simultaneous erasing of all the memory cells of the sector.
  • the voltage on the common node connected to the source terminals of all the memory cells belonging to a same sector depends upon the current drained by the memory cells being read, so that, given that the outcome of the reading of the contents of a memory cell depends to a significant extent upon the voltage present on its own source terminal, the variation that the voltage present on the common node can undergo according to the datum that is being read may lead to errors in reading the contents of a memory cell.
  • two architectures for generation of the references are used alternatively: a centralized one and a local one.
  • the centralized reference-generation architecture envisages basically that the three reference currents supplied to each of the sense amplifiers are obtained by mirroring an equal number of reference currents generated by a suitable reference generating circuit.
  • This solution albeit with the minor generation errors, entails, however, the use of current mirrors made up of transistors of rather large size, so that this solution has the biggest bulk and a current consumption proportional to the size of the transistors for charging the capacitances associated to their gate regions.
  • the local reference-generation architecture illustrated schematically in Figure 7 once again for the case of multilevel memory cells storing two bits, basically envisages that the three reference currents supplied to each of the sense amplifiers are directly generated by the reference generating circuit.
  • This solution albeit having a smaller bulk in so far as it does not entail current-mirror transistors, leads, however, during testing of the memory device, to long times for checking the references generated.
  • a further problem that adversely affects reading of multilevel memory cells is represented by the so-called "bending" of the voltage-current characteristics of the memory cells, this bending being in turn originated by the so-called “column path” created by the current of the memory cells being read.
  • a dashed line illustrates the ideal voltage-current characteristic of a memory cell
  • a solid line illustrates the actual voltage-current characteristic of a memory cell, which has an evident bending downwards for high cell currents, being caused by the voltage drops on the column-selection transistors and possibly leading to an evident adverse effect on reading.
  • the reading of multilevel memory cells is then strongly influenced by the precision and by the repeatability of the reading voltage supplied to the gate terminals of the memory cells during successive reading operations, the precision and repeatability depending to a marked extent upon the presence of ripple on the reading voltage, the variation of the operating temperature of the memory device, the variation of the supply voltage supplied from outside the memory device, and any excessively close memory accesses.
  • reading of multilevel memory cells is also influenced by the gain spread of the memory cells due to process spreads, by the widening of the distributions of the drain currents caused by the gain variation of the multilevel memory cells, which is in turn caused by variations in the operating temperature of the memory device, as shown in Figure 9, and by the compression of the distributions of the drain currents of the multilevel memory cells caused by minimum-gain memory cells, as highlighted in Figure 10.
  • US-A-6009040 discloses an apparatus for controlling reading of memory cells in a memory device, and including a word line voltage generator operative to apply a word line voltage to a selected memory cell of memory device responsive to a sensing period signal.
  • a dummy memory cell is coupled to the word line voltage generator such that the word line voltage is applied to the dummy memory cell, the dummy memory cell having a threshold voltage.
  • a sensing period controller is coupled to the dummy memory cell and operative to produce the sensing period signal responsive to a current generated in the dummy memory cell.
  • the sensing period controller includes a dummy sense amplifier coupled to the dummy memory cell and operative to produce a dummy cell sense amplifier output signal responsive to a current in the dummy memory cell.
  • a sensing time detector is coupled to the dummy sense amplifier and operative to produce a sensing time signal in response to a transition of the dummy cell sense amplifier output signal.
  • a sensing period signal generator is coupled to the sensing time detector and operative to generate the sensing period signal responsive to the sensing time signal. Apparatus for controlling sensing periods in a multi-level memory device, as well as related operating methods, are also described.
  • US-B1-6385110 discloses a multilevel non-volatile semiconductor memory device comprising plural memory cells having plural threshold levels for allowing the plural memory cells to turn ON or OFF in accordance with relationships of word levels to the plural threshold levels ; a word level generator circuit generating the word levels in every read out time periods for the plural threshold levels ; a memory cell read-out circuit for reading out information from the memory cells ; dummy memory cells receiving inputs of the word levels and having substantially the same threshold levels as the memory cells for allowing the dummy cells to turn ON with delay from the memory cells; and a read out end timing controller for controlling the word level generator circuit to discontinue rising the word level when the dummy memory cell turns ON, and also for controlling the memory cell read-out circuit to finish the read out operations.
  • the aim of the present invention is hence to provide a reading method for a nonvolatile memory device that overcomes at least in part the problems of known nonvolatile memory devices highlighted above.
  • the present invention moreover regards a nonvolatile memory device, as defined in claim 9.
  • the present invention envisages:
  • the four triggering signals will switch in succession and in a given order, which depends upon the threshold voltages of the respective memory cells; in this case precisely the switching order of the triggering signals gives the information regarding the contents of the array memory cell.
  • Figures 11, 12 and 13 respectively illustrate the distributions of the threshold voltages of memory cells associated to the memory of the four two-bit combinations "11", “10”, “01” and “00", the currents I CELL , I REF1 , IREF2 and I REF3 flowing in the array memory cell and in the three reference memory cells, and the comparison current I 0 , and the latch signals LATCH CELL , LATCH REF1 , LATCH REF2 and LATCH REF3 corresponding to the array memory cell and the three reference memory cells.
  • V TH1 , V TH2 and V TH3 indicate the threshold voltages of the reference memory cells (which, in practice, represent the voltage value of the three reference currents that define the four reference intervals initially described and used for reading a multilevel memory cell); furthermore the maximum value of the reading voltage V READ is shown.
  • a dashed line in Figures 11 and 12 indicates the ramp pattern of the reading voltage V READ .
  • the contents of the array memory cell to be read is "10", i.e., the memory cell the contents whereof is to be read belongs to the distribution that is identified in Figure 11 by “10” and is comprised in the range delimited by the threshold voltages V TH1 and V TH2 ⁇
  • the first reference memory cell starts to conduct current and, when its current I REF1 exceeds the reference current I 0 , the corresponding reference-latch signal LATCH REF1 switches from the low to the high logic level.
  • switching of the cell-latch signal LATCH CELL occurs in the interval of time elapsing between the switching of the reference-latch signal LATCH REF1 and the switching of the reference-latch signal LATCH REF2 .
  • the switching of the reference-latch signal LATCH REF1 is indicative of overstepping of the threshold voltage V TH1 that represents the top end of the reference interval, within which the threshold voltages of the memory cells which store the bits "11" fall
  • the switching of the reference-latch signal LATCH REF2 is indicative of overstepping of the threshold voltage V TH2 that represents the bottom end of the reference interval within which the threshold voltages of the memory cells which store the bits "10" fall
  • the switching of the cell-latch signal LATCH CELL that occurs between the switching of the reference-latch signal LATCH REF1 and the switching of the reference-latch signal LATCH REF2 is indicative of the fact that the array memory cell presents a threshold voltage comprised between the threshold voltage V TH1 and the threshold voltage V TH2 and hence stores the bits "10".
  • the information carried on the bus can alternatively be made up either of the reference-latch signals LATCH REF1 , LATCH REF2 and LATCH REF3 directly generated by the sense amplifiers, which will then be compared locally with the cell-latch signal LATCH CELL corresponding to the array memory cell being read, or else of a binary code obtained from processing the reference-latch signals LATCH REF1 , LATCH REF2 and LATCH REF3 , the meaning of which will be clarified hereinafter.
  • Figure 15 illustrates the circuit architecture of a nonvolatile memory device, wherein reading of multilevel memory cells storing each two bits is performed as above described and wherein the information carried on the bus includes the reference-latch signals LATCH REF1, LATCH REF2 and LATCH REF3 directly generated by the sense amplifiers.
  • the memory device designated as a whole by 1 and shown only for the parts concerned in the present invention, comprises: a memory array 2 formed by array memory cells 3 arranged in rows and columns, in which wordlines 4 connect the gate terminals of the array memory cells 3 arranged on a same row and bitlines 5 connect the drain terminals of the array memory cells 3 arranged on a same column; a ramp generator 6, supplied with a voltage V x derived from the supply voltage V DD supplied from outside the memory device and outputting the ramp-like reading voltage V READ having the characteristics described above; three reference memory cells 7 having the threshold voltages V TH1 , V TH2 and V TH3 mentioned above; three sense amplifiers, represented schematically in Figure 15 by a single block designated at 8, for comparing the reference currents I REF1 , I REF2 and I REF3 drained by the three reference memory cells 7 with the comparison current I 0 , for example generated by a suitable current source (not illustrated), and for generating the three reference-l
  • Figure 16 illustrates the circuit architecture of a nonvolatile memory device wherein the reading of two-bit multilevel memory cells is performed according to the present invention and wherein the information carried on the bus is formed by a code obtained by processing the reference-latch signals LATCH REF1, LATCH REF2 and LATCH REF3 generated by the sense amplifiers 8; the meaning of this code will now be clarified.
  • the bus 10 receives the two bits "11" associated to the first distribution of threshold voltages illustrated in Figure 11, i.e., the two bits that are considered to be stored in the memory cells the threshold voltages of which are comprised in the range of reference threshold voltages delimited by the lowest reference threshold voltage, i.e., V TH1, and by the immediately following reference threshold voltage, i.e., V TH2 .
  • the two bits sent on the bus 10 are modified in accordance with the variation of the two bits associated to the distributions of threshold voltages illustrated in Figure 11, which is obtained as the reading voltage V READ increases, i.e., "11" is modified to "10", "01" and "00".
  • the contents of the array memory cell 3 being read are simply the two bits present on the bus 10 when the cell-latch signal LATCH CELL switches, so that the switching of the cell-latch signal LATCH CELL may be used for storing the contents of the bus 10 at that time, and these contents constitute the datum stored in the array memory cell being read.
  • the memory cell that has originated said switching is turned off. This applies both for the array memory cells 3 and for the reference memory cells 7. This is clearly visible in Figure 12, where, immediately after the currents of the memory cells have reached the reference value, they decrease rapidly to zero. Since, however, a reading voltage is applied to their gate terminals, the cell should be turned off by acting on the biasing of the drain terminal, in that the source terminal is generally grounded. This function is performed by the sense amplifiers, which, as known, in addition to recognizing the logic value stored in the memory cells, also correct bias the drain terminals of the memory cells.
  • a small comparison current enables proportional reduction of the size of the column-selection transistors, with consequent reduction of the aforementioned bending of the voltage-current characteristics of the memory cells originated by the column path created by the current of the memory cells being read.
  • the true reading voltage is not the supply voltage V DD supplied from outside the memory device, but rather the voltage ramp generated by the ramp generator, so that any variation of the supply voltage is to some extent mitigated by the ramp generator, which, even though supplied by the supply voltage, derives therefrom only the current necessary for generating the ramp on the wordlines, attenuating the noise present on its supply.
  • inventive gist underlying the present invention may be applied to the reading of memory cells which store any number of bits, even just one.
  • the contents of the array memory cell can be established simply on the basis of which, between the array memory cell and the reference memory cell, first starts conducting.
  • the reading voltage could have a ramp pattern opposite to the one described and illustrated in the figures, namely, a ramp pattern which decreases linearly in time from a maximum to a minimum value.
  • the information regarding the contents of the array memory cell would reside in the switch-off order of the array and reference memory cell or cells.
  • both the array memory cell and the reference memory cells would all start conducting and would turn off one at a time, thereby losing the advantages linked to the possibility of turning off the conducting memory cell as soon as this has provided its contribution to reading, namely, saving of current and eliminating the apparent displacement of the distributions of the threshold voltages.
  • the reading voltage could even have a pattern different from the ramp-like one described and illustrated in the figures, namely, a pattern that is generically variable in time, for example a staircase pattern or else a generically curvilinear pattern that increase or decrease in time.

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Claims (17)

  1. Leseverfahren für eine Speichervorrichtung (1), die eine mehr als zwei Speicherzustände aufweisende Speicherzellenanordnung (3) sowie mindestens zwei Referenzspeicherzellen (7) aufweist, wobei das Verfahren umfasst:
    - Vorspannen der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7), um so deren entsprechende Stromleitzustände bei unterschiedlichen Augenblicken zu modifizieren; und
    - Bestimmen des Inhaltes der Speicherzellenanordnung (3) basierend auf einer zeitlichen Beziehung, die zwischen den Augenblicken existiert, wenn die Stromleitzustände der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7) modifiziert werden;
    wobei das Verfahren gekennzeichnet ist durch:
    - Abschalten der Speicherzellenanordnung (3) als Antwort darauf, dass der Stromleitzustand der Speicherzellenanordnung (3) derart modifiziert worden ist, so dass ihr Stromflußwert größer als ein vorbestimmter Wert ist, und der Stromleitzustand von mindestens einer der Referenzspeicherzellen (7) noch nicht modifiziert worden ist.
  2. Leseverfahren nach Anspruch 1, wobei die zeitliche Beziehung durch den Modifikationsablauf der Stromleitzustände der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7) bestimmt ist.
  3. Verfahren nach Anspruch 1 oder 2, wobei das Vorspannen der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7) umfasst:
    - Anlegen einer gleichen Lesespannung (VREAD) mit einem zeitveränderlichen Muster an die Steueranschlüsse der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7).
  4. Verfahren nach Anspruch 3, wobei die Lesespannung (VREAD) einen im wesentlichen rampenähnlichen Zeitverlauf aufweist.
  5. Verfahren nach Anspruch 4, wobei der im wesentlichen rampenähnliche Zeitverlauf mit der Zeit ansteigt.
  6. Verfahren nach irgendeinem der vorstehenden Ansprüche, wobei das Bestimmen des Inhaltes der Speicherzellenanordnung (3) umfasst:
    - Vergleichen des Zellenstromes (ICELL) der Speicherzellenanordnung (3) und der Referenzströme (IREF) der Referenzspeicherzellen (7) mit demselben Vergleichsstrom (I0), wodurch ein Zellen-Verriegelungssignal (LATCHCELL) und entsprechende Referenz-Verriegelungssignale (LATCHREF) generiert werden, die Informationen über die Augenblicke enthalten, bei denen der Zellenstrom (ICELL) beziehungsweise die Referenzströme (IREF) eine voreingestellte Relation zu dem Vergleichsstrom (I0) erfüllen; und
    - Bestimmen des Inhaltes der Speicherzellenanordnung (3) auf der Grundlage der zeitlichen Beziehung zwischen den Augenblicken, wenn der Zellenstrom (ICELL) und die Referenzströme (IREF) die voreingestellte Relation erfüllen.
  7. Verfahren nach Anspruch 6, wobei die voreingestellte Relation durch die Bedingung bestimmt wird, dass der Zellenstrom (ICELL) oder die Referenzströme (IREF) den Vergleichsstrom übersteigt beziehungsweise übersteigen.
  8. Verfahren nach Anspruch 6 oder 7, wobei das Zellenverriegelungssignal (LATCHCELL) und die Referenz-Verriegelungssignale (LATCHREF) Signale des Logik-Typs sind, die von einem ersten Logikpegel auf einen zweiten Logikpegel umschalten, wenn der Zellenstrom (ICELL) beziehungsweise die Referenzströme (IREF) die voreingestellte Relation erfüllen.
  9. Speichervorrichtung (1), aufweisend:
    - eine Speicherzellenanordnung (3) mit mehr als zwei Speicherzuständen und mindestens zwei Referenzspeicherzellen (7);
    - eine zum Vorspannen der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7) konfigurierte Vorspanneinrichtung (6), um so deren entsprechende Stromleitzustände bei unterschiedlichen Augenblicken zu modifizieren; und
    - eine zum Bestimmen des Inhaltes der Speicherzellenanordnung (3) auf der Grundlage einer zeitlichen Beziehung, die zwischen den Augenblicken existiert, wenn die Stromleitzustände der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7) modifiziert werden, konfigurierte Evaluationseinrichtung (8, 9, 11);
    gekennzeichnet durch:
    - eine Abschalteinrichtung (8, 9), die konfiguriert ist zum Abschalten der Speicherzellenanordnung (3) als Antwort darauf, dass der Stromleitzustand der Speicherzellenanordnung (3) derart modifiziert worden ist, so dass deren Stromwert größer als ein vorbestimmter Wert ist, und der Stromleitzustand von mindestens einer der Referenzspeicherzellen (7) noch nicht modifiziert worden ist.
  10. Speichervorrichtung nach Anspruch 9, wobei die zeitliche Beziehung durch den Modifikationsablauf der Stromleitzustände der Speicherzellenanordnung (3) und der Referenzspeicherzellen (7) bestimmt ist.
  11. Speichervorrichtung nach Anspruch 9 oder 10, wobei die Vorspanneinrichtung aufweist:
    - eine zum Versorgen von Steueranschlüssen der Speicherzellenanordnung (3) und der Referenzspeicherstelle (7) mit einer gleichen, einen zeitveränderlichen Verlauf aufweisenden Lesespannung (VREAD) konfigurierte Spannungserzeugungseinrichtung (6).
  12. Speichervorrichtung nach Anspruch 11, dadurch gekennzeichnet, dass die Lesespannung (VREAD) einen im wesentlichen rampenähnlichen Zeitverlauf darstellt.
  13. Speichervorrichtung nach Anspruch 12, wobei der im wesentlichen rampenähnliche Zeitverlauf mit der Zeit anwächst.
  14. Speichervorrichtung nach irgendeinem der Ansprüche 9 bis 13, wobei die Evaluationseinrichtung (8, 9, 11) aufweist:
    - eine zum Vergleichen des Zellenstromes (ICELL) der Speicherzellenanordnung (3) und der Referenzströme (IREF) der Referenzspeicherzellen (7) mit einem Vergleichsstrom (l0) konfigurierte Komparatoreinrichtung (8, 9), die dadurch ein Zellenverriegelungssignal (LATCHCELL) sowie Referenz-Verriegelungssignale (LATCHREF) mit Informationen über die Augenblicke, zu denen der Zellenstrom (ICELL) beziehungsweise die Referenzströme (IREF) eine voreingestellte Relation zu dem Vergleichsstrom (l0) erfüllen, generiert; und
    - eine zum Bestimmen des Inhaltes der Speicherzellenanordnung (3) auf der Basis der zeitlichen Beziehung zwischen den Augenblicken, zu denen der Zellenstrom (ICELL) und die Referenzströme (IREF) die voreingestellte Relation erfüllen, konfigurierte Bestimmungseinrichtung (11).
  15. Speichervorrichtung nach Anspruch 14, wobei die voreingestellte Relation durch die Bedingung bestimmt ist, dass der Zellenstrom (ICELL) oder die Referenzströme (IREF) den Vergleichsstrom (l0) übersteigt beziehungsweise übersteigen.
  16. Speicherverfahren nach Anspruch 14 oder 15, wobei das Zellenverriegelungssignal (LATCHCELL) sowie die Referenz-Verriegelungssignale (LATCHREF) Signale des Logik-Typs sind, die von einem ersten Logikpegel auf einen zweiten Logikpegel umschalten, wenn der Zellenstrom (ICELL) beziehungsweise die Referenzströme (IREF) die voreingestellte Relation erfüllt beziehungsweise erfüllen.
  17. Speichervorrichtung nach irgendeinem der Ansprüche 14 bis 16, ferner charakterisiert durch:
    - eine zum Befördern der Zellenverriegelungs- und Referenz-Verriegelungs-Signale (LATCHCELL, LATCHREF) konfigurierte Buseinrichtung (10).
EP03425224A 2003-04-10 2003-04-10 Leseverfahren eines nichtflüchtigen Halbleiterspeichers und zugehörige Vorrichtung Expired - Lifetime EP1467377B1 (de)

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EP03425224A EP1467377B1 (de) 2003-04-10 2003-04-10 Leseverfahren eines nichtflüchtigen Halbleiterspeichers und zugehörige Vorrichtung
US10/820,458 US7054197B2 (en) 2003-04-10 2004-04-08 Method for reading a nonvolatile memory device and nonvolatile memory device implementing the reading method

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US20040257876A1 (en) 2004-12-23

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