ITMI20051628A1 - Architettura di meoria con lettura a rampa di tensione - Google Patents

Architettura di meoria con lettura a rampa di tensione

Info

Publication number
ITMI20051628A1
ITMI20051628A1 IT001628A ITMI20051628A ITMI20051628A1 IT MI20051628 A1 ITMI20051628 A1 IT MI20051628A1 IT 001628 A IT001628 A IT 001628A IT MI20051628 A ITMI20051628 A IT MI20051628A IT MI20051628 A1 ITMI20051628 A1 IT MI20051628A1
Authority
IT
Italy
Prior art keywords
meoria
architecture
voltage ramp
reading
ramp reading
Prior art date
Application number
IT001628A
Other languages
English (en)
Inventor
Emanuele Confalonieri
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT001628A priority Critical patent/ITMI20051628A1/it
Priority to US11/469,754 priority patent/US7567475B2/en
Publication of ITMI20051628A1 publication Critical patent/ITMI20051628A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
IT001628A 2005-09-02 2005-09-02 Architettura di meoria con lettura a rampa di tensione ITMI20051628A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT001628A ITMI20051628A1 (it) 2005-09-02 2005-09-02 Architettura di meoria con lettura a rampa di tensione
US11/469,754 US7567475B2 (en) 2005-09-02 2006-09-01 Memory architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001628A ITMI20051628A1 (it) 2005-09-02 2005-09-02 Architettura di meoria con lettura a rampa di tensione

Publications (1)

Publication Number Publication Date
ITMI20051628A1 true ITMI20051628A1 (it) 2007-03-03

Family

ID=38003581

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001628A ITMI20051628A1 (it) 2005-09-02 2005-09-02 Architettura di meoria con lettura a rampa di tensione

Country Status (2)

Country Link
US (1) US7567475B2 (it)
IT (1) ITMI20051628A1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8374045B2 (en) * 2009-12-07 2013-02-12 Spansion Israel Ltd Methods circuits devices and systems for operating an array of non-volatile memory cells
US8854898B2 (en) * 2011-12-14 2014-10-07 Micron Technology, Inc. Apparatuses and methods for comparing a current representative of a number of failing memory cells

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687114A (en) * 1995-10-06 1997-11-11 Agate Semiconductor, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
DE60317768T2 (de) 2003-04-10 2008-11-27 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zum Auslesen einer nichtflüchtigen Speichervorrichtung und zugehörige Vorrichtung

Also Published As

Publication number Publication date
US20070103973A1 (en) 2007-05-10
US7567475B2 (en) 2009-07-28

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