EP1449244A2 - Verfahren zur herstellung einer schicht auf einem substrat - Google Patents
Verfahren zur herstellung einer schicht auf einem substratInfo
- Publication number
- EP1449244A2 EP1449244A2 EP02787365A EP02787365A EP1449244A2 EP 1449244 A2 EP1449244 A2 EP 1449244A2 EP 02787365 A EP02787365 A EP 02787365A EP 02787365 A EP02787365 A EP 02787365A EP 1449244 A2 EP1449244 A2 EP 1449244A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- edge
- substrate
- stress field
- elastic stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 230000001419 dependent effect Effects 0.000 claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 206010010144 Completed suicide Diseases 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910019001 CoSi Inorganic materials 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000005693 optoelectronics Effects 0.000 claims description 2
- 239000007858 starting material Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 20
- 229910017052 cobalt Inorganic materials 0.000 description 18
- 239000010941 cobalt Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 229910020711 Co—Si Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000001015 X-ray lithography Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000276 deep-ultraviolet lithography Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 238000010671 solid-state reaction Methods 0.000 description 1
- -1 specifically Co Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
Definitions
- the invention relates to a method for producing a layer on a substrate.
- This layer is first formed on a substrate.
- at least one structure with a first and second structure edge spaced apart by a minimum distance x is produced.
- the layer having this structure is further structured, so that in particular structures with structure edges are produced with a distance in the nanometer range.
- Optical lithography is used to produce structures in the nanometer range. With the aid of mask technology, the desired structure is transferred to a photosensitive varnish with the aid of lighting, which then serves as a mask for the production of the actual structure.
- This conventional optical lithography allows a resolution of up to approx. 130 nanometers. Processes with an even better resolution, such as X-ray lithography, electron beam lithography or deep-UV lithography, have so far only been possible on a laboratory scale and require a high level of technical complexity and costs (R. Kassing, R. Käsmeier, I. Rangelow, Physikalischet Vol. 56, 2000). In microelectronics, the production of structures ⁇ 100 nanometers represents a major challenge.
- nanostructures i.e. structures smaller than 100 nanometers, not only plays an important role in microelectronics, but is rather a key step in nanotechnology in general. There is a great need for alternative manufacturing processes in order to avoid the extremely complex and expensive lithography processes and to produce structures beyond their resolution limit.
- a method for nanostructuring which is based on self-adjusting processes is known from DE 198 53 023 AI ftö ⁇ L.
- the method relates to the production of a layer having a sub-micrometer structure on a substrate, a layer first being formed on a substrate. Furthermore, means for forming elastic stresses are formed at at least one predetermined position of this layer and then the layer is subjected to a stress-dependent solid-state reaction. This leads to a material separation and consequently a structuring of the layer at this position.
- the structure then has structural edges with distances of at least 30 to 50 nanometers. Smaller structures cannot be produced in this way.
- the object of the invention is therefore to specify a method by means of which structures generated by any structuring method can be reduced at least locally or everywhere.
- the further downsizing of submicron and nanometer structures is the subject of the invention.
- the object is achieved by a method according to the main claim.
- the object is further achieved by a component and a layer sequence according to the dependent claims.
- Advantageous embodiments of the invention emerge from the claims which refer back to it.
- a layer is first formed on a substrate.
- this layer at least one structure with a first and second structure edge spaced apart by a minimum distance x is produced.
- the layer having this structure is then structured further, with this edge having an elastic layer in the area of at least the first structural edge. see voltage field is applied, and then a voltage-dependent diffusion or reaction process is used.
- the first structure edge grows through material transport in the direction of the second structure edge and the desired reduction in size of the structure is achieved.
- the downsizing of the structure is made possible by generating the elastic stress field in an already structured layer and, if appropriate, in the substrate by suitable means. Finally, the voltage-dependent diffusion or reaction process takes place.
- a layer is first formed on a substrate.
- at least one structure is formed with a first and second structure edge spaced apart by a minimum distance x.
- the prior art enables structures with structural edges whose minimum spacing from one another is approximately 30-50 nanometers.
- an elastic stress field is applied to this edge by suitable means in the area of at least the first structure edge, so that in this area the first structure edge grows in the direction of the second structure edge due to material transport and the structure shrinks.
- the mask structure can also have been used to structure the layer. Another way is that the layer to be produced itself generates this elastic stress field due to intrinsic properties or a possible lattice mismatch.
- the growth can also start from both structural edges, e.g. B. by using a suitably designed mask structure, so that the structure is reduced from both directions by material transport.
- a voltage-dependent diffusion or reaction process takes place. This process results in the desired reduction in size, in which in the area of at least the first structure edge in which the elastic stress field has been applied, the structure is reduced in size by material transport out of the layer to be structured. Material can also be transported by diffusion out of the substrate. The growth therefore does not have to take place exclusively through material transport from the layer itself.
- the method is suitable for reproducibly reducing the existing structures.
- the voltage-dependent diffusion or reaction local oxidation, tempering, or a specific alloy formation.
- the amount of material transport and thus the reduction in size of a given structure in the layer can also be reproducibly adjusted to the above-mentioned dimensions by the level of the temperature and by the duration of the diffusion or reaction process. Since the ratios of the elastic stress field are strongly temperature-dependent, the temperature should be selected appropriately for the desired reduction, depending on the materials used.
- oxidation in an oxygen-containing atmosphere is particularly suitable as a diffusion process.
- the voltage-dependent diffusion can also be triggered in a simple manner.
- the formation of specific suicides in a voltage-dependent reaction process by applying metals, especially cobalt, titanium or nickel to a silicon substrate can be carried out at suitable temperatures, e.g. B. at 400 to 900 ° C also cause a reduction in the original structure.
- Corresponding metallic mono- or disilicides are formed.
- the layer thus advantageously contains at least one metal, specifically Co, Ti, Ni, Pd, Pt, W, Ta or Nb or their suicides. These metals due to their good electrical conductivity, they are suitable materials for contacts or connecting lines of electronic components, the corresponding suicides being particularly advantageous in silicon technology because of their high compatibility with silicon.
- Co-Si 2 itself is also particularly suitable as the material for the layer.
- CoSi is very important for semiconductor technology. It can also be structured in such a way that structures are formed with a first and a second structure edge whose spacing is 50 nanometers and less. It is scalable, ie it retains its favorable properties, e.g. B. in terms of conductivity.
- epitaxial cobalt disilicide is particularly advantageous, since this generates the desired elastic stress field itself at suitable temperatures.
- Epitaxial cobalt disilicide is understood to mean cobalt disilicide, which in a lattice-adapted manner on z. B. is a silicon substrate.
- Si 3 N and Si0 2 can be used as materials for forming the elastic stress field, each present individually or in a layer sequence of a mask structure.
- Si 3 N 4 is particularly advantageous because it creates the desired elastic stress field due to its intrinsic properties.
- the method according to the invention allows an at least one-time local reduction of structure which were generated beforehand with the aid of structuring methods according to the prior art.
- the method can also be carried out several times in order to achieve structures with ever smaller dimensions.
- the advantages of the method lie in the possibility of reducing the size of structures into areas beyond the resolution limit of the structuring methods, as are known from the prior art.
- the process is inexpensive and includes technologically comparatively simple processes.
- FIG. 1 shows a cross section through a substrate 1, on the surface of which a layer 2 and a mask structure 3 have been applied.
- the mask structure was structured using conventional lithography and comprises an Si 3 N 4 layer (3a) and an Si0 2 layer (3b).
- Figure 2 shows the cross section of Figure 1 after oxidation as a self-adjusting structuring process according to the prior art.
- Layer 2 separates along the edge of mask structure 3.
- a structure 4 thus arises.
- Structure 4 forms from the substrate and has a first structure edge 4a and a second structure edge 4b, which are at a distance of 70 nanometers from one another.
- the oxidation creates a further Si0 2 layer 5. This covers the unmasked area of layer 2 and structure 4.
- Figure 3 shows the cross section of Figure 2 after removal of the Si0 2 layer and after a voltage-dependent diffusion or reaction process in which the structure 4 converges through material transport from the layer 2 and optionally from the substrate 1, so that structure 4 is reduced and Structure 4 is formed.
- the structural edges 4a ⁇ and 4b * are only 10 to 20 nanometers apart.
- FIG. 4 shows a second exemplary embodiment with the cross section of a substrate 11, on the surface of which there is an already structured layer 12, consisting of a pure metal with a structure 14.
- Structure 14 has a first structure edge 14a and a second structure edge 14b, which are at a distance of approximately 130 nanometers from one another.
- Structure 14 was fabricated using optical lithography and standard etching techniques.
- FIG. 5 shows the cross section of FIG. 4 after a voltage-generating layer 8 has been applied and structured using conventional lithography.
- FIG. 6 shows the cross section of FIG. 5 after a voltage-dependent diffusion or reaction process has been carried out, in which the layer 12 is further structured and converges through the transport of material from the layer itself and possibly also from the substrate, so that with reference to one another structure 14 'is simultaneously reduced to the material of new layer 12' and structure 14 'is produced.
- the structural edges 14b 'and 14a' are only 20 nanometers apart.
- FIG. 7 shows a third exemplary embodiment and the cross section of a substrate 21.
- Structure 24 has a first structure edge 24a and a second structure edge 24b.
- the structured layer 22 was produced by lithography and itself generates an elastic stress field in the substrate 21.
- FIG. 8 shows the cross section of FIG. 7 after a voltage-dependent diffusion or reaction process has been carried out.
- the length of structure 24 is reduced by material transport from layer 22 and possibly from the substrate, so that structure 24 'is formed.
- the structural edges 24a 'and 24b' are then only 15 nanometers apart.
- an approximately 20-30 nanometer thick cobalt disilicide layer 2 is epitaxially applied to a silicon substrate 1.
- the entire layer sequence is oxidized, the silicide layer 2 separating in a self-adjusting manner due to anisotropic diffusion in the elastic stress field at the edges of the nitride layer, and the structure 4 with a length of approximately 70 nanometers is formed (FIG. 2).
- the structure 4 arises from the material of the substrate and has two structure edges 4a and 4b. This oxidation step is usually carried out at temperatures around 1000 ° C., which are necessary in order to produce a homogeneous, uniform structuring.
- the further silicon dioxide layer 5 formed on the unmasked areas by the oxidation is removed again by treatment with a hydrofluoric acid solution.
- the entire layer sequence is oxidized at a lower temperature around 600 ° C. wet in water vapor for about two to three hours.
- the temperature is chosen so that the structure 4 is reduced in size by the changed voltage conditions in this oxidation step (FIG. 3).
- the two structural edges are then only 10 to 20 nanometers apart.
- the material transport and thus the growth of the structural edges takes place due to the size of the elastic stress field from both structural edges through anisotropic diffusion of the cobalt atoms.
- the direction of diffusion for the cobalt atoms thus reverses due to the changed voltage ratios.
- the structure 4 or 4 ' can assume any possible structure under supervision, in particular a continuous, ie channel-shaped structure. However, it is also possible to produce a structure which is step-shaped or edged in the broadest sense depending on the shape of the mask structure 3.
- a pure metal layer 12 made of cobalt is applied to a silicon substrate 11 and structured with the aid of lithography, so that structure 14 with the structure edges 14a and 14b is formed.
- the structure edges are at a distance of approximately 130 nanometers from one another (FIG. 4).
- a mask structure 8 is deposited on part of the layer 12 and structured with the aid of optical lithography (FIG. 5). 5, the edge of the mask structure 8 slightly overlaps the structure edge 14a. At the edges of the mask structure 8, an elastic stress field arises in the layer underneath and in the substrate. In the following voltage-dependent reaction process, the structure 14 is reduced by suitable temperature treatment by anisotropic diffusion of silicon and cobalt as material transport in the stress field caused by the mask structure (FIG. 6), so that structure 14 'is formed. The structural edges grow towards one another from both sides in the given dimensions, as in exemplary embodiment 1, and are only about 20 nanometers apart.
- the desired cobalt disilicide layer 12 ' is formed from layer 12 by siliciding. It is equally possible to apply such a mask structure, that is to say in particular slightly overlapping the structure edge, to both structure edges. Especially when a larger structure, for example in the micrometer range, is to be reduced in size, in which the elastic stress field of a mask structure does not extend to the second structure edge. This enables faster downsizing.
- a corresponding silicide of the elements Ti, Ni, Pd, Pt, W, Ta or Nb can be produced just as well if the corresponding metals have been deposited beforehand.
- Layer sequences of several of these metals mentioned can also be used as a layer to be further structured.
- example 2 wet oxidation at 600 ° C. leads to a reduction in the size of the structure 14 and thus to a structure 14 '.
- a layer of epitaxial cobalt disilicide 22 with structure 24 is present on a substrate 21.
- Structure 24 has structure edges 24a and 24b at a distance of 50 to 130 nanometers (FIG. 7).
- the cobalt disilicide layer 22 has the property of generating an elastic stress field in the substrate 21 itself. This layer is further structured. With suitable thermal treatment, z. B. in wet oxidation at 600 ° C, the structure 24 is reduced by anisotropic diffusion of cobalt as material transport in the stress field generated by it (Fig. 8), so that structure 24 'is formed.
- the structural edges 24a 'and 24b' are only 15 nanometers apart.
- the structures produced according to the invention can be used in particular for producing an electrical, optical, optoelectronic or sensor component.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electron Beam Exposure (AREA)
- Electrodes Of Semiconductors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10157627 | 2001-11-26 | ||
DE10157627A DE10157627A1 (de) | 2001-11-26 | 2001-11-26 | Verfahren zur Herstellung einer Schicht auf einem Substrat |
PCT/DE2002/004237 WO2003046972A2 (de) | 2001-11-26 | 2002-11-16 | Verfahren zur herstellung einer schicht auf einem substrat |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1449244A2 true EP1449244A2 (de) | 2004-08-25 |
Family
ID=7706798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02787365A Withdrawn EP1449244A2 (de) | 2001-11-26 | 2002-11-16 | Verfahren zur herstellung einer schicht auf einem substrat |
Country Status (4)
Country | Link |
---|---|
US (1) | US7084075B2 (de) |
EP (1) | EP1449244A2 (de) |
DE (1) | DE10157627A1 (de) |
WO (1) | WO2003046972A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004048096A1 (de) * | 2004-09-30 | 2006-04-27 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4765169A (en) * | 1987-11-02 | 1988-08-23 | The Monarch Machine Tool Co. | Method of tension leveling nonhomogeneous metal sheet |
DE19503641A1 (de) * | 1995-02-06 | 1996-08-08 | Forschungszentrum Juelich Gmbh | Schichtstruktur mit einer Silicid-Schicht, sowie Verfahren zur Herstellung einer solchen Schichtstruktur |
KR19980024663A (ko) * | 1996-09-18 | 1998-07-06 | 윌리엄 비. 켐플러 | 규화물 영역 형성 방법 |
US6309975B1 (en) * | 1997-03-14 | 2001-10-30 | Micron Technology, Inc. | Methods of making implanted structures |
DE19853023A1 (de) * | 1998-11-18 | 2000-05-31 | Forschungszentrum Juelich Gmbh | Verfahren zur Herstellung von Nanostrukturen in dünnen Filmen |
US6359325B1 (en) * | 2000-03-14 | 2002-03-19 | International Business Machines Corporation | Method of forming nano-scale structures from polycrystalline materials and nano-scale structures formed thereby |
US6397922B1 (en) * | 2000-05-24 | 2002-06-04 | Massachusetts Institute Of Technology | Molds for casting with customized internal structure to collapse upon cooling and to facilitate control of heat transfer |
-
2001
- 2001-11-26 DE DE10157627A patent/DE10157627A1/de not_active Withdrawn
-
2002
- 2002-11-16 EP EP02787365A patent/EP1449244A2/de not_active Withdrawn
- 2002-11-16 US US10/496,850 patent/US7084075B2/en not_active Expired - Fee Related
- 2002-11-16 WO PCT/DE2002/004237 patent/WO2003046972A2/de active Application Filing
Non-Patent Citations (1)
Title |
---|
See references of WO03046972A2 * |
Also Published As
Publication number | Publication date |
---|---|
DE10157627A1 (de) | 2003-06-12 |
US7084075B2 (en) | 2006-08-01 |
WO2003046972A3 (de) | 2004-01-15 |
WO2003046972A2 (de) | 2003-06-05 |
US20050042870A1 (en) | 2005-02-24 |
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