Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
  • H03M3/402—Arrangements specific to bandpass modulators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
  • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
  • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
  • H03M3/416—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type all these quantisers being multiple bit quantisers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
  • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
  • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
  • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
  • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
  • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
  • H03M3/45—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedforward inputs, i.e. with forward paths from the modulator input to more than one filter stage
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
  • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
  • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
  • H03M3/454—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Definitions

• the present invention relates to a Sigma-Delta bandpass analog-digital converter, and a Sigma-Delta MASH converter incorporating it.
• the invention finds applications in radiofrequency receivers, in particular of mobile stations or fixed stations of a radiocommunication system, for example a private professional radiocommunication system (PMR system, from the English "Private Mobile Radiocommunication").
• the signal to be converted is for example a signal containing about twenty channels each having a width approximately equal to 12 kHz (kilohertz), or a signal occupying a frequency band of total width equal to approximately 200 kHz .
• Sigma-Delta converters are very widespread in the field of analog-digital conversion due to their high resolution (quantization is typically carried out on 16 bits, and even on 17 or 18 bits in some cases). This high resolution is obtained thanks to a high sampling frequency relative to the band of the converted signal (typically, the sampling frequency is of the order of megahertz or ten megahertz), which does not constitute a disadvantage in a radio frequency system.
• FIG. 1 The principle of a Sigma-Delta modulator is illustrated by the diagram of FIG. 1.
• a low-pass Sigma-Delta modulator 100 has been represented which makes it possible to convert samples x (nT) of an analog signal input obtained at a determined sampling frequency, denoted Fs in the following, in values y (nT) of a digital output signal coded on n bits, where n is an integer.
• the converter 100 comprises an analog subtractor 11 whose positive input receives the samples x (nT), and whose negative input receives the samples x '(nT) of an analog feedback signal.
• the exit of the subtractor 11 is supplied at the input of a filter 12, the output of which is connected to the input of an analog-digital converter 10, hereinafter called CAN (or ADC in English, for “Analog-to-Digital Converter”) .
• a feedback loop comprises a digital-analog converter 20, hereinafter called DAC (or DAC in English, for “Digital-to-Analog Converter”), which receives as input the values y (nT) of the digital output signal and the converts to deliver the x '(nT) samples of the above analog feedback signal.
• the filter 12 is a low-pass filter. This achieves a shaping of the quantization noise ("Noise Shaping", in English), making it possible to reject the quantization noise towards the high frequencies.
• the shaping of the quantization noise by the first order low pass filter is illustrated by the graph in FIG. 2.
• the energy density N of the quantization noise is represented as a function of the frequency f, for values of f between 0 and Fs.
• the ADC converts, not the samples x (nT) of the input signal directly, but the difference between these samples x (nT) and the samples x '(nT) of the analog reaction signal, after shaping quantization noise by the filter 12.
• the quantization noise is then eliminated, by a digital post-processing, by means of a decimation filter (not shown) receiving as input the values y (nT) of the digital output signal coded on n bits, and delivering as output digital values coded on n + m bits, where m is also an integer.
• Post-processing by the decimation filter operates a low-pass filtering, to attenuate the energy of the signal outside the useful band. It also has the function of reducing the sampling frequency to the Nyquist frequency, for example by averaging over several values of the consecutive output signal y (nT).
• the quantization noise shaping function corresponds to the inverse of a function cardinal sine ("sine" function), so that the transfer function of the decimation filter is a sine function, which is easy to perform.
• the converter When the converter is made with components in CMOS technology, which generate noise at zero frequency (frequency of the DC), it is preferable not to convert the signal to baseband.
• the signal is converted after frequency transposition in a frequency band between, for example, 400 kHz and 600 kHz.
• the signal to be converted is then centered on a central frequency Fo, equal to 500 kHz in this example.
• the shaping of the quantization noise by the low-pass filter of the converter then becomes a drawback, since the energy density of the quantization noise at the frequency Fo can be high, which greatly degrades the signal to noise ratio or SNR (from the English "Signal-to -oise Ratio").
• a Sigma-Delta bandpass converter 200 is illustrated by the diagram in FIG. 3, in which the same elements as in FIG. 1 bear the same references. In essence, this principle is similar to that of the Sigma-Delta low-pass converter 100, the low-pass filter 12 for shaping the quantization noise of the latter (FIG. 1) being nevertheless replaced by a resonator 13.
• a resonator is a bandpass filtering cell having an infinite gain at a determined frequency (corresponding to a pole of the transfer function) called the central frequency of the resonator.
• the central frequency of the resonator 13 is adjusted to the central frequency Fo of the frequency band of the signal to be converted.
• the shaping of the quantization noise by a first-order resonator is illustrated by the graph in FIG. 4, to be compared to that of FIG. 2.
• the quantization noise is rejected by hand and on the other side of the central frequency Fo.
• the invention aims to propose an alternative to these techniques of the prior art.
• an analog-digital converter Sigma-Delta bandpass comprising: a first analog adder receiving, on a first input, the samples of an analog input signal to be converted, and the samples of a first analog feedback signal on a second input;
• a second analog adder receiving, on a first input, the samples delivered by the output of the first resonator, the samples of a second analog feedback signal on a second input, and, in addition, the samples of the analog input signal to convert on a third input;
• a second second order resonator whose central frequency is adjustable, receiving as input the samples delivered by the output of the second analog adder; - an analog-digital converter receiving as input the samples delivered by the output of the second resonator and delivering as output values of a digital output signal corresponding to the converted analog input signal;
• a first feedback loop which comprises a digital-analog converter receiving as input the values of the digital output signal, and which delivers the samples of the first analog feedback signal;
• a second feedback loop which comprises said digital-analog converter and which delivers the samples of the second analog feedback signal.
• the resonators have an adjustable central frequency makes it possible to increase the width of the frequency band outside of which the quantization noise is rejected.
• a high SNR can be obtained in a relatively wide frequency band, of the order of 200 kHz.
• the invention also relates to a Sigma-Delta MASH analog-digital converter, comprising at least a first and a second Sigma-Delta cascade bandpass analog-to-digital converter, as well as a recombination filter receiving the output signal from the first converter. on a first input and the output signal of the second converter on a second input, in which the first and / or the second converters are Sigma-Delta bandpass analog-digital converters as defined above.
• the advantage of the Sigma-Delta MASH analog-digital converter of the invention lies in the fact that such an eighth order converter is obtained with only two stages, which reduces the space occupied by the converter on a silicon substrate.
• FIG. 11 a diagram illustrating the geographic distribution on a silicon substrate of 16 ⁇ 16 current sources entering into the composition of a DAC with 4 bits at input;
• Figure 12 a table illustrating the control of 16 elementary current sources used in the composition of a 4-bit DAC, with pseudo-random interleaving of these sources;
• FIG. 5 is a schematic representation of an analog-digital converter Sigma-Delta bandpass 300 according to the invention.
• This converter 300 includes a first analog adder S1. This receives, on a first input, via a scaling circuit 53 whose gain J3 is positive, the samples x (nT) of the analog input signal x to be converted. It also receives, on a second input, the samples x1 '(nT) of a first analog feedback signal xV.
• the converter 300 also includes a first resonator 101, preferably of the second order.
• the central frequency of the resonator 101 is adjustable.
• the resonator 101 receives as input the samples delivered by the output of the analog adder S1, corresponding to the analog sum of the samples x1 '(nT) and the samples x (nT) affected by the gain J3 of the scaling circuit 53. It delivers at the output of the samples j (nT) a signal j corresponding to the analog signal received at the input after bandpass filtering.
• the converter 300 also includes a second analog adder S2. This receives, on a first input the samples j (nT) delivered by the output of the resonator 101. It also receives, on a second input, the samples x2 '(nT) of a second analog feedback signal x2' . Preferably, it also receives, on a third entry, via another scaling circuit 54 whose gain J4 is positive, the samples x (nT) of the analog input signal x.
• the converter 300 also comprises a second resonator 102, preferably also of the second order, the central frequency of which is also adjustable.
• This receives as input the samples of the analog signal delivered by the output of the second analog adder S2, corresponding to the analog sum of the samples j (nT) and x2 ′ (nT), and in addition of the samples x (nT) affected by the gain J4 of the scaling circuit 54. It outputs the samples k (nT) of an analog signal k corresponding to the analog signal received as input after bandpass filtering.
• the signal k output from the resonator 102 is called band pass filtered analog signal.
• the order bandpass filtering to which reference is thus made is, in the example described, a fourth order filtering resulting from the second order filtering by each of the resonators 101 and 102.
• the CAN 103 receives as input the samples k (nT) of the filtered analog signal bandpass k, delivered by the output of the second resonator 102. It delivers at the output the values y (nT) of a digital signal y corresponding to the analog signal input x converted.
• the converter 300 also comprises a first feedback loop 111 which comprises a digital-analog converter 104 with n bits at input.
• the DAC 104 receives the values y (nT) of the digital output signal y as an input, and outputs the samples x '(nT) of an analog signal x' corresponding to the converted output signal y.
• the feedback loop 111 also includes a scaling circuit 51, receiving the samples x '(nT) at the input and outputting the samples x1' (nT) of the aforementioned first analog feedback signal x1 '.
• the gain J1 of the scaling circuit 51 is negative, in order to obtain the desired feedback.
• the converter 300 finally comprises a second feedback loop 112, which includes the CAN 104 and another scaling circuit 52, receiving the samples x ′ (nT) at the input and delivering the samples at the output.
• the gain J2 of circuit 52 is also negative, in order to obtain the desired feedback.
• the analog signal to be converted has a frequency band of the order of 200 kHz wide, corresponding to 20 channels of approximately 12 kHz wide each. This band is transposed to a central frequency Fo substantially equal to 1.2 MHz.
• the respective transfer functions of the first resonator 101 and the second resonator 102 are denoted H1 (z) and H2 (z) respectively, where z denotes the discrete variable time frequency.
• ⁇ 1 and ⁇ 2 the argument of the variable z for the transfer function H1 (z) and for the transfer function H2 (z) respectively.
• the transfer function H1 (z) of the resonator 101 is preferably given by the following relation: (cos ⁇ 1 xz - z- * and the transfer function H2 (z) of the second resonator 102 is preferably given by the following relation:
• the resonator 101 and the resonator 102 are of identical structure, that is to say that their respective transfer functions are performed by identical electronic components. This simplifies the design, testing and implementation of the converter on a silicon substrate.
• the resonator 101 and the resonator 102 are filters second order analogs.
• they have a structure with switched capacities, with adjustment of the parameter respectively cos ⁇ l or cos ⁇ 2, via a respective variable capacity.
• switched capacity is meant a capacitor having an ISAM upstream serial switch and an ISAV downstream serial switch, respectively in series with each of these terminals on the one hand, and in addition an IPAM upstream parallel switch and an IPAV downstream parallel switch, parallel respectively with each of its terminals on the other hand (see for example the switched capacity CO1 in the diagram in FIG. 6).
• the free terminal of the parallel switches IPAM and IPAV of each switched capacity to which reference is made below, is connected to earth.
• Switched capacity filters are well known to those skilled in the art and do not call for specific comments here.
• the resonator 101 which here has a switched capacitor structure, comprises two integrating stages. Each of these stages comprises an operational amplifier 61A and 62A respectively, in series via a switched capacitor C12. The output of the resonator 101 is taken from the output of the amplifier 61 A, which therefore delivers the analog signal j.
• the non-inverting inputs of amplifiers 61 A and 62A are connected to ground.
• the output of amplifier 61A is connected to its inverting input via a capacitor C1A.
• the output of the amplifier 62A is connected to its inverting input via a variable capacitor C2A, making it possible to adjust the above-mentioned cos ⁇ l parameter.
• the inverting input of amplifier 61 A receives the analog input signal x (multiplied by the gain J3 of the scaling circuit 53) via a switched capacitor C01.
• the first feedback signal x1 ' is carried on the free terminal of the upstream parallel switch IPAM of the switched capacity C01, the latter not being connected to ground.
• the switched capacity C01 thus connected, forms the analog adder S1.
• the inverting input of amplifier 61 A is connected to the output of amplifier 62A via a switched capacitor C21.
• the inverting input of amplifier 62A receives the analog input signal x (multiplied by the gain J3 of the setting circuit. scale 53) via another switched capacitor C02.
• the first feedback signal x1 ' is carried on the free terminal of the upstream parallel switch
• IPAM of the switched capacity C02 this one not being connected to the ground.
• the resonator 102 which also here has a switched capacitor structure, comprises two integrating stages. Each of these stages comprises an operational amplifier 61B and 62B respectively, in series via a switched capacitor C12.
• the output of the resonator 102 is taken from the output of the amplifier 61 B, which delivers the filtered analog signal bandpass k.
• the non-inverting inputs of amplifiers 61 B and 62B are connected to ground.
• the output of amplifier 61 B is connected to its inverting input via a capacity C1 B.
• the output of amplifier 62B is connected to its inverting input via a variable capacity C2B, making it possible to adjust the aforementioned parameter cos ⁇ 2 .
• the inverting input of amplifier 61 B receives, firstly the analog signal j via a switched capacitor C01, and secondly the analog input signal x (multiplied by the gain J4 of the scaling circuit 54 ) via another switched capacity C01.
• the second feedback signal x2 ' is carried on the free terminal of the upstream parallel switch IPAM of each of the two switched capacitors C01 mentioned above, the latter not being connected to ground.
• the switched capacities C01, as well switched, form the analog adder S2.
• the inverting input of amplifier 61 B is connected to the output of amplifier 62B via a switched capacitor C21.
• the inverting input of amplifier 62B also receives, firstly the analog signal j via a switched capacitor C02, and secondly the analog input signal x (multiplied by the gain J4 of the scaling circuit 54 ) via another switched capacitor C02.
• the second feedback signal x2 ' is carried on the free terminal of the upstream parallel switch IPAM of each of the two above-mentioned switched capacitors C02, the latter not being connected to ground. If the following relationships are also provided:
• capacitors C2A and C2B are adjustable, and it is by them that we can adjust the values of the parameters cos ⁇ l and cos ⁇ 2 respectively, which determine the exact position of the poles of the transfer functions H1 (z) and
• the center frequency Fc1 of the resonator 101 is slightly lower (respectively higher) than the center frequency Fo of the frequency band of the analog input signal x to be converted, and the center frequency Fc1 of the resonator 102 is slightly higher (respectively lower) than this central frequency Fo.
• the curve 81 gives for example the shape of the quantization noise shaping by the resonator 101
• the curve 82 gives the shape of the shaping of the quantization noise by the resonator 102.
• the curve 90 gives the appearance of the shaping of the quantization noise by the Sigma-Delta bandpass converter 300 comprising the associated resonators 101 and 102.
• the analog-digital converter 103 is preferably of the Flash type with n bits at output. Such a converter has the advantage of a high conversion speed, thanks to the absence of transient regimes.
• the digital-analog converter 104 is preferably also of the Flash type, with n bits at input, with weighted current sources. The advantage of such a converter is also due to the speed of the conversion.
• the principle of a DAC with weighted current sources, which is known in itself, is illustrated by the diagram in FIG. 10.
• the DAC comprises n current sources CSO to CSn-1 connected in parallel between a node A and a node B, and each in series with a control switch, respectively SWO to SWn-1. Current sources
• CSO, CS1 CSi, ..., CSn-1 are said to be weighted in the sense that they deliver a current respectively lo, 2xlo, ..., 2'xlo, ..., 2 n "1 xlo where lo is the current delivered by an elementary current source.
• a resistor R is furthermore connected between the nodes A and B.
• the control switches are controlled by n respective control signals, the logic state of which is determined by the information bits stored in a register (not shown), and corresponding to the digital value to be converted.
• the voltage Vout between nodes A and B constitutes the analog signal produced by the conversion.
• the current sources SCO to SCn-1 are produced by 2 n elementary current sources, each delivering the aforementioned current lo, and one of which is not used.
• the current source CSO includes such an elementary current source.
• the current source CS1 includes two in parallel.
• the current source CS2 includes four in parallel.
• the current source CS3 includes eight in parallel. And so on.
• each of the 2 n elementary current sources consists of 2 ⁇ elementary current sub-sources, each delivering a current lo / 2 ⁇ . It is therefore a total of 2 n x 2 n current sources which are included in such a DAC.
• these are respective bipolar transistors.
• These current sources are preferably placed on a silicon substrate according to a determined geographic distribution of the 2 ⁇ x 2 n matrix type, with pseudo-random interleaving.
• references of the type "i-1.j- 1" designate the implantation zone (here substantially a rectangle) on the silicon substrate, of the j-th elementary current sub-source of the i-th current source elementary, for i and j between 0 and 15.
• the pseudo-random interleaving (or mixing) of the current sources still makes it possible to reject part of the energy of these parasitic lines outside of the pass band.
• This object is achieved by periodically modifying the control bit of a current source with another control bit (these control bits being the binary data stored in the aforementioned register). The changes are made by following a pseudo-random law of length L. Admittedly, the periodicity of these modifications is at the origin of parasitic lines in the spectrum of the analog signal at the output of the DAC, but the value of L is chosen so that these lines are located outside the bandwidth.
• CO to C15 the control signals of the sixteen elementary current sources
• InO to In15 the binary input values of the DAC.
• the graphs of FIGS. 13 and 14 show the curve of the shaping of the quantization noise, obtained by simulation software, respectively without and with interleaving of the current sources.
• the quantization noise is more strongly rejected outside the bandwidth (around 200 kHz around 1.2 MHz) thanks to interleaving. It has been measured that the improvement in the SNR in the passband which results from this interleaving is of the order of 2.3 dB (decibel).
• a converter produced according to the present invention makes it possible to produce a radio frequency reception chain capable of complying with most of the current standards which govern radiocommunication systems (GSM standards, TETRAPOL, APCO 25, etc.).
• the structure of the MASH type, or cascaded structure makes it possible to increase the order of the Sigma-Delta converter without incurring stability problems.
• two Sigma-Delta converters of the fourth order cascades we obtain indeed an analog-digital converter Sigma-Delta of type MASH of the eighth order.
• an eighth order converter is sufficient for most applications.
• the Sigma-Delta MASH 400 converter comprises two cascade stages 300a and 300b, each of these stages being an analog-digital Sigma-Delta bandpass converter of the fourth order, as described below. above with reference to the diagram in FIG. 5.
• the same elements as in FIG. 5 bear the same references to which however the suffix "a” or the suffix "b" is added, to the first stage elements 300a and for the second stage elements 300b respectively.
• the first stage 300a outputs digital values y1 (nT) of an output signal y1.
• the second stage 300b delivers digital values y2 (nT) as an output from an output signal y2.
• the structure of each floor is not described again here.
• the scaling circuit 54b of the second stage 300b does not directly receive the input signal of the second stage 300b, but this input signal multiplied by the gain J3b of the scaling circuit 53b. It follows that the value of the gain J3b + J4b of the circuit 53b and of the circuit 54b put in series, corresponds to the value of the gain J4 of the shaping circuit 54 of the converter 300 of FIG. 5.
• the converter 400 further comprises an analog subtractor 151, the positive input of which receives the samples x'a (nT) of the analog signal delivered by the output of the DAC 104a of the first stage 300a, and the negative input of which receives the samples ka (nT) of the filtered analog signal band pass ka of the first stage 300a.
• the output of subtractor 151 delivers samples of an analog signal corresponding to the difference of samples x'a (nT) and samples ka (nT).
• This analog signal after passing through a scaling circuit 152 and through a self-timer 153, constitutes the analog input signal of the second stage 300b.
• the converter 400 further comprises a recombination filter 154 which receives, on a first input, the output signal y1 of the converter 200a and, on a second input, the output signal y2 of the converter 200b.
• This filter 154 combines the values y1 (nT) and the values y2 (nT) of the digital signals y1 and y2 respectively, in order to produce the values y (nT) of the digital output signal y of the converter 400.
• z denotes the discrete time-frequency variable
• y1 denotes the output signal of said first converter (200a)
• y2 denotes the output signal of said second converter (200b)
• G denotes the gain of the scaling circuit 152 disposed between the converter 300a and the converter 300b.

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