WO2017037744A2 - A delta sigma modulator with noise attenuating feedback filters - Google Patents

Abstract

An M-bit delta sigma modulator (200) includes at least one integrator (204) comprised of plurality of amplifiers. An amplifier of a plurality of amplifiers in the amplification path is chopped at a chopping frequency (f_chp) to generate an integrated signal (201-1). The chopping frequency (f_chp) being 1/N times of a predetermined sampling frequency (f_s). A loop filter (206) is coupled to the at least one integrator (204) to generate a filtered analog signal (201-2). An M-bit analog to digital converter (208) is coupled to the loop filter (206) to convert the filtered analog signal (201-2) to an M-bit digital signal (D) sampling at the predetermined sampling frequency (f_s). At least one filter (210) and a Q-bit digital to analog converter (212) are provided in a feedback path (220-1) to generate a negative feedback analog signal (201-3). The at least one filter (210) is configured with a transfer function.

Description

A DELTA SIGMA MODULATOR WITH NOISE ATTENUATING FEEDBACK

FILTERS

TECHNICAL HELD

[0001] The present subject matter, generally, relates to analog to digital converters, and particularly relates to analog to digital converters based on Sigma Delta Modulation, and more particularly relates to Sigma Delta Modulators with filters for noise attenuation.

BACKGROUND

[0002] Analog to Digital Converters (ADC) based on sigma delta modulation are employed in high-resolution and low to medium frequency range applications. Moreover these ADC converters are inherently monotonous and usually exhibit high linearity. Despite the relative simplicity and robustness, a trend towards higher performance has distended the scope of sigma delta modulators. For example, at an audio resolution, say 24 bits, which is commercially available, any source of noise becomes a concern. This is particularly true at low frequency, where, for example, flicker noise may become a limiting factor. For sensor applications, using the ADC converters of sigma delta modulation, performance degradation may be due to gain and offset errors. Many techniques are used to reduce the offset errors and flicker noises associated with sigma delta modulators, for example, correlated double sampling or chopping.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference, like features and components.

[0004] Figure 1 illustrates a mechanism of down conversion of quantization noise in a chopped continuous time delta-sigma modulator (CTDSM). [0005] Figure 2A illustrates a delta sigma modulator with a feedback digital filter, according to an embodiment of the present subject matter.

[0006] Figure 2B illustrates a circuit implementation of loop filter of Figure 2A comprising a cascade of integrators, according to an embodiment of the present subject matter.

[0007] Figures 3A and 3B illustrate an example circuit implementation of a first integrator of Figure 2A, according to an embodiment of the present subject matter.

[0008] Figure 4A illustrates an example of an OTA-RC integrator of Figure 3A, with a chopped feed-forward compensated OTA, according to an embodiment of the present subject matter.

[0009] Figure 4B illustrates an example of Miller compensated OTA, according to an embodiment of the present subject matter.

[0010] Figure 5A illustrates a continuous time delta sigma modulator with a feedback FIR DAC, according to an embodiment of the present subject matter.

[0011] Figure 5B illustrates a graph depicting Power Spectral density (PSD) for the continuous time delta sigma modulator of Figure 5A, according to an embodiment of the present subject matter.

[0012] Figure 5C illustrates another graph depicting Power Spectral density (PSD) for the continuous time delta sigma modulator of Figure 5A, according to an embodiment of the present subject matter.

[0013] Figure 5D illustrates yet another graph depicting Power Spectral density (PSD) for the continuous time delta sigma modulator of Figure 5A, according to an embodiment of the present subject matter.

[0014] Figure 6 illustrates a flowchart of a method for generating an M-bit digital signal, according to an embodiment of the present subject matter DETAILED DESCRIPTION

[0015] "Delta-sigma modulators" are also commonly referred to using other interchangeable terms such as "sigma-delta modulators", "delta-sigma converters", "sigma delta converters", and "noise shapers". "Delta-sigma modulator" and "sigma delta modulator" are interchangeable terms for the purpose of this specification.

[0016] In general, delta sigma converters are operated at a significantly higher sampling rate than the bandwidth of the analog input signal, a technique referred to as oversampling, wherein the analog input signal is sampled at a very high sampling rate in order to perform a noise shaping function. In an example, the oversampling is performed at a multiple of Nyquist rate for a given input signal frequency content, wherein a quantization noise power is spread over a bandwidth equal to a sampling frequency (fs). The sampling frequency, for example, is the average number of samples obtained per second. The Nyquist rate, for example, is the minimum rate at which a signal can be sampled without introducing errors, which is twice the highest frequency present in the signal.

[0017] In another example, a sigma-delta converter includes a modulator, which, by performing the oversampling technique, manipulates noise spectrum of an analog input signal such that a major component of quantization noise power is shifted to a frequency range outside of the band of interest. Noise shaping filters, such as integrators, are provided in signal path of the delta sigma modulator; and digital filtering is performed on the oversampled digital output signal obtained by the oversampling technique to achieve a high resolution; and decimation is employed to reduce the effective sampling rate back to the Nyquist rate. The decimation, for example, is a process that reduces the sampling rate of the signal.

[0018] In a delta-sigma modulator, there are two types of noise sources, namely, output stage noise sources and input stage noise sources. The output stage noise sources, for example, are dominated by quantization noise and the input stage noise sources, for example, result from DC offset and 1/f noise or flicker noise. Flicker noise is a noise that is characterized by a 1/f relationship such that lower frequencies tend to contribute more to the noise. Many industrial applications require high resolution ADCs whose low frequency performance is important. However, their low frequency precision is degraded by the flicker noise. On the other hand, quantization noise or error is introduced when a delta sigma modulator receives an input signal and coverts the signal into binary pulses having an average amplitude over time proportional to the input signal, and the modulator is designed to suppress the components of this noise which reside in the signal band. For example, in audio baseband, the frequency component of interest is between about OHz and about 20-25 kHz.

[0019] Conventionally, in order to reduce the flicker noise, large input devices were used in the amplifiers of a delta sigma modulator, for example, input devices that are lOOOx larger than would be needed if flicker noise was not present. For example, this flicker noise problem is a significant issue with circuits fabricated with CMOS devices of 45nm. One approach has been to increase the devices sizes away from 45 nm. The result, however, is a modulator that is unattractively 2 to 4 times the size. In addition, if the size increases, parasitic capacitances also increase. Therefore, using large input devices in the modulator to reduce flicker noise increases area occupied by the input devices, and increases parasitic capacitance at the input stage virtual ground, and degrades the modulator linearity by reducing a loop gain of the input devices. The input device, for example, is an integrator comprised of an amplifier such as Operational Transconductance Amplifier (OTA). Therefore, there remains a need for a sigma delta modulator that reduces the impact of flicker noise and also provides small device/circuit size to avoid impacting current and power consumption.

[0020] Another, conventional approach for addressing the flicker noise or 1/f noise is to chop the OTA of the input integrator, to modulate its flicker noise out of the signal band of interest. This, however, degrades the Sigma Delta Modulators (A∑M's) Signal Quantization Noise ratio (SQNR) by aliasing shaped quantization noise in-signal band of interest. Another conventional approach is to increase number of quantization levels, for example, 15 levels, by employing a multibit quantizer. However, this will also result in an increase in current and power consumption. A quantizer, for example, is device whose function is to create quantization levels of an analog signal. An analog-to-digital converter is an example of a quantizer. Therefore, there remains a need for a sigma delta modulator that reduces the impact of shaped quantization noise aliasing but also provides small device/circuit size to avoid impacting current and power consumption.

[0021] A circuit shown in Figure 1 depicts how the quantization noise aliases into a signal band. Figure 1 illustrates a mechanism of down conversion of quantization noise in a chopped continuous time delta-sigma modulator (CTDSM). A delta sigma modulator may be a continuous time delta-sigma modulator (CTDSM) or a discrete time delta-sigma modulator (DTDSM). The delta sigma modulator shown in Figure 1 is an example of a continuous time delta-sigma modulator (CTDSM). As shown in Figure 1, modulator (100) operates by accepting an input signal (101) through an Operational Transconductance Amplifier (OTA) (104), which feeds a loop filter (108) built with a set of series connected multiple filter elements each with its own feedback and illustrated later on in this document. The loop filter (108) basically provides an integrated value of this input signal (101) to a quantizer (110), which is typically implemented, for example, as a comparator. The quantizer output signal (D) is fed back to an input junction through a resistor (R) or a combination of resistors. In an example, a feedback loop of the modulator forces the average of feedback signal to be substantially equal to the input signal. The number of feedback loops in the loop filter determines the order of continuous time delta- sigma modulator. The number of feedback loops in the loop filter (108), for example, may be same as number of integrators used in the loop filter (108). The quantizer (110), for example, is a one-bit quantizer, the density of "ones" in quantizer's output signal (D) is proportional to the value of the input signal (101). The delta sigma modulator (100) oversamples the input signal (101) by clocking the comparator or quantizer (110) at a sampling rate (f_s) that is much higher than the Nyquist rate. [0022] Briefly describing Figure 1, an analog input signal (101) is acquired and then chopped by chopping switch (102) at a chopping frequency (f_Chp) at the input of a first transconductor stage (104). There are a wide variety of conventional chopping switches that may be used and one example of a chopping switch is depicted in this figure. The chopped signal from chopping switch (102) is amplified by first transconductor (104) and then is chopped again by a second chopper (106) before reaching a second transconductor stage (shown as loop filter). The output from the second chopper (106) is amplified at the second transconductance stage. The next step in is to quantize the output from the second transconductor with a quanitizer (110), which is sampled at f_s to produce a digital signal (D) that can be further processed. As is known, the output of the quanitizer (110) is typically fed-back to an input of the transconductors. The portion of the delta sigma modulator (100) where the chopped signal and the feedback signal are combined is known as a summing junction (112) where the voltages of the chopped signal from the second chopper (106) and the feedback signal are alternately summed and subtracted. While this arrangement of Figure 1 does partially address flicker noise issues, it also introduces other disadvantages. In particular, quantization noise from the quanitizer (110) is present at the summing junction (112) along with the analog input signal (101); therefore the summing junction (112) contains frequency components from 0 to f_s. Because the f_ChP is performed at less than f_s, the operation of combining the voltages at the summing junction (112) occurs at less than the Nyquist rate of f_s. Thus, foldover, or aliasing, of quantization noise is introduced; in other words, high frequency components at multiples of f_ChP gets folded to around DC due to this operation at the summing junction (112). Thus, the noise floor of the continuous time delta sigma modulator (100) is increased.

[0023] The detailed mechanism and the signal waveforms by which shaped quantization noise aliases into a signal band of interest is explained in Figure 1, which shows the details of the 1st integrator of a high order 1-bit CTA∑M (100) sampling at f_s. For illustration, the first integrator is an active- RC integrator that uses a 1-stage operational transconductance amplifier (OTA) (104). The 1-stage OTA (104) is chopped at f_ChP, the value of f_ChP, for example, chosen as fs /12. The CTA∑M (100) output is denoted by D (= +1). The transconductance of the Operational Transconductance Amplifier (104) is denoted by (G_ota) in the figure. Since the G_ota is finite, virtual ground nodes (v_xp & v_xm) before the first chopper (102) have peak-to-peak swing (l/RG_0ta), as shown as signal waveform representation in Fig. l . An impulsive current (i_x) flows into the virtual ground node v_Xp due to the OTA' s parasitic (Cpl ). This impulsive current (i_x) can be separated into two components, namely i_xi and Ai_x. The component of impulsive current i_xl, is due to transitions in the output D, and consists of impulses given by i_xl = Cpl (D[k] - D [k - l])/RG_ota. In the equation, the impulsive component being proportional to a high-pass version of D, the i_xl has negligible low frequency content.

[0024] The other impulsive component of i_x, denoted by Aix, occurs at every rising and falling edge of the chopping frequency (fchp) as shown in the signal waveform representation of Figure 1. Since the fchp = fs /12, edges of the fchp occur every 6th cycle of fs (as shown in Figure 1); and hence the OTA (104) input node voltage (vyp) jumps by D [6k]/RG_0ta (once every 6 cycles of fs). Thus Aix is an impulsive sequence which is equal to Cpl .D [6k]/ (RG_0ta). Since Aix depends on D sampled at 2fchp, shaped quantization noise at multiples of 2fchp (= fs 16 in our example shown in Figure 1) aliases in-band. The spectral density of out-of- band shaped noise in a high order CTA∑M, for example, a 3rd order 1-bit CTA∑M is more than 100 dB higher than the in-band density; so even small amounts of aliased noise may dramatically degrade in-band SQNR (Signal-to-Quantization- Noise Ratio).

[0025] In the example illustrated in Figure 1, the low frequency component of Aix for a general chopping frequency fchp is given by 2. fchp, - ^ - ·

This corresponds to_¾ ^ , Fi[6fe] . Since the full scale feedback current is given by v[k]/R, it follows that the normalized level of chopping artifacts due to Cpl is 2fchp.Cpl/G_0ta. Chopping also causes abrupt changes in voltage across the OTA's output parasitic Cp2 at every chopping edge. This abrupt change in voltage causes two problems. First, integrated shaped quantization noise from multiples of 2fchp aliases into the signal band of interest, due to sampling at every edge of fchp.

Analysis shows that this in-band aliased noise is proportional to^{* '},^*' Second, switching Cp2 at 2fchp forms a switched capacitor resistor _^ ^ ^ at the OTA output, degrading its DC gain. This is a problem, as 1/f noise of the loop filter is larger when referred to the CTA∑M input.

[0026] Conventionally, in-band chopping artifacts are reduced by increasing Gota, so that the virtual ground swing (1/RGota) is smaller; however this is not a power efficient solution. Alternatively, the step size of the feedback waveform could be reduced by employing a multibit quantizer. For example, a 15-level quantizer instead of a single-bit one reduces out-of-band noise spectral density by only 24 dB, which is not adequate, and needs (Dynamic Element Matching) DEM, which complicates DAC design.

[0027] Alternatively, the chopping frequency can be chosen to be fchp = fs. However, chopping the OTA (104) at fs is problematic as the chopping switches (102 and 106) are activated more often, mismatch in their injected charge may be larger. Further, reduced OTA DC gain due to the switching of capacitance Cp2, increases the input referred offset and 1/f noise from the loop filter (108). Finally, rapidly switching the OTA (106) degrades its linearity.

[0028] Therefore, the present subject matter relates to a delta sigma modulator (ΔΣΜ) comprising a chopped integrator and a digital filter that addresses the aliasing of quantization noise while maintaining low power consumption and linearity. According to an embodiment of the present subject matter, in the delta- sigma modulator (ΔΣΜ), a first amplifier of an integrator is chopped at a low frequency, for example, at (fs/24), and quantization noise aliasing is reduced by using the digital filter, for example, an FIR filter. The digital filter is configured with a transfer function to introduce spectral nulls in a feedback waveform at all even multiples of the low frequency fs/24, which in turn is equal to 2fchp, where fchp is the chopping frequency. Thus, shaped noise at frequencies those can potentially alias in-band is attenuated.

[0029] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0030] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment. Further, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments.

[0031] According to an embodiment of the present subject matter, delta sigma modulator is an M-bit delta sigma modulator comprising at least one integrator, a loop filter, a M-bit analog to digital converter (ADC), at least one filter, and a Q- bit digital to analog converter (DAC). The at least one integrator generates an integrated signal. The at least one integrator is realized using plurality of amplifiers, wherein an amplifier of the plurality of amplifiers is chopped at a chopping frequency (f_ChP) in an amplification path of the at least one integrator, wherein the chopping frequency (f_ChP) is 1/N times of a predetermined sampling frequency (f_s). In an example, the amplifier of the at least one integrator is an operational amplifier or a transconductance amplifier or an operational transconductance amplifier (OTA).

[0032] The loop filter is coupled to the at least one integrator to generate a filtered analog signal, wherein the loop filter comprises a transitive cascade of integrators. In an example, the loop filter is in one of feedforward topology, negative feedback topology, and combination of both. The M-bit analog to digital converter (ADC) is to convert the filtered analog signal to a M-bit digital signal (D) sampling at the predetermined sampling frequency (f_s). The at least one filter is provided in a feedback path to receive the M-bit digital signal (D) and generates a filtered digital signal, wherein the at least one filter is configured with a transfer function. A Q-bit digital to analog converter (DAC) is coupled to the at least one filter to convert the filtered digital signal into a negative feedback analog signal.

[0033] Figure 2A illustrates a delta sigma modulator with a feedback digital filter, according to an embodiment of the present subject matter. The delta-sigma modulator (200), hereinafter referred to as modulator, is operable to receive an analog input voltage Vi_n (201) and convert it into a digital output pulse string (D) having an average amplitude over time proportional to the analog input voltage V_in (201). The output of the modulator (200) is input to a digital filter (210) to filter undesired signal and noise to provide a filtered output.

[0034] The delta sigma modulator (200) is a M-bit digital sigma modulator that has a summing junction (202) for receiving the analog input voltage Vin (201) and summing it with a negative feedback analog signal (201-3) from a feedback path (220-1). The output of the summing junction (202) is input to at least one integrator (204). The at least one integrator (204), for example, is a first integrator which is chopper stabilized. The at least one integrator (204) is realized using plurality of amplifiers, wherein an amplifier of the plurality of amplifiers is chopped at a chopping frequency (fchp) in an amplification path of the at least one integrator, wherein the chopping frequency (fchp) is 1/N times of a predetermined sampling frequency (fs). The at least one integrator (204) has an output integrated signal (201-1), which is fed as an input to a second integrator shown as Loop filter (206), built with an amplification path that is configured with a plurality of amplifiers). The circuit construction of the loop filter (206) is discussed in Figure 2A. The loop filter is constructed with a transitive cascade set of a plurality of integrators (204-1 to 204-n) Figure 2B illustrates the loop filter (206) with each integrator of the loop filter (206) built with an amplification path configured with a plurality of amplifiers. Each of the integrator cascade stages in the plurality of integrators contains a feedback of the of the output digital signal (D). The output of the loop filter (206), which is a filtered analog signal (201-2) is provided as an input to an analog-to-digital converter (ADC) (208) that is clocked at a predetermined sampling frequency (fs), the output of which provides a digital signal (D). The output of the ADC (208), which is an M-bit digital signal is provided to the input of a Q-bit digital-to-analog converter (DAC) (212) through the digital filter (210). The digital filter (210) is provided on a feedback path (220- 1) to generate a filtered digital signal which is fed into the Q-bit DAC, which in turn generates a negative feedback analog signal (201-3). According to an embodiment, bit width of Q of the Q-bit (DAC) (212) is equal to or greater than or lesser than a bit width of M of the M-bit digital signal (D). This configuration of a Q-bit DAC (212) and the digital filter (210) feedback is provided to one or more stages of the transitive set of integrators (204-1 to 204-n).

[0035] The at least one integrator (204) is comprised of a plurality of amplifiers, wherein an amplifier of the plurality of amplifiers is chopped at a chopping frequency (fchp) which, in the preferred embodiment, is 1/N of the predetermined sampling clock frequency (fs). As will be described herein below, the 1/f noise and DC offset errors are translated to a higher frequency by the at least one integrator (204) which is chopper stabilized and this noise is then filtered out by the digital filter (210). In an example, the at least one integrator (204) is realized using Transconductance-capacitance (Gm-C), active resistance capacitance (active-RC) or Transconductance-Operational Transconductance Amplifier-Capacitance (Gm-OTA-C) techniques. Delta sigma modulator (100) may be Continuous time sigma delta modulators using continuous-time active-RC filter comprising a set of opamp integrators with Operational Transconductance Amplifiers (OTAs). In accordance with an embodiment, the set of opamp integrators includes at least one single stage transconductor as the Operational Transconductance Amplifier (OTA).

[0036] In accordance with another embodiment, the set of opamp integrators includes at least one Miller compensated Operational Transconductance Amplifier (OTA), at least one two stage feed forward Operational Transconductance Amplifier (OTA) or the Operational Transconductance Amplifier (OTA) is implemented as a folded cascode structure.

[0037] According to an embodiment, the digital filter (210) of Figure 2A is a finite impulse response (FIR) filter. In an example, the FIR filter is realized with an FIR digital processor (DSP) which is operable to be interfaced with a FIR controller that controls the operation of the FIR DSP in accordance with FIR coefficients stored in a memory. In an example, the FIR DSP may be an arithmetic logic unit (ALU), which has the input thereof multiplexed to perform the calculations necessary to realize filter transfer function. The digital output pulses (D) from the modulator (200) is processed through the FIR DSP in accordance with the coefficients stored in the memory. For example, the FIR filter DSP under the control of the FIR controller therefore provides decimation of the output of the modulator (200).

[0038] In addition, the filter transfer function configured in the digital filter (210), in the preferred embodiment, introduces spectral nulls or zeros at the chopping frequency (fchp) such that maximum rejection is realized at the harmonics of the chopping frequency (fchp). The harmonics may be odd harmonics or even harmonics or both. This aspect of the present subject matter, in that the FIR filter response now provides a rejection of the 1/f noise that was modulated to the chopping frequency (fchp) by the chopper stabilized amplifier of the at least one integrator (204) of the modulator (200).

[0039] In the following, chopper modulation of exemplary sigma-delta modulator is described to provide a more thorough understanding of the subject matter disclosed herein, followed by several example implementations of embodiments of the herein disclosed subject-matter.

[0040] Figure 2B illustrates a circuit implementation of loop filter of Figure 2A comprising a cascade of integrators, according to an embodiment of the present subject matter. The loop filter (206) comprises cascade of integrators (204-1, 204-2, 204-3... 204-n). According to an embodiment, the cascade of integrators is comprised of a first integrator having a first amplifier chopped at the chopping frequency (fchp). An analog input voltage (Vin) (201) is fed as an input to each of the cascade of integrators (204-1, 204-2, 204-3... 204-n). Further, in addition to the analog input voltage (Vin) (201), a negative feedback analog signal (201-3) is fed as an input to each of the cascade of integrators (204-1, 204-2, 204- 3... 204-n). The negative feedback analog signal (201-3) and the analog input voltage (Vin) (201) are summed at input summation blocks (202-1, 202-2, 202- 3...202-n).

[0041] Signal (201-1) is representative of the output of the at least one integrator shown in Figure 2A. This integrated signal (201-1) is provided to the input summing block (202-1) of the second integrator (204-1) along with the negative feedback analog signal (201-3) and the analog input voltage (Vin) (201). Subsequently, output from the second integrator (204-1) is fed into the input summing block (202-2) of the third integrator (204-2) along with the negative feedback analog signal (201-3) and the analog input voltage (Vin) (201). Thus, this configuration provides a series of integrators connected in a fashion as shown in Figure 2B. Further, in the configuration a first feedback signal (230) from the output of the second integrator (204-1) is fed into the input of a first integrator. Subsequently, a second feedback signal (230-1) from the output of the third integrator (204-2) is fed into the input of the second integrator (204-1). This configuration extends in a similar fashion up to n-integrators as shown in Figure 2A. Further, a signal at the output of the summation block (202-n) is representative of the filtered analog signal (201-2), which is the output of the loop filter (206) (as shown in Figure 2). The filtered analog signal (201-2) is a sum of the outputs of each of the cascaded integrators (204-1, 204-2, 204-3... 204-n) of the loop filter (206). This filtered output signal (201-2) is fed into a quantizer (208) (as shown in Figure 2) in the form of an analog-digital converter (ADC). The quantizer may be an M bit quantizer providing an M bit digital output (D). The M-bit digital output (D) is then fed into a feedback path (220-1) as a feedback signal. The feedback signal is representative of the output of the quantizer. In accordance with an embodiment, the feedback path (220-1) comprises a combination of Q-bit digital-to-analog converters (DAC) (212-1, 212-2 ...212-n) and digital filters (210-1, 210-2...210-n). The feedback path (220-1) may include one or more feedback loops (250, 250-1... 250-n) as shown in Figure 2A, each comprising a DAC and a digital filter. Each digital filter in turn comprises a transfer function that introduces spectral nulls in the feedback signal at multiples of 2*(fs/N), where N may range from 0 to a large integer. In accordance with an embodiment, the feedback path (220-1) comprising digital-to-analog converter (DAC) serves to provide the negative feedback analog signal (201-3) to input of each of the cascaded integrators (204-1, 204-2, 204-3... 204-n).

[0042] The chopper modulation in the first integrator as shown in Figure 2A provides suppression of low frequency noise. However, a drawback of quantization noise at high frequency in the quantizer output, for example, the ADC output, can be folded back into a (low frequency) signal band of interest. This folding back of quantization noise may occur due to non-idealities of the chopping modulation. Further, due to sampling at the ADC, quantization noise present in the spectrum at frequencies 2fchp will fold around DC, increasing the noise floor in the signal band of interest. This effect may then degrade the signal- to-noise ratio of the modulator.

[0043] Therefore, the feedback signal in the feedback path (220-1) contains both signal components and quantization noise, which is fed as input to each of the digital filters in each feedback loop (250, 250-1... 250-n). Such quantization noise is attenuated by the digital filters (210-1, 210-2...210-n) provided in the feedback path (220-1) having transfer functions represented in z domain and is coupled between an output of the quantizer (208) and the feedback path (220-1). The digital filters (210-1, 210-2...210-n) according to an embodiment are added after the quantizer (208) (i.e. coupled between the output of the quantizer and the feedback path). According to an embodiment, the digital filter is configured to process the quantizer output, which is an M-bit digital signal (D) and to generate a negative feedback analog signal (201-3) by means of DAC coupled to it. The digital filters 210-1, 210-2...210-n) are comprised of L taps, where L is an integer. The tap weights of all L-taps in the digital filters, in accordance to the preferred embodiment, are equal to 1/N, where L may be greater than N. In accordance with another embodiment, the taps weights of L taps are chosen so as to introduce spectral nulls in the feedback signal at all multiples of fs/N, and wherein the chopping frequency (fchp) of the first integrator (204) is chosen as fs/(2N). Further, in accordance with another embodiment, a transfer function of each digital filter or the taps weights of L taps are chosen so as to introduce two zeros each at multiples of 2fs/N, and wherein the chopping frequency (fchp) of the first integrator (204) is chosen as fs/ (N).

[0044] According to an embodiment, the digital filters (210-1, 210-2...210-n) are implemented as FIR filters. For example, if the chopping frequency (fchp) is chosen as fs/N, where fs is the sampling frequency of the quantizer and N is an integer, the digital filters (210-1, 210-2...210-n) can be implemented as FIR filters with input-output response in the Z-domain, in which the response has spectral nulls at even or odd harmonics of the chopping frequency (fchp). According to another embodiment, the response has spectral nulls at specific multiples of the chopping frequency (fchp).

[0045] Figures 3A and 3B illustrate an example circuit implementation of a first integrator of Figure 2A, according to an embodiment of the present subject matter. Figure 3A depicts symbolic representation of the first integrator (304) in form of an Operational Transconductance Amplifier- RC and/or opamp-RC implementation. Figure 3B depicts symbolic representation of the first integrator (304) in form of a Transconductor Capacitor based implementation (Gm-C). In the figure, DAC (302) provided converts digital signal into a reconstructed representation of analog input signal (Vin). In particular, reconstructed signal (302-1) from the DAC (302) is applied to difference circuit (301) as a negative feedback. The difference circuit (301), for example, is a summing block at an input of the first integrator (304). In the example, the first integrator (304) is shown in the form of OTA-RC implementation. Difference circuit (301) generates a difference signal (301-1) representative of the difference between input signal and reconstructed signal (302-1) and provides the difference signal (301-1) to an input of first integrator (304). The first integrator integrates the difference signal (301-1) provided by difference circuit (301). In other words, the first integrator (304) integrates the output according to the difference between input signal (Vin) and the reconstructed signal (302-1)

[0046] In the example, transconductors are chosen as an integrator owing to its versatility when being employed in many analog and mixed-signal circuit applications, such as continuous-time filters, delta-sigma modulators, variable gain amplifier or data converter. The transconductors perform voltage-to -current conversion. Linearity is one of most critical requirements in designing these transconductors. Especially in designing delta-sigma modulators for high resolution Analog/Digital converters, it needs high linearity transconductors to accomplish the required signal-to-noise distortions ratio.

[0047] In the example illustrated in Figures 3 A and 3B, integrators are differential integrators. As will be described in more detail in Figures 4A and 4B, integrator may include a transconductance amplifier that outputs differential current signals that represent the difference between input signal and the reconstructed signal. The differential current signals drive capacitive loads that effectively integrate the difference signal to generate differential voltage signals. Common mode feedback (CMFB) local to the integrator maintains a constant common mode voltage at the outputs. The differential voltage signals are of an equal magnitude and opposite polarities, and represent the integrated difference between the input signal and the reconstructed signal. However, conceivable are other examples, in which the integrator need not be a differential integrator.

[0048] On the other hand, integrators as active RC filters using the operational amplifier (opamp) are widely used. These filters, for example, are used in low frequency applications, such as telecommunication networks, signal processing circuits, communication systems, control, and instrumentation systems. However, another approach is to use the Operational Transconductance Amplifier (OTA) to replace the conventional opamp in active RC filters. An ideal the Operational Transconductance Amplifier is a voltage-controlled current source, with infinite input and output impedances and constant transconductance. The OTA may be implemented widely in CMOS, and bipolar, and also in BiCMOS and GaAs technologies. The CMOS OTA, for example, can work typically in the frequency range of 50 MHz to several 100 MHz. OTA active filters have advantages such as low power consumption, noise, parasitic effects, and cost.

[0049] As shown in Figure 3 A and Figure 3B, both the example integrators are fully-differential amplifiers. Both types of amplifiers have differential inputs. Fully differential amplifiers have differential outputs, while a standard operational amplifier's output is single-ended. In the fully-differential amplifier architecture, the output is differential and the output common-mode voltage can be controlled independently of the differential voltage. Such a differential amplifier architecture generally requires a CMFB circuit (Common Mode Feedback Circuit) for setting the common-mode voltage, which usually lies in the middle between the positive and negative supply voltages.

[0050] The amplifiers of the integrators as depicted in Figures 3 A and 3B are realized using various forms of transistors, which are disclosed in detail in Figures 4A and 4B. Figure 3 A is a circuit diagram showing an example of the circuit construction of an OTA-RC amplifier. The amplifier demonstrates a configuration in which differential inputs (ip and im), and differential outputs (op and om) are used. In the Figure, the opamp receives input voltages xp and xm at the non- inverting and inverting inputs respectively. The input current passes through a resistor R to provide the input voltages. As discussed previously, the output of digital to analog converter is provided as an input to the amplifier. The amplifier is chopped at a chopping frequency (fchp), which is equal to 1/N times of the predetermined frequency (fs). The output of the chopped amplifier (op and om) is fed into an analog to digital converter of the delta sigma modulator. The output of the capacitor C in the amplifier may be provided as a feedback, and is indicative of an output which is the integral of the input signal

[0051] Figure 3B depicts the Gm-C filter, which refers to a filter composed of a transconductor (Gm) which converts a voltage signal into a current signal and a capacitor (C) which integrates the current signal. The Gm-C filter, as shown in the figure, has a fully-differential structure. Therefore, a common- mode feedback circuit is required to stabilize a bias point (also referred to as a common-mode operating point) of a differential output. In general, a Gm-C-type filter is used as the loop-filter in order to achieve desired filter characteristics. In an example, the Gm-C-type filter has the configuration in which a voltage-to- current converting amplifier (OTA: the Operational Transconductance Amplifier) is used in the feed-forward path to compensate for phase delay. The Gm-C type integrator may be useful because it consumes relatively less power. Moreover, Gm-C type integrators are generally limited by input differential range (i.e., the difference from DAC to input), thereby providing a linear circuit over a limited differential range. A high resolution DAC is helpful in that it helps limit the difference signal applied to the integrator. In other example embodiments, however, integrator may comprise an alternate type of differential integrator or a non-differential integrator.

[0052] Gm-C type filter includes voltage-to-current converting amplifiers (OTA), and capacitors at its output. Capacitors function as an integrator that converts the differential current (ip and im) into a differential voltage. Moreover, in an implementation, capacitors operate on the demodulated signal to pass the low frequency input signal components at baseband and substantially eliminate noise components that are located at a carrier frequency. In this manner, integration may be designed to provide a stable feedback path with acceptable bandwidth while also filtering out the 1/f noise and offset from measurement band. The voltage-to-current converting amplifiers (OTA) convert an input voltage signal from voltage to current so as to output a current signal. The respective output currents charge the output capacitors connected to the output nodes. As a result, voltages corresponding to the integration of the respective output currents are obtained. In this manner, a single voltage-to-current converting amplifier (OTA) and a single capacitor together constitute a single-stage integrator (low -pass filter).

[0053] Figure 4A illustrates an example of an OTA-RC integrator of Figure 3A, with a chopped feed-forward compensated OTA, according to an embodiment of the present subject matter. In the illustrated embodiment, delta sigma modulator utilizes a differential architecture that includes a differential integrator that outputs differential signals that are substantially the same in magnitude and substantially opposite in polarity. Other architectures may, however, be used without departing from the scope of this disclosure. As seen in Figure 4A, the symbolic representation of the OTA-RC chopped amplifier is expanded to demonstrate the circuit construction of the chopped amplifier. The figure depicts that an input differential signals (xp and xm) is chopped at a first chopping modulator (402) at a chopping frequency (fchp) at input nodes (a and c) of the first transconductance amplifier (404). The output of the first transconductance amplifier (404) at nodes (d and b) is again subjected to chopping at a second chopping modulator (406) to produce a chopped signal at nodes (e and f), which serves as an input to a second transconductance amplifier (408). The un-chopped differential signal (xp and xm) is fed into a third transconductance amplifier (410) in a feed-forward path to sum with the output signals (om and op) from the second transconductance amplifier (408). Further, the circuit construction of the OTA-RC integrator comprising the first, second and third transconductance amplifier is realized using transistors as shown in the figure. [0054] These transistors may include, but not limited to, metal oxide semiconductor field effect transistor (MOSFET), such as PMOS and NMOS transistors, as well as any other suitable form of transistors. In certain applications within transistors, as will be apparent to one of ordinary skill in the art, these transistors may be used as switches. In such cases, the use of the term "input" in connection with such switching transistors in the specification shall mean the terminal at which current flows into the transistor (e.g., the source in a PMOS transistor and the drain in an NMOS transistor), and the term "output" in connection with such switching transistors in the specification shall mean the terminal at which current flows out of the transistor (e.g., the drain in a PMOS transistor and the source in an NMOS transistor). Also, the resistors and capacitors used in the integrators may be implemented with transistor-based equivalents as known in the art when appropriate.

[0055] The first transconductance amplifier (404) includes PMOS transistor (420, 424), and NMOS transistors (422, 426) forming an input differential pair. The chopped signal from the nodes (a and c) are provided as the input differential pair. PMOS transistors (428, 430) serve as a current source pair. Also, the NMOS transistors (432, 434) serve as a current source pair, and the PMOS transistor (420, 424), and the NMOS transistors (422, 426) forming an input differential pair function as a source follower. The amplifier performs an amplification operation, with biases being applied to PMOS transistors (428, 430) and the NMOS transistors (432, 434). The gates of the NMOS transistors (432, 434) receive common feedback (CMFB). In the example, the currents running through the NMOS transistors (432, 434) are the same as the currents running through the PMOS transistors (428, 430). As a result, a differential output is taken at nodes (b and d) from the output of the PMOS transistors (428, 430), which receives the common feedback (CMFB).

[0056] The feedforward loop comprising the second and third transconductance amplifier (408, 410) includes PMOS transistors (420-1, 424-1) forming a first input differential pair, and NMOS transistors (422-1, 426-1) forming a second input differential pair. The feedforward inputs (xp and xm) are provided as the second input differential pair. The chopped signal at nodes (e and f) at the input of the second transconductance amplifier (408) is provided as the first input differential pair. The output of the PMOS transistors (420-1, 424-1) receives the common feedback (CMFB), and the gates of the NMOS transistors (432-1, 434-1) receive the same common feedback (CMFB). The differential outputs (op and om) are realized across the output of the PMOS transistors (420-1, 424-1) through capacitors connected in parallel with the common feedback (CMFB).

[0057] Similarly, Figure 4B illustrates an example of Miller compensated OTA, according to an embodiment of the present subject matter. The architecture and the realization of the Miller compensated OTA is similar to that of the OTA- RC integrator, which uses a combination of NMOS and PMOS transistors to demonstrate the circuit construction. In the Figure, a Miller capacitance Cc is provided between the input and the output of the second transconductance amplifier. The circuit further comprises two chopping modulators operating at chopping frequency (fchp), which is equal to 1/N times of a predetermined sampling frequency (fs).

[0058] The above illustrated example of differential integrators with compensation provides the advantage of being less affected by any common mode shift in the output voltage. Disturbances at the differential outputs are both shifted by approximately the same amount, thus resulting in little or no change in the difference between the differential outputs. Common mode shifts in the differential output voltages are rejected by a quantizer. In other words, noise or other disturbances will affect each of differential output voltages equally. Thus, the difference between the two signals is relatively unaffected. Typically, the output difference voltage is small because analog input signal does not experience large signal changes.

[0059] The above illustrated example configurations provides the benefits of higher resolution DAC feedback. The result is increased precision due to lower quantization noise without using high oversampling ratios or higher order loop filtering that consume large amounts of energy. Additional advantages are discussed in this disclosure or may occur to those skilled in the art upon consideration of this disclosure. Moreover, such advantages may not coexist in every embodiment. Further, a two-stage example was chosen to illustrate how additional stages may be added in accordance with certain embodiments of the invention.

[0060] Figure 5A illustrates a continuous time delta sigma modulator with a feedback FIR DAC, according to an embodiment of the present subject matter. The continuous time delta sigma modulator (CTDSM) (500), hereinafter referred to as modulator, receives an analog input signal Vin, which can be of any amplitude and any bandwidth, and can be single-ended or differential. The continuous time delta sigma modulator (CTDSM) (500) in the example is a 3rd order, 1-bit CTA∑M. The continuous time delta sigma modulator (500) converts the analog input signal Vin to digital form and provides a multi-bit (M-bit) digital output signal D for use in discerning and operating on information contained in the analog input signal Vin.

[0061] As illustrated in Figure 5A, the modulator (500) receives the analog input signal Vin and negative feedback analog signal (510-2) at a first summer (501) or summation node in a forward signal path or an input path (510). The input path (510) further includes a loop filter (502), an analog to digital A/D converter (504) as a quantizer. The loop filter (502) includes a cascade of integrators to generate a filtered analog signal (510-1). The A/D converter (504) converts the filtered analog signal (510-1) into a single or multi-bit digital output (D) at a sampling rate or frequency (fs) that is significantly higher than the Nyquist rate for the bandwidth of the analog input signal Vin (e.g., oversampling). In the illustrated example, a first integrator of the cascade of integrators in the loop filter (502) is chopped at a chopping frequency (fchp) as shown in the figure. The chopping frequency is 1/N times the sampling frequency (fs). [0062] The M-bit digital output (D) is then provided to a digital filter (506-1) or a decimation system and to a Q-bit digital to analog converter (DAC) (506-2). According to an embodiment, the A/D converter (504) is a flash ADC providing a 5-level (e.g., 3 bit) digital output (D) representative of the analog input Vin, however, any A/D converter type may be employed within the scope of the invention. The digital filter (506-1) receives the M-bit digital output (D) and further provides noise shaping for a quantization error associated with the A/D converter (504). The digital filter (506-1) is provided in a feedback path (512) coupled to the A/D converter (504) in the input path (510) and provides the negative feedback analog signal (510-2) through the DAC (506-2) to the first summer (501) in the input path (510) according to the M-bit digital output (D), wherein the negative feedback analog signal (510-2) is noise shaped with respect to the quantization error of the A/D converter. According to an embodiment, the multiples of twice the chopping frequency (2f_ChP) coincide with one or more frequencies of the negative feedback analog signal (510-2) at which there is a small spectral content.

[0063] In accordance with an embodiment, the modulator (500) includes at least one integrator amplifier chopped at a chopping frequency (fchp), and a feedback digital filter is employed in noise shaping the quantization errors. In this example, only a single stage of the integrator amplifier is copped. In the example, the modulator may be a first order modulator that quantizes the quantization noise created by the A/D converter, in the form of a digital output, which can then be operated on with a digital domain noise-shaping transfer function.

[0064] Further, the digital filter (506-1) in the feedback path (512), according to the illustrated example, is FIR (Finite Impulse Response Filter) with L-taps, where L is chosen as 12. Therefore, the feedback path (512) includes a 12-tap FIR filter (506-1) along with the DAC (506-2) to form a feedback 12-tap FIR DAC (506) to attenuate shaped quantization noise from the M-bit digital output (D). According to an embodiment, the tap weights of the feedback L-tap FIR DAC (506) is determined so as to provide spectral nulls at multiples of twice the chopping frequency, wherein the multiples of twice the chopping frequency coincides with one or more frequencies of the negative feedback analog signal at which there is a small spectral content. The feedback 12-tap FIR DAC (506) in this example is realized by analog, digital and semi-digital implementation or their combinations. The feedback 12-tap FIR DAC (506) attenuates the shaped quantization noise or error at twice the chopping frequency (2fchp), wherein the chopping frequency is equal to fs/N.

[0065] Thus, the quantization noise at the modulator output will be attenuated by the feedback FIR DAC (506) and will eventually be cancelled at the frequency locations at which spectral nulls are introduced by the transfer function (F(z)) of the feedback FIR DAC (506). Thus, by proper selection of the chopping frequency (fchp) and of the frequency response of the feedback FIR DAC, quantization noise can be minimized at the harmonics of the chopping frequency (fchp) and folding back can be avoided or at least be reduced, thus avoiding or at least reducing a signal to noise ratio degradation by the quantization noise. The transfer function of the feedback FIR DAC (F(z)) and the chopping frequency (fchp) can be chosen in many ways. One way to choose all tap weights to be equal to 1/N, so that there are nulls in the spectrum at all multiples of fs/N. The chopping frequency is then chosen as fs/ (2N). Another choice is to choose F(z) so that there are two zeros at the same frequency. For instance, rather than having nulls at fs/N, one could have two zeros, each at multiples of 2fs/N, and choose the chopping frequency to be fs/N.

[0066] Figure 5B illustrates a graph depicting Power Spectral density (PSD) for the continuous time delta sigma modulator of Figure 5A, according to an embodiment of the present subject matter. Figure 5B shows the PSD waveform plotted against f/fchp with and without 12-tap feedback FIR DAC. It is clearly evident from the graph of Figure 5B that the PSD keeps increasing when no feedback FIR DAC provided, which in turn is indicative of degradation of Signal to Noise Ratio. Further, by implementing the 12-tap feedback FIR DAC, spectral nulls are introduced at multiples of 2fchp, which in this example, is equal to fs/12, wherein the fs =6.144 MHz It is clearly evident from the graph of Figure 5A that the PSD is nullified at the specific multiples, which in turn is indicative of a good signal-to-noise ratio. Experimental results prove that the continuous delta sigma modulator with 12-tap feedback FIR DAC achieves 98.5 dB SNDR, 99.3 dB SNR and 103.6 dB DR in a 24kHz BW, while consuming only 280μ\¥ from a 1.8 V supply. Further, due to chopping at multiples of fs/N, the modulator achieves a 1/f noise corner of <10 Hz.

[0067] Figure 5C illustrates another graph depicting Power Spectral Density (PSD) for the continuous time delta sigma modulator of Figure 5A, according to an embodiment of the present subject matter. Figure 5C depicts a PSD comparison when the chopping frequency fchp=fs/24 and when fchp=fs/20. It is clearly evident from the experimental results provided in the graph of Figure 5C that when the fchp is chosen as fs/20, the multiples of 2fchp are no longer at the nulls of the feedback FIR DAC. This results in a much larger aliasing of shaped quantization noise into the signal band, which in turn increases the in-band noise floor to increase and many more spurious tones in the signal band, causing a SNDR (signal to noise distortion ratio) degradation of about 3db. In contrast, as evident from the plot of Figure 5C, a person skilled in art will be able to comprehend that when the chopping frequency is chosen as fchp=fs/24, aliased shaped noise is much more reduced than at fs/20. Experimental results prove that by choosing fchp=fs/24, aliased shaped noise is about 20 dB below thermal noise floor.

[0068] Figure 5D illustrates another graph depicting Power Spectral density (PSD) for the continuous time delta sigma modulator of Figure 5A, according to an embodiment of the present subject matter. Figure 5D is a comparison plot provided for the continuous time delta sigma modulator operating at the following conditions (i) without chopping (ii) providing input devices at 16x larger design (iii) providing a chopping frequency fchp=fs (iv) providing a chopping frequency fchp=fs/24. It is evident from the comparison plot provided that when designing continuous time delta sigma modulator by providing a chopping frequency fchp=fs/24, the power spectral density is lower compared to other conditions taken into consideration. Therefore, it is indicative that high SNDR (signal to noise distortion) is achievable at fchp=fs/24 by employing the feedback FIR DAC of Figure 5.

[0069] Figure 6 illustrates a flowchart of a method for generating an M-bit digital signal, according to an embodiment of the present subject matter. A method for converting an analog input signal (Vin) to a M-bit digital signal (D) is provided in the Figure 6. Although the operations of the method herein are shown and described in a particular order, the order of the operations of the method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.

[0070] At step 602, an analog input signal (Vin) is provided to a summing point, which is at an input of at least one integrator or cascade of integrators. According to an embodiment, the analog input signal (Vin) to an input of each of the cascaded integrators. At step 604, an integrated signal is generated by the at least one integrator in an input path comprising a loop filter and an analog to digital converter. The integrated signal is generated by chopping an amplifier of a plurality of amplifiers in the amplification path of the at least one integrator at a chopping frequency (fchp), wherein the chopping frequency (fchp) is 1/N times of the predetermined sampling frequency (fs). At step 606, the integrated signal is filtered by the loop filter to generate a filtered analog signal. At step 608, the filtered analog signal is converted into a M-bit digital signal (D) by the analog to digital converter.

[0071] At step 610, the M-bit digital signal (D) is fed into a FIR filter on a feedback path to generate a filtered digital signal. The filtered digital signal is comprised of spectral nulls at multiples of fs/N, and wherein value of N ranges from 2 to infinity. At step 612, the filtered digital signal is then fed into a digital to analog converter (DAC) to convert the filtered digital signal to a negative feedback signal. The output of step 612 is provided as an input to step 602.

[0072] It should also be noted that at least some of the operations for the methods may be implemented using software instructions stored on a computer useable storage medium for execution by a computer system. As an example, an embodiment of a computer program product includes a computer useable storage medium to store a computer readable program that, when executed on a computer system, causes the computer system to perform operations, as described herein.

[0073] For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the computer system, instruction execution system, apparatus, or device. The computer-useable or computer-readable medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device), or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disc. Current examples of optical discs include a compact disc with read only memory (CD-ROM), a compact disc with read/write (CD-R/W), a digital versatile disc (DVD), and a Blu-ray disc (BD).

[0074] Furthermore, embodiments of at least portions of the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer system or any instruction execution system. For example, the integrator, digital filter and/or other components of the embodiments of the invention may be implemented as software in a computer system, while the integrator, digital filter, quantizer and other components may be implemented as hardware or electrical circuits.

[0075] In one embodiment, the computer system that can be utilized to implement the modulator and/or other components includes one or more processors and memory, and may further include other devices such as communication devices (e.g., storage interfaces, network interfaces) and interconnects (e.g., buses, peripherals). The processor(s) may include central processing units (CPUs) and thus control operation of the computer system. In certain embodiments, the processor(s) accomplish this by executing software or firmware stored in memory. The processor(s) may be, or may include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable controllers, programmable logic devices (PLDs), or the like, or a combination of such devices. The memory may be or may include random access memory (RAM), read-only memory (ROM), flash memory, or the like, or a combination of such devices and may include the main memory of the computer system. In operation, the memory may contain, among other things, a set of machine instructions which, when executed by the processor(s), causes the processor(s) to perform operations to implement embodiments of the present invention.

[0076] In addition, although specific embodiments of the invention that have been described or depicted include several components described or depicted herein, other embodiments of the invention may include fewer or more components to implement less or more feature.

[0077] Furthermore, although specific embodiments of the invention have been described and depicted, the invention is not to be limited to the specific forms or arrangements of parts so described and depicted. The scope of the invention is to be defined by the claims appended hereto and their equivalents.

[0078] It should be noted that the description merely illustrates the principles of the present subject matter. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present subject matter and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be for explanatory purposes to aid the reader in understanding the principles of the present subject matter and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and implementations of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0079] Although implementations of present subject matter have been described in language specific to structural features and/or methods, it is to be understood that the present subject matter is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed and explained in the context of a few example implementations of the above-mentioned aspects of the present subject matter.

Claims

I/We claim:

1. A M-bit delta sigma modulator (200) comprising: at least one integrator (204) to generate an integrated signal (201-1), wherein an amplifier of a plurality of amplifiers in an amplification path of the at least one integrator (204) is chopped at a chopping frequency (f_Chp), and wherein the chopping frequency (f_Ch_P) is 1/N times of a predetermined sampling frequency (f_s); a loop filter (206) coupled to the at least one integrator (204) to generate a filtered analog signal (201-2), wherein the loop filter (206) comprises cascade of integrators (204-1, 204-2... 204-n);

a M-bit analog to digital converter (ADC) (208) to convert the filtered analog signal (201-2) to a M-bit digital signal (D) sampling at the predetermined sampling frequency (f_s);

at least one filter (210) provided in a feedback path (220-1) to receive the M-bit digital signal (D) and generate a filtered digital signal, wherein the at least one filter (210) is configured with a transfer function; and

a Q-bit digital to analog converter (DAC) (212) coupled to the at least one filter (210) to convert the filtered digital signal into a negative feedback analog signal (201-3).

2. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein a bit width of Q of the Q-bit (DAC) (212) is equal to or greater than or lesser than a bit width of M of the M-bit digital signal (D).

3. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein an output (230) of the loop filter (206) is a negative feedback to the input of the at least one integrator (204).

4. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the cascade of integrators (204-1, 204-2... 204-n) is comprised of a first integrator having a first amplifier chopped at the chopping frequency

5. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the amplifier of the at least one integrator (204) is an operational amplifier or a transconductance amplifier or an Operational Transconductance Amplifier (OTA).

6. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the transfer function of the at least one filter (210) introduces spectral nulls at multiples of 2*(f_s/N), and wherein value of N ranges from 2 to a large integer.

7. The M-bit delta sigma modulator (200) as claimed in claim 5, wherein the spectral nulls are introduced at specific multiples of the chopping frequency (f_chp).

8. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the at least one filter (210) is a Finite Impulse Response (FIR) filter comprised of L taps, and wherein tap weights of L-tap FIR filter are determined so as to provide spectral nulls at multiples of twice the chopping frequency

9. The M-bit delta sigma modulator (200) as claimed in claim 8, wherein one or more L-tap FIR filters and the Q-bit DAC are realized by a combination of an analog and digital implementation.

10. The M-bit delta sigma modulator (200) as claimed in claim 7, wherein the multiples of twice the chopping frequency (2f_ChP) coincide with one or more frequencies of the negative feedback analog signal (201-3) at which there is a small spectral content.

11. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the loop filter (206) is in one of feedforward topology, negative feedback topology, and combination of both.

12. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the M-bit digital signal (D) is comprised of a shaped quantization error or noise;

13. The M-bit delta sigma modulator (200) as claimed in claim 12, wherein the at least one filter (210) attenuates the shaped quantization error at twice chopping frequency (f_Ch_P), wherein the chopping frequency (f_Ch_P) is equal to f_s/N.

14. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the negative feedback analog signal (201-3) is fed into each input of the cascade of integrators (204-1, 204-2,... 204-n) of the loop filter (206).

15. The M-bit delta sigma modulator (200) as claimed in claim 1, wherein the feedback path (220-1) comprises the Q-bit DAC (210) and the at least one filter (212).

16. A method for converting an analog input signal (Vi_n) to a M-bit digital signal (D), the method comprising: generating an integrated signal (201-1) in an input path (220), wherein the integrated signal (201-1) is a signal chopped at a chopping frequency (f_Chp), and wherein the chopping frequency (f_Chp) is 1/N times of a predetermined sampling frequency (f_s); filtering the integrated signal (201-1) to generate a filtered analog signal (201-2), wherein the wherein the filtered analog signal is generated by a loop filter (206) comprising a cascade of integrators (204-1, 204-2... 204-n); converting the filtered analog signal (201-2) to a M-bit digital signal (D) by sampling at the predetermined sampling frequency (f_s).

17. The method as claimed in claim 16, further comprising: generating a filtered digital signal in a feedback path (220-1) by at least one filter (210) configured with a transfer function; and converting the filtered digital signal to a negative feedback analog signal (201-3) by a Q-bit digital to analog converter (DAC) (212).

18. The method as claimed in claim 16, wherein the integrated signal (201-1) is generated by chopping an amplifier of a plurality of amplifiers in the amplification path of at least one integrator (204) at a chopping frequency

19. The method as claimed in claim 16, wherein the filtered analog signal (201-2) is sampled at a predetermined sampling frequency (f_s).

20. The method as claimed in claim 16 to 19, wherein the chopping frequency (fchp) is 1/N times of the predetermined sampling frequency (f_s).

21. The method as claimed in claims 16 to 20, wherein the filtered digital signal is comprised of spectral nulls at multiples of f_s/N, and wherein value of N ranges from 2 to infinity.

22. The method as claimed in claim 17, wherein the negative feedback analog signal (201-3) is fed into an input of the at least one integrator (102).

23. The method as claimed in claim 16, further comprising:

providing an analog input signal (Vi_n) to the at least one integrator (204) and a loop filter (206), wherein the loop filter (206) is comprised of cascade of integrators ((204-1, 204-2,... 204-n), and wherein the analog input signal (Vi_n) is provided to input of each of the cascade of integrators (204-1, 204-2, ... 204-n).