EP1407554A1

EP1407554A1 - Bandpass sigma-delta analog-to-digital converter and mash sigma-delta converter incorporating same

Info

Publication number: EP1407554A1
Application number: EP02748926A
Authority: EP
Inventors: Patrick Radja; Michel Robbe; Hervé Guegnaud
Original assignee: EADS Telecom SAS
Current assignee: EADS Telecom SAS
Priority date: 2001-06-13
Filing date: 2002-06-04
Publication date: 2004-04-14
Also published as: FR2826207B1; FR2826207A1; US6943715B2; CA2450702A1; US20040174285A1; WO2002101932A1

Abstract

The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator (101) and a second order second resonator (102), preferably of second order, whereof the respective central frequencies are adjustable, so as to enable a high SNR in a relatively wide frequency band, and a MASH Sigma-Delta analog-to-digital converter incorporating at least two such cascaded converters.

Description

SIGMA-DELTA BANDPASS ANALOG-TO-DIGITAL CONVERTER AND SIGMA-DELTA MASH CONVERTER INCORPORATING

The present invention relates to a Sigma-Delta bandpass analog-digital converter, and a Sigma-Delta MASH converter incorporating it.

It relates to the field of analog-digital conversion, and in particular to oversampled or over-clocked analog-to-digital converters, better known under the name of Sigma-Delta converters (or Σ-Δ converters).

The invention finds applications in radiofrequency receivers, in particular of mobile stations or fixed stations of a radiocommunication system, for example a private professional radiocommunication system (PMR system, from the English "Private Mobile Radiocommunication"). In such an application, the signal to be converted is for example a signal containing about twenty channels each having a width approximately equal to 12 kHz (kilohertz), or a signal occupying a frequency band of total width equal to approximately 200 kHz .

Sigma-Delta converters are very widespread in the field of analog-digital conversion due to their high resolution (quantization is typically carried out on 16 bits, and even on 17 or 18 bits in some cases). This high resolution is obtained thanks to a high sampling frequency relative to the band of the converted signal (typically, the sampling frequency is of the order of megahertz or ten megahertz), which does not constitute a disadvantage in a radio frequency system.

The principle of a Sigma-Delta modulator is illustrated by the diagram of FIG. 1. In this figure, a low-pass Sigma-Delta modulator 100 has been represented which makes it possible to convert samples x (nT) of an analog signal input obtained at a determined sampling frequency, denoted Fs in the following, in values y (nT) of a digital output signal coded on n bits, where n is an integer. The converter 100 comprises an analog subtractor 11 whose positive input receives the samples x (nT), and whose negative input receives the samples x '(nT) of an analog feedback signal. The exit of the subtractor 11 is supplied at the input of a filter 12, the output of which is connected to the input of an analog-digital converter 10, hereinafter called CAN (or ADC in English, for "Analog-to-Digital Converter") . A feedback loop comprises a digital-analog converter 20, hereinafter called DAC (or DAC in English, for "Digital-to-Analog Converter"), which receives as input the values y (nT) of the digital output signal and the converts to deliver the x '(nT) samples of the above analog feedback signal.

In a low-pass Sigma-Delta analog-to-digital converter, which is suitable for analog-to-digital conversion of a baseband signal, the filter 12 is a low-pass filter. This achieves a shaping of the quantization noise ("Noise Shaping", in English), making it possible to reject the quantization noise towards the high frequencies.

The shaping of the quantization noise by the first order low pass filter is illustrated by the graph in FIG. 2. In this figure the energy density N of the quantization noise is represented as a function of the frequency f, for values of f between 0 and Fs. The higher the filter order, the greater the density of energy rejected at high frequencies.

Thus connected, the ADC converts, not the samples x (nT) of the input signal directly, but the difference between these samples x (nT) and the samples x '(nT) of the analog reaction signal, after shaping quantization noise by the filter 12.

The quantization noise is then eliminated, by a digital post-processing, by means of a decimation filter (not shown) receiving as input the values y (nT) of the digital output signal coded on n bits, and delivering as output digital values coded on n + m bits, where m is also an integer. Post-processing by the decimation filter operates a low-pass filtering, to attenuate the energy of the signal outside the useful band. It also has the function of reducing the sampling frequency to the Nyquist frequency, for example by averaging over several values of the consecutive output signal y (nT). For a low-pass Sigma-Delta analog-to-digital converter, the quantization noise shaping function corresponds to the inverse of a function cardinal sine ("sine" function), so that the transfer function of the decimation filter is a sine function, which is easy to perform.

When the converter is made with components in CMOS technology, which generate noise at zero frequency (frequency of the DC), it is preferable not to convert the signal to baseband. The signal is converted after frequency transposition in a frequency band between, for example, 400 kHz and 600 kHz. The signal to be converted is then centered on a central frequency Fo, equal to 500 kHz in this example. The shaping of the quantization noise by the low-pass filter of the converter then becomes a drawback, since the energy density of the quantization noise at the frequency Fo can be high, which greatly degrades the signal to noise ratio or SNR (from the English "Signal-to -oise Ratio").

This is why there is a need for Sigma-Delta bandpass analog-to-digital converters.

The principle of a Sigma-Delta bandpass converter 200 is illustrated by the diagram in FIG. 3, in which the same elements as in FIG. 1 bear the same references. In essence, this principle is similar to that of the Sigma-Delta low-pass converter 100, the low-pass filter 12 for shaping the quantization noise of the latter (FIG. 1) being nevertheless replaced by a resonator 13. It is recalled that a resonator is a bandpass filtering cell having an infinite gain at a determined frequency (corresponding to a pole of the transfer function) called the central frequency of the resonator. The central frequency of the resonator 13 is adjusted to the central frequency Fo of the frequency band of the signal to be converted.

The shaping of the quantization noise by a first-order resonator is illustrated by the graph in FIG. 4, to be compared to that of FIG. 2. As can be seen in this figure, the quantization noise is rejected by hand and on the other side of the central frequency Fo. The higher the order of the filter, the greater the energy density of the quantization noise thus rejected.

In practice, it is arranged so that the central frequency Fo of the band of the signal to be converted is equal to Fs / 4. This is known as "Fs / 4 mode" of the converter. The return to baseband at the converter output (in upstream of the decimation filter) is then ensured by simple numerical calculation operations, since it is a multiplication by the four values 1, 0, -1, and 0.

Examples of such converters are proposed, for example, in document US Pat. No. 5,383,578. In this document, embodiments are proposed in which the converter comprises two first or second order resonators in series, each having their center frequency adjusted to the center frequency Fo of the frequency band of the signal to be converted.

An important parameter of a Sigma-Delta bandpass converter is the width of the frequency band around the center frequency of the resonator, outside of which the quantization noise is rejected. This parameter has a direct influence on the SNR. The larger this width, the better the SNR.

In the prior art, two techniques are currently known which make it possible to increase the width of this strip:

- Either the sampling frequency Fs is increased, by ensuring, for example, that the central frequency Fo of the band of the signal to be converted is equal to Fs / 8 (we then speak of "Fs / 8 mode" of the converter ); this amounts to increasing the oversampling ratio or OSR (from the English "Over Sampling Ratio"), but we are limited for that by the characteristics of the amplifiers used for the realization of the converter;

- or we increase the order of the converter, which requires the use of special structures, the most common of which is the cascaded structure of the MASH type (see "Oversampling Delta-Sigma Data Converters - Theory, Design, and Simulation", Candy et al., IEEE Press, 1992), in order to circumvent stability problems; examples of converters thus having several cascade stages (so-called “Sigma-Delta MASH converter) are shown for example in the document US Pat. No. 5,383,578 cited above.

The invention aims to propose an alternative to these techniques of the prior art.

This object is achieved, according to the invention, thanks to an analog-digital converter Sigma-Delta bandpass comprising: a first analog adder receiving, on a first input, the samples of an analog input signal to be converted, and the samples of a first analog feedback signal on a second input;

- a first second order resonator whose central frequency is adjustable, receiving as input the samples delivered by the output of the first analog adder;

a second analog adder receiving, on a first input, the samples delivered by the output of the first resonator, the samples of a second analog feedback signal on a second input, and, in addition, the samples of the analog input signal to convert on a third input;

- a second second order resonator whose central frequency is adjustable, receiving as input the samples delivered by the output of the second analog adder; - an analog-digital converter receiving as input the samples delivered by the output of the second resonator and delivering as output values of a digital output signal corresponding to the converted analog input signal;

a first feedback loop which comprises a digital-analog converter receiving as input the values of the digital output signal, and which delivers the samples of the first analog feedback signal; and,

a second feedback loop which comprises said digital-analog converter and which delivers the samples of the second analog feedback signal.

The fact that the resonators have an adjustable central frequency makes it possible to increase the width of the frequency band outside of which the quantization noise is rejected.

Indeed, by setting the center frequency of the first resonator to a value slightly lower or higher than the center frequency of the frequency band of the analog input signal to be converted, and by setting the center frequency of the first resonator to a value respectively slightly higher or slightly lower than the center frequency of the frequency band of the analog input signal to be converted, a high SNR can be obtained in a relatively wide frequency band, of the order of 200 kHz.

The invention also relates to a Sigma-Delta MASH analog-digital converter, comprising at least a first and a second Sigma-Delta cascade bandpass analog-to-digital converter, as well as a recombination filter receiving the output signal from the first converter. on a first input and the output signal of the second converter on a second input, in which the first and / or the second converters are Sigma-Delta bandpass analog-digital converters as defined above.

The advantage of the Sigma-Delta MASH analog-digital converter of the invention lies in the fact that such an eighth order converter is obtained with only two stages, which reduces the space occupied by the converter on a silicon substrate.

Other characteristics and advantages of the invention will become apparent on reading the description which follows. This is purely illustrative and should be read in conjunction with the accompanying drawings, in which:

- in Figure 1, already analyzed: a diagram illustrating the principle of a low pass Sigma-Delta converter;

- in Figure 2, also already analyzed: a graph showing the shaping of the quantization noise by the converter of Figure 1;

- in Figure 3, also already analyzed: a diagram illustrating the principle of a Sigma-Delta bandpass converter; - in Figure 4, also already analyzed: a graph showing the shaping of the noise by the converter of Figure 3;

- in Figure 5: the diagram of a Sigma-Delta converter according to the invention;

- in Figure 6 and Figure 7: circuit diagrams for producing the resonators of the Sigma-Delta converter according to an advantageous embodiment of the invention;

- in Figure 8 and in Figure 9: graphs illustrating the shaping of the quantization noise by a Sigma-Delta converter according to the invention; - in Figure 10: a diagram illustrating the principle of a DAC with weighted current sources;

- in FIG. 11: a diagram illustrating the geographic distribution on a silicon substrate of 16 × 16 current sources entering into the composition of a DAC with 4 bits at input;

- in Figure 12: a table illustrating the control of 16 elementary current sources used in the composition of a 4-bit DAC, with pseudo-random interleaving of these sources;

- in Figure 13 and in Figure 14: graphs showing the shaping of the quantization noise, obtained by simulation respectively without and with pseudo-random interleaving of the elementary current sources of the DAC; and,

- in Figure 15: the diagram of a Sigma-Delta MASH converter according to the invention. FIG. 5 is a schematic representation of an analog-digital converter Sigma-Delta bandpass 300 according to the invention.

This converter 300 includes a first analog adder S1. This receives, on a first input, via a scaling circuit 53 whose gain J3 is positive, the samples x (nT) of the analog input signal x to be converted. It also receives, on a second input, the samples x1 '(nT) of a first analog feedback signal xV.

The converter 300 also includes a first resonator 101, preferably of the second order. The central frequency of the resonator 101 is adjustable. The resonator 101 receives as input the samples delivered by the output of the analog adder S1, corresponding to the analog sum of the samples x1 '(nT) and the samples x (nT) affected by the gain J3 of the scaling circuit 53. It delivers at the output of the samples j (nT) a signal j corresponding to the analog signal received at the input after bandpass filtering.

The converter 300 also includes a second analog adder S2. This receives, on a first input the samples j (nT) delivered by the output of the resonator 101. It also receives, on a second input, the samples x2 '(nT) of a second analog feedback signal x2' . Preferably, it also receives, on a third entry, via another scaling circuit 54 whose gain J4 is positive, the samples x (nT) of the analog input signal x.

The converter 300 also comprises a second resonator 102, preferably also of the second order, the central frequency of which is also adjustable. This receives as input the samples of the analog signal delivered by the output of the second analog adder S2, corresponding to the analog sum of the samples j (nT) and x2 ′ (nT), and in addition of the samples x (nT) affected by the gain J4 of the scaling circuit 54. It outputs the samples k (nT) of an analog signal k corresponding to the analog signal received as input after bandpass filtering. In the following, the signal k output from the resonator 102 is called band pass filtered analog signal. The order bandpass filtering to which reference is thus made is, in the example described, a fourth order filtering resulting from the second order filtering by each of the resonators 101 and 102. The converter 300 also comprises an analog-digital converter 103 with n bits at output, where n is an integer strictly greater than one. Preferably, n is equal to sixteen (n = 16). The CAN 103 receives as input the samples k (nT) of the filtered analog signal bandpass k, delivered by the output of the second resonator 102. It delivers at the output the values y (nT) of a digital signal y corresponding to the analog signal input x converted.

The converter 300 also comprises a first feedback loop 111 which comprises a digital-analog converter 104 with n bits at input. The DAC 104 receives the values y (nT) of the digital output signal y as an input, and outputs the samples x '(nT) of an analog signal x' corresponding to the converted output signal y. The feedback loop 111 also includes a scaling circuit 51, receiving the samples x '(nT) at the input and outputting the samples x1' (nT) of the aforementioned first analog feedback signal x1 '. The gain J1 of the scaling circuit 51 is negative, in order to obtain the desired feedback.

The converter 300 finally comprises a second feedback loop 112, which includes the CAN 104 and another scaling circuit 52, receiving the samples x ′ (nT) at the input and delivering the samples at the output. x2 '(nT) of the aforementioned second analog feedback signal x2'. The gain J2 of circuit 52 is also negative, in order to obtain the desired feedback.

In one example, the analog signal to be converted has a frequency band of the order of 200 kHz wide, corresponding to 20 channels of approximately 12 kHz wide each. This band is transposed to a central frequency Fo substantially equal to 1.2 MHz. Preferably, the sampling frequency Fs of the analog input signal x to be converted is such that Fo is equal to a quarter of Fs (Fo = Fs / 4). This simplifies the return to baseband of the signal of the digital output signal (i.e., after analog-digital conversion). In the example Fs is therefore equal to 4.8 MHz.

In the following, the respective transfer functions of the first resonator 101 and the second resonator 102 are denoted H1 (z) and H2 (z) respectively, where z denotes the discrete variable time frequency. In addition, we denote Θ1 and Θ2 the argument of the variable z for the transfer function H1 (z) and for the transfer function H2 (z) respectively. Recall that the argument θ of the variable z is such that θ = 2.π.f / Fs, where f denotes the frequency.

By taking into account these notations, and by also designating by cos the cosine function, the transfer function H1 (z) of the resonator 101 is preferably given by the following relation: (cosθ1 xz - z- * and the transfer function H2 (z) of the second resonator 102 is preferably given by the following relation:

They are therefore bi-quadratic functions, that is to say quadratic functions in the numerator and the denominator.

Preferably, the resonator 101 and the resonator 102 are of identical structure, that is to say that their respective transfer functions are performed by identical electronic components. This simplifies the design, testing and implementation of the converter on a silicon substrate. In this case the resonator 101 and the resonator 102 are filters second order analogs. Preferably, they have a structure with switched capacities, with adjustment of the parameter respectively cosθl or cosθ2, via a respective variable capacity. By switched capacity is meant a capacitor having an ISAM upstream serial switch and an ISAV downstream serial switch, respectively in series with each of these terminals on the one hand, and in addition an IPAM upstream parallel switch and an IPAV downstream parallel switch, parallel respectively with each of its terminals on the other hand (see for example the switched capacity CO1 in the diagram in FIG. 6). Unless otherwise stated, the free terminal of the parallel switches IPAM and IPAV of each switched capacity to which reference is made below, is connected to earth. Switched capacity filters are well known to those skilled in the art and do not call for specific comments here.

In Figure 6, there is shown schematically a possible embodiment of the resonator 101, further including the adder S1 in a particular case where J1 = -J3 and where J2 = - (J4 + 1).

The resonator 101, which here has a switched capacitor structure, comprises two integrating stages. Each of these stages comprises an operational amplifier 61A and 62A respectively, in series via a switched capacitor C12. The output of the resonator 101 is taken from the output of the amplifier 61 A, which therefore delivers the analog signal j. The non-inverting inputs of amplifiers 61 A and 62A are connected to ground. The output of amplifier 61A is connected to its inverting input via a capacitor C1A. In addition, the output of the amplifier 62A is connected to its inverting input via a variable capacitor C2A, making it possible to adjust the above-mentioned cosθl parameter. Furthermore, the inverting input of amplifier 61 A receives the analog input signal x (multiplied by the gain J3 of the scaling circuit 53) via a switched capacitor C01. The first feedback signal x1 'is carried on the free terminal of the upstream parallel switch IPAM of the switched capacity C01, the latter not being connected to ground. The switched capacity C01, thus connected, forms the analog adder S1. In addition, the inverting input of amplifier 61 A is connected to the output of amplifier 62A via a switched capacitor C21. Finally, the inverting input of amplifier 62A receives the analog input signal x (multiplied by the gain J3 of the setting circuit. scale 53) via another switched capacitor C02. The first feedback signal x1 'is carried on the free terminal of the upstream parallel switch

IPAM of the switched capacity C02, this one not being connected to the ground.

If the following relationships are also provided: C01 = l01xC1A;

C21 = S21xC1A;

C12 = 12xC2A; and,

C02 = I02XC2A, where 101, S21, 112 and I02 are appropriate parameters, then we can show that the transfer function H1 (z) of the resonator 101 is given by the following relation: uι _{/ \} - (I01-I02X S21) X ZI -I01X Z-2

^{H1 (Z)} ~ 1 - (2-I12X S21) X ZI + Z-2 ⁽³⁾

If in addition, we provide 101 = S21 = 1, then the relation (3) is identified with the relation (1) above, by also posing I02 = (1 -cosθl) and 112 = 2x (1 -cosθl ). In Figure 7, there is shown schematically a possible embodiment of the resonator 102, further including the adder S2.

The resonator 102, which also here has a switched capacitor structure, comprises two integrating stages. Each of these stages comprises an operational amplifier 61B and 62B respectively, in series via a switched capacitor C12. The output of the resonator 102 is taken from the output of the amplifier 61 B, which delivers the filtered analog signal bandpass k. The non-inverting inputs of amplifiers 61 B and 62B are connected to ground. The output of amplifier 61 B is connected to its inverting input via a capacity C1 B. In addition, the output of amplifier 62B is connected to its inverting input via a variable capacity C2B, making it possible to adjust the aforementioned parameter cosθ2 . Furthermore, the inverting input of amplifier 61 B receives, firstly the analog signal j via a switched capacitor C01, and secondly the analog input signal x (multiplied by the gain J4 of the scaling circuit 54 ) via another switched capacity C01. The second feedback signal x2 'is carried on the free terminal of the upstream parallel switch IPAM of each of the two switched capacitors C01 mentioned above, the latter not being connected to ground. The switched capacities C01, as well switched, form the analog adder S2. In addition, the inverting input of amplifier 61 B is connected to the output of amplifier 62B via a switched capacitor C21. Finally, the inverting input of amplifier 62B also receives, firstly the analog signal j via a switched capacitor C02, and secondly the analog input signal x (multiplied by the gain J4 of the scaling circuit 54 ) via another switched capacitor C02. The second feedback signal x2 'is carried on the free terminal of the upstream parallel switch IPAM of each of the two above-mentioned switched capacitors C02, the latter not being connected to ground. If the following relationships are also provided:

C01 = I01XC1 B;

C21 = S21xC1 B;

C12 = 12xC2B; and,

C02 = I02XC2A, where 101, S21, 112 and I02 are the appropriate parameters mentioned above, then we can show that the transfer function H2 (z) of the resonator 102 is given by the following relation: u _/ - (I01-I02X S21) X ZI -I01 X Z-2 ...

^{H2 (Z) "} 1- (2-l12χS21) xz-ι ₊ z-2 < ⁴ >

If in addition, we provide 101 = S21 = 1, then the relation (4) is identified with the relation (2) above, by also posing I02 = (1-cosθ2) and 112 = 2x (1-cosθ2 ).

The values of the capacitors C2A and C2B are adjustable, and it is by them that we can adjust the values of the parameters cosθl and cosθ2 respectively, which determine the exact position of the poles of the transfer functions H1 (z) and

H2 (z) respectively. These capacities therefore make it possible to control the operating mode of the resonators 101 and 102 respectively (operation in Fs / 4 mode or in Fs / 8 mode, for example) and the adjustment of their central frequency.

In particular, when cosθl = cosθ2 = 0, the central frequency Fc1 and the central frequency Fc2 of the resonators 101 and 102 respectively are equal to a quarter of the sampling frequency (Fc1 = Fc2 = Fs / 4). This is then the Fs / 4 mode. Similarly, when cosθl = cosθ2 = + V2 / 2, the center frequencies

Fc1 and Fc2 respectively of resonators 101 and 102 are equal to the eighth the sampling frequency (Fc1 = Fc2 = Fs / 8). This is then Fs / 8 mode.

According to an advantageous embodiment, the center frequency Fc1 of the resonator 101 is slightly lower (respectively higher) than the center frequency Fo of the frequency band of the analog input signal x to be converted, and the center frequency Fc1 of the resonator 102 is slightly higher (respectively lower) than this central frequency Fo.

This adjustment is illustrated by the graphs of FIGS. 8 and 9, in a preferred embodiment in which the central frequency Fo of the frequency band of the analog signal x to be converted is equal to a quarter of the sampling frequency Fs (Fo = fs / 4). In FIG. 8, the curve 81 gives for example the shape of the quantization noise shaping by the resonator 101, and the curve 82 gives the shape of the shaping of the quantization noise by the resonator 102. In FIG. 9, the curve 90 gives the appearance of the shaping of the quantization noise by the Sigma-Delta bandpass converter 300 comprising the associated resonators 101 and 102. It will be noted that the same curve 90 would be obtained if the shaping of the quantization noise by the resonator 101 corresponding to the curve 82, the shaping of the quantization noise by the resonator 102 then corresponding to the curve 81. This would simply correspond an inversion of the position of the respective poles of the transfer functions H1 (z) and H2 (z) with respect to the frequency Fs / 4.

This setting widens the frequency band outside which the energy density N of the quantization noise is rejected. It is thus possible to obtain a satisfactory SNR in a wider band than with operation in Fs / 4 mode or in Fs / 8 mode.

The analog-digital converter 103 is preferably of the Flash type with n bits at output. Such a converter has the advantage of a high conversion speed, thanks to the absence of transient regimes. In addition, the digital-analog converter 104 is preferably also of the Flash type, with n bits at input, with weighted current sources. The advantage of such a converter is also due to the speed of the conversion. The principle of a DAC with weighted current sources, which is known in itself, is illustrated by the diagram in FIG. 10. The DAC comprises n current sources CSO to CSn-1 connected in parallel between a node A and a node B, and each in series with a control switch, respectively SWO to SWn-1. Current sources

CSO, CS1 CSi, ..., CSn-1, are said to be weighted in the sense that they deliver a current respectively lo, 2xlo, ..., 2'xlo, ..., 2 ^{n "1} xlo where lo is the current delivered by an elementary current source. A resistor R is furthermore connected between the nodes A and B. The control switches are controlled by n respective control signals, the logic state of which is determined by the information bits stored in a register (not shown), and corresponding to the digital value to be converted.The voltage Vout between nodes A and B constitutes the analog signal produced by the conversion.

In practice, the current sources SCO to SCn-1 are produced by 2 ⁿ elementary current sources, each delivering the aforementioned current lo, and one of which is not used. The current source CSO includes such an elementary current source. The current source CS1 includes two in parallel. The current source CS2 includes four in parallel. The current source CS3 includes eight in parallel. And so on. According to an advantageous embodiment, each of the 2 ⁿ elementary current sources consists of 2 ^π elementary current sub-sources, each delivering a current lo / 2 ^π . It is therefore a total of 2 ⁿ x 2 ⁿ current sources which are included in such a DAC. Typically, these are respective bipolar transistors. These current sources are preferably placed on a silicon substrate according to a determined geographic distribution of the 2 ^π x 2 ⁿ matrix type, with pseudo-random interleaving.

Said determined geographical distribution, which results in a particular drawing ("Layout" in English) on the silicon substrate, makes it possible to reduce the errors due to the variations of the currents supplied by each current source resulting from the imperfections of the production process (errors say "matching errors" of current sources). To this end, we make sure, on the one hand, to keep the respective implantation zones as far away as possible from the 2 ' elementary current current sources of each current sub-source SCi determined for i comprised between 0 and n − 1, and on the other hand to separate as much as possible the respective implantation zones of each elementary current sub-source d '' a determined elementary current source. The diagram in Figure 11 shows an example of such a geographic distribution of current sources. In this figure, we consider the example of a converter with four input bits (n = 4). The references of the type "i-1.j- 1" designate the implantation zone (here substantially a rectangle) on the silicon substrate, of the j-th elementary current sub-source of the i-th current source elementary, for i and j between 0 and 15.

The advantage provided by such a geographic distribution lies in the low non-linearity distortion (also called "Intégral Non-Linearity Error" or INL), which results in a reduction of stray lines ("Spurious", in present in the spectrum of the analog signal output from the DAC.

In addition, the pseudo-random interleaving (or mixing) of the current sources still makes it possible to reject part of the energy of these parasitic lines outside of the pass band. This object is achieved by periodically modifying the control bit of a current source with another control bit (these control bits being the binary data stored in the aforementioned register). The changes are made by following a pseudo-random law of length L. Admittedly, the periodicity of these modifications is at the origin of parasitic lines in the spectrum of the analog signal at the output of the DAC, but the value of L is chosen so that these lines are located outside the bandwidth.

The table in FIG. 12 illustrates the principle of this interleaving, still in the example of a converter with four bits at input (n = 4), and for a periodicity equal to four (L = 4). In this figure, we denote CO to C15 the control signals of the sixteen elementary current sources, and we denote InO to In15 the binary input values of the DAC. The leftmost column contains the values InO to In15 assigned to the signals CO to C15 at time t = to. The second column from the left contains the values InO to In15 assigned to the signals CO to C15 at time t = to + Ts, where Ts denotes the sampling period (Ts = 1 / Fs). The third column from the left contains the values InO to In15 assigned to the signals CO to C15 at time t = to + 2xTs. Finally, the fourth column from the left contains the values InO to In15 assigned to the signals CO to C15 at time t = to + 3xTs.

The graphs of FIGS. 13 and 14 show the curve of the shaping of the quantization noise, obtained by simulation software, respectively without and with interleaving of the current sources. As can be seen, the quantization noise is more strongly rejected outside the bandwidth (around 200 kHz around 1.2 MHz) thanks to interleaving. It has been measured that the improvement in the SNR in the passband which results from this interleaving is of the order of 2.3 dB (decibel).

A converter produced according to the present invention makes it possible to produce a radio frequency reception chain capable of complying with most of the current standards which govern radiocommunication systems (GSM standards, TETRAPOL, APCO 25, etc.).

In Figure 15, there is shown the diagram of an example of an analog-digital converter Sigma-Delta MASH according to the invention.

The structure of the MASH type, or cascaded structure, makes it possible to increase the order of the Sigma-Delta converter without incurring stability problems. With two Sigma-Delta converters of the fourth order cascades, we obtain indeed an analog-digital converter Sigma-Delta of type MASH of the eighth order. One can naturally further increase the number of Sigma-Delta converters of the fourth order thus cascades, in order to obtain an analog-digital converter Sigma-Delta of MASH type of higher order (multiple of four). However, in practice, an eighth order converter is sufficient for most applications.

In the example shown in FIG. 15, the Sigma-Delta MASH 400 converter comprises two cascade stages 300a and 300b, each of these stages being an analog-digital Sigma-Delta bandpass converter of the fourth order, as described below. above with reference to the diagram in FIG. 5. In FIG. 15, the same elements as in FIG. 5 bear the same references to which however the suffix "a" or the suffix "b" is added, to the first stage elements 300a and for the second stage elements 300b respectively. The first stage 300a outputs digital values y1 (nT) of an output signal y1. Likewise, the second stage 300b delivers digital values y2 (nT) as an output from an output signal y2. The structure of each floor is not described again here. It will only be noted that the scaling circuit 54b of the second stage 300b does not directly receive the input signal of the second stage 300b, but this input signal multiplied by the gain J3b of the scaling circuit 53b. It follows that the value of the gain J3b + J4b of the circuit 53b and of the circuit 54b put in series, corresponds to the value of the gain J4 of the shaping circuit 54 of the converter 300 of FIG. 5.

In order to ensure the connection between the two stages 300a and 300b, the converter 400 further comprises an analog subtractor 151, the positive input of which receives the samples x'a (nT) of the analog signal delivered by the output of the DAC 104a of the first stage 300a, and the negative input of which receives the samples ka (nT) of the filtered analog signal band pass ka of the first stage 300a. The output of subtractor 151 delivers samples of an analog signal corresponding to the difference of samples x'a (nT) and samples ka (nT). This analog signal, after passing through a scaling circuit 152 and through a self-timer 153, constitutes the analog input signal of the second stage 300b.

The converter 400 further comprises a recombination filter 154 which receives, on a first input, the output signal y1 of the converter 200a and, on a second input, the output signal y2 of the converter 200b. This filter 154 combines the values y1 (nT) and the values y2 (nT) of the digital signals y1 and y2 respectively, in order to produce the values y (nT) of the digital output signal y of the converter 400.

In an example, the transfer function R (z) of the recombination filter (230) is given by the following relation: R (z) = (z-3 x yl) + ¹ + 2- ^Z j + ^{z "2} x y2 (5)

where z denotes the discrete time-frequency variable, where y1 denotes the output signal of said first converter (200a), where y2 denotes the output signal of said second converter (200b), and where G denotes the gain of the scaling circuit 152 disposed between the converter 300a and the converter 300b.

Claims

1. Sigma-Delta bandpass analog-to-digital converter (300) comprising:

- a first analog adder (S1) receiving on a first input the samples of an analog input signal (x) to be converted, and the samples of a first analog feedback signal (x1 ') on a second input;

- a first second order resonator (101) whose central frequency is adjustable, receiving as input the samples delivered by the output of the first analog adder (S1); - a second analog adder (S2) receiving on a first input the samples delivered by the output of the first resonator (101), the samples of a second analog feedback signal (x2 ') on a second input, and in addition the samples the analog input signal (x) to be converted to a third input; - a second second order resonator (102) whose central frequency is adjustable, receiving as input the samples delivered by the output of the second analog adder (S2);

- an analog-digital converter (103) receiving as input the samples delivered by the output of the second resonator (102) and delivering as output the values of a digital output signal (y) corresponding to the analog input signal (x) converted;

- a first feedback loop (111) which comprises a digital-analog converter (104) receiving as input the values of the digital output signal (y), and which delivers the samples of the first analog feedback signal (x1 ');

- a second feedback loop (112) which comprises said digital-analog converter (104) and which delivers the samples of the second analog feedback signal (x2 ').

2. Converter according to claim 1, in which the first resonator (101) has a transfer function H1 (z) given by the following relation:

and / or wherein the second resonator (102) has a transfer function

H2 (z) given by the following relation:

where z designates the discrete time frequency variable, and where Θ1 and Θ2 designate the argument of the variable z, respectively for the transfer function H1 (z) and for the transfer function H2 (z).

3. Converter according to any one of claims 1 or 2, wherein the first resonator (101) and the second resonator (102) are of identical structure.

4. Converter according to any one of the preceding claims, in which the first resonator (101) and / or the second resonator (102) have a switched capacitance structure, with adjustment of the parameter cosθl and / or cosθ2 respectively via a variable capacitance respective (C2A, C2B).

5. Converter according to any one of the preceding claims, in which the sampling frequency (Fs) is substantially equal to four times the center frequency (F0) of the frequency band of the analog input signal (x) to be converted .

6. Converter according to any one of the preceding claims, in which the central frequency (F1) of the first resonator (101) is slightly lower or higher than the central frequency (F0) of the frequency band of the analog input signal ( x) to be converted, and in which the center frequency (F2) of the second resonator (102) is, respectively slightly higher or slightly lower than the center frequency (FO) of the frequency band of the analog input signal (x) to be converted.

7. Converter according to any one of the preceding claims, in which the analog-digital converter (ADC) is of the Flash type with n bits at output, where n is an integer strictly greater than unity.

8. Converter according to any one of the preceding claims, in which the digital-analog converter (DAC) is of the Flash type with n bits at input, with weighted current sources.

9. Converter according to claim 8, in which the current sources are produced on a silicon substrate according to a geographic distribution of the 2 ⁿ × 2 ⁿ matrix type, with pseudo-random interleaving.

10. Analog-digital converter Sigma-Delta of the MASH type, comprising at least a first (300a) and a second (300b) analog-digital converters Sigma-Delta bandpass cascades, as well as a recombination filter (154) receiving the output signal (y1) of said first converter (200a) on a first input and the output signal (y2) of said second converter (300b) on a second input, wherein said first and / or said second converters are converters according to any one of the preceding claims.

11. Converter according to claim 10, in which the transfer function R (z) of the recombination filter (154) is given by the following relation: R (z) = (z-3 x yl) + ¹ + ² - ^z _Q ¹ + ^{z "2} x y2 (5)

where z denotes the discrete time frequency variable, where y1 denotes the output signal of said first converter (300a), where y2 denotes the output signal of said second converter (300b), and where G denotes the gain of a scaling circuit (152) arranged between said first converter (300a) and said second converter (300b).