EP1367647A2 - Dispositif electro-optique, méthode de fabrication et appareil électrique - Google Patents

Dispositif electro-optique, méthode de fabrication et appareil électrique Download PDF

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Publication number
EP1367647A2
EP1367647A2 EP03253429A EP03253429A EP1367647A2 EP 1367647 A2 EP1367647 A2 EP 1367647A2 EP 03253429 A EP03253429 A EP 03253429A EP 03253429 A EP03253429 A EP 03253429A EP 1367647 A2 EP1367647 A2 EP 1367647A2
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EP
European Patent Office
Prior art keywords
layer
electro
optical device
light
metal layer
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Application number
EP03253429A
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German (de)
English (en)
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EP1367647A3 (fr
Inventor
Hayato c/o Seiko Epson Corporation Nakanishi
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Seiko Epson Corp
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Seiko Epson Corp
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Publication of EP1367647A3 publication Critical patent/EP1367647A3/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/26—Light sources with substantially two-dimensional radiating surfaces characterised by the composition or arrangement of the conductive material used as an electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the present invention relates to an electro-optical device, a method of manufacturing the same, and an electronic apparatus.
  • an electro-optical device such as anelectroluminescence (hereafter, abbreviated as EL) display device etc.
  • EL electro-optical device
  • the device is made by putting a light-emitting layer including a light-emitting material between electrode layers of anodes and cathodes, and the device utilizes a phenomenon of emitting light when the hole injected from anode sides are re-combined with an electron injected from a cathode sides in a light-emitting layer which has an ability of fluorescence, so that they lose their energy from excitation state.
  • the prior electro-optical device should form the metal layer as the base layer in order to form the anodes with reflectivity, thereby complicating manufacturing processes. As a result, manufacturing efficiency deteriorates and the manufacturing cost is expensive.
  • the anodes in order to give reflexibility to the anodes having good display properties while the light is not transmitted to the lower part of the anodes, the anodes should be flat. Therefore, it is difficult to efficiently use the space of the lower part in the hole.
  • an electro-optical device of the present invention comprises: first electrodes connected to switching elements; a second electrode arranged to oppose the first electrodes; light-emitting layers provided between the first electrodes and the second electrode; pixel display parts for regulating the light emitted from the light-emitting layers to the second electrode; a circuit layer provided under the first electrodes, the circuit layer having a laminated structure at least including the switching elements and power source lines for driving the light-emitting layers; and metal parts provided at positions overlapping the pixel display parts in the direction of lamination within the circuit layer, the metal parts reflecting the light emitted from the corresponding light-emitting layer.
  • the light beams transmitted through the first electrode are upwardly reflected at the metal part provided in the circuit layer and are emitted upwardly via the light-emitting layer, the pixel display part, and the second electrode.
  • the light from the light-emitting layer can be emitted toward the second electrode without giving reflexibility to the first electrode. Further, since it is unnecessary to transmit the light through a lower part of the metal part, it is possible to efficiently use the space thereof.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein the metal parts are provided at positions overlapping substantially the entire display area of each pixel display part.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein the surfaces of the metal parts are flatly formed within the overlapping region with the pixel display parts.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein layers below the metal parts in the circuit layer are formed in a beta-shaped pattern having a predetermined layer thickness within the overlapping region with the pixel display parts.
  • any one of the layers under the metal parts, which are formed in a beta-shaped pattern having a predetermined layer thickness, is flat within the overlapping region with the pixel display part. Since the metal part is formed on an upper layer in a beta-shaped pattern, flatness of the metal part is remarkably improved within the range of the pixel display part. As a result, reflection nonuniformity of the light is more suppressed and the use efficiency of light with display performance can be remarkably improved.
  • a predetermined range of beta-shaped pattern means that a certain thickness of layer is made of a single layer material within the predetermined range.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein power source lines for supplying electricity to the switching elements also serve as the metal parts.
  • the power source lines are provided in the overlapping region with the pixel display parts, it is possible to ensure the area of the power source line at least as large as the pixel display part and to form a relatively large electrostatic capacitor between the power source line and the second electrode. As a result, the display property can be stably secured and the display characteristics can be improved.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein the circuit layer has a first metal layer and a second metal layer on the first metal layer, and the second metal layer constitutes the metal parts.
  • the metal part is formed in the circuit layer by the upper second metal layer nearer to the first electrode than the first metal layer, the distance between the first electrode and the metal part can be made shorter than that between the first metal layer and the metal part. Further, the optical loss generated when the light from the light-emitting layer travels between the first electrode and the metal part, can be reduced. As a result, the use efficiency of light can be improved.
  • the circuit layer under the second metal layer becomes a space through which where the light does not have to be transmitted.
  • the efficiently available space can be thicker in the direction of lamination.
  • the electro-optical device of the present invention is the abovementioned electro-optical device wherein the second metal layer constitutes the power source lines for supplying electricity to the switching elements.
  • the process of manufacturing the metal part can be also used as a manufacturing process essential for forming the circuit layer. As a result, the manufacturing cost can be reduced.
  • the electro-optical device of the present invention is the same abovementioned electro-optical device wherein the first electrodes are provided on the metal parts, and they are electrically connected to each other.
  • the circuit layer such as an insulating layer is not included between the metal part and the first electrode, there is no optical loss when the light is transmitted through the circuit layer. Therefore, the use efficiency of light can be improved.
  • the manufacturing process can be simplified, the manufacturing cost can be reduced, and the productivity can be improved.
  • the electro-optical device of the present invention is the same abovementioned or the just abovementioned electro-optical device wherein the first metal layer constitutes the power source lines for supplying electricity to the switching elements.
  • the first metal layer constitutes the power source lines
  • the second metal layer for various purposes other than for the power source line while ensuring a wider power source line.
  • the potential of the metal part formed on the second metal layer can be freely set, and a configuration that does not cause a short circuit can be remarkably easily made, even though the metal part abuts the first electrode with no insulating layer.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein the switching elements are disposed between the adjacent pixel display parts.
  • the switching elements are disposed between the adjacent pixel display parts in the circuit layer, there is no possibility that the flatness of the pixel display part does not deteriorate due to a cubic shape of the switching element. For this reason, it is possible to flatly form the pixel display part with ease.
  • the electro-optical device of the present invention is any one of the abovementioned electro-optical devices wherein electrostatic capacitors are formed in the circuit layer between the power source lines and the second electrode at a position overlapping the pixel display parts, the capacitors being formed by the layers below the metal parts.
  • the electrostatic capacitor since the electrostatic capacitor is formed in the layers below the metal part located under the pixel display part, the electrostatic capacitor can be formed by efficiently using a space under the pixel display part. As a result, an area where the electrostatic capacitor is formed can be increased, so that the display can be stably held and the display property can be improved.
  • a method of manufacturing an electro-optical device of the present invention includes a circuit layer having a laminated structure; and first electrodes, light-emitting layers, and a second electrode sequentially provided on the circuit layer, the electro-optical device emitting light from the second electrode via pixel display parts for regulating, above the light-emitting layers, the light emitted from the light-emitting layers, wherein the method comprises a step of forming a metal layer in the circuit layer, and wherein metal parts are formed under the light-emitting layers simultaneously with the metal layer forming step.
  • the aforementioned electro-optical devices according to the present invention can be manufactured. Accordingly, the same effect as the electro-optical device of the present invention can be achieved.
  • the method of manufacturing the electro-optical device of the present invention is the manufacturing method of the electro-optical device described above, and the metal layer formation step comprises a first metal layer formation step of forming a first metal layer in the circuit layer, and a second metal layer formation step of forming a second metal layer after the first metal layer is formed, and metal parts are formed under the light-emitting layers simultaneously with the second metal layer formation step.
  • the electro-optical device According to such method of manufacturing the electro-optical device, it is possible to manufacture the aforementioned electro-optical devices according to the present invention, comprising the first metal layer and the second metal layer in the circuit layer. Therefore, the same effect as the electro-optical device of the present invention can be achieved.
  • an electronic apparatus of the present invention comprises the electro-optical device of the present invention.
  • an electronic apparatus there are mobile phones, mobile information terminals, watches, and information processing devices such as word processors and personal computer, etc.
  • the electro-optical device of the present invention into a display part of such electronic apparatuses, it is available to provide an electronic apparatus whose display performance is improved at low cost.
  • a EL display device which uses an organic EL material among electroluminescence type materials as an example of an electro-optical material.
  • Fig. 1 is a mimetic diagram illustrating an equivalent circuit and a wiring structure of an EL display device according to the present embodiment.
  • An EL display device (electro-optical device) 1 shown in Fig. 1 is an active matrix type EL display device using a thin film transistor (hereinafter, abbreviated as TFT) as a switching element.
  • TFT thin film transistor
  • the EL display device 1 comprises: a plurality of scanning lines 101; a plurality of signal lines 102 extending in the direction of perpendicularly intersecting each scanning line 101; and a plurality of power source lines 103 extending parallel to each signal line 102. Further, a pixel region A is arranged around each intersection between the scanning lines 101 and the signal lines 102.
  • a data line driving circuit 100 which comprises a shift register, a level shifter, a video line, and an analog switch, is connected to the signal lines 102.
  • a scanning-line driving circuit 80 which comprises a shift register and a level shifter, is connected to the scanning lines 101.
  • Each pixel region A is provided with a switching TFT (switching element) 112 where scanning signals are supplied to gate electrodes via the scanning lines 101; a storage capacitor (electrostatic capacitor) 113 for holding pixel signals shared from the signal lines 102 via the switching TFT 112; a driving TFT (switching element) 123 where the pixel signals held by the storage capacitor 113 are supplied to the gate electrodes; an anode (first electrode) 23 into which driving current flows from the power source lines 103 when electrically connected to the power source line 103 via the driving TFT 123; and a functional layer (light-emitting layer) 110 which is sandwiched between the anode 23 and a cathode (second electrode) 50.
  • the anodes 23, the cathode 50, and the functional layer 110 constitute a light-emitting element.
  • the EL display device 1 when the scanning line 101 is driven to turn on the switching TFT 112, potential of the signal line 102 is held by the storage capacitor 113 and an on/off state of the driving TFT 123 is determined in accordance with a state of the corresponding storage capacitor 113. Further, current flows into the anode 23 from the power source line 103 via a channel of the driving TFT 123, and then flows into the cathode 50 via the functional layer 110. The functional layer 110 emits light in accordance with the amount of the current flowing therethrough. Thus, since on/off operation of each anode 23 is controlled for the light emission, the anode 23 is composed of a pixel electrode.
  • Fig. 2 is a plan view mimetically illustrating a configuration of the EL display device 1.
  • Fig. 3 is a sectional view taken along the line A-B of Fig. 2.
  • Fig. 4 is a sectional view taken along the line C-D of Fig. 2.
  • the EL display device 1 of the present embodiment illustrated in Fig. 2 comprises: a substrate 20 having an electric insulating property; a pixel electrode region (not shown) where pixel electrodes connected to switching TFTs (not shown) are disposed in a matrix on the substrate 20; power source lines 103 ⁇ arranged around the pixel electrode region and connected to each pixel electrode; and a pixel part 3 (within a frame indicated by one-dotted chain line in the drawing) formed in a substantially rectangular shape in a plan view and located at least on the pixel electrode region.
  • the pixel part 3 is partitioned into a central substantial display region 4 (within a frame indicated by two-dotted chain line in the drawing) and a dummy region (region between the one-dotted chain line and the two-dotted chain line) 5 arranged around the substantial display region 4.
  • display regions (R, G, B) are disposed in a matrix so as to have a pixel electrode, respectively, and to correspond to three primary colors of red, green, and blue.
  • the display regions (R, G, B) are repeatedly arranged in a separated way.
  • C-D direction display regions corresponding to the same color are separately arranged.
  • scanning-line driving circuits 80 are disposed on both sides of the substantial display region 4 in the drawing.
  • the scanning-line driving circuits 80 are positioned under the dummy region 5.
  • an inspection circuit 90 is disposed at an upper part of the substantial display region 4 in the drawing.
  • the inspection circuit 90 is positioned under the dummy region 5.
  • the inspection circuit 90 inspects an operational state of the EL display device 1.
  • the inspection circuit has inspected result output means (not shown) for outputting an inspected result to the outside, and it is configured to be capable of inspecting the quality and defects of a display device during the manufacture or shipment thereof.
  • Driving voltages of the scanning-line driving circuits 80 and the inspection circuit 90 are applied via driving voltage continuity parts 310 (see Fig. 3) and driving voltage continuity parts 340 (see Fig. 4). Further, driving control signals and the driving voltages to the scanning-line driving circuits 80 and the inspection circuit 90 are transmitted and applied via driving control signal continuity parts 320 (see Fig. 3) and driving voltage continuity parts 350 (see Fig. 4) composed of predetermined main drivers for controlling an operation of the EL display device 1. In this case, the driving control signals are command signals from the main drivers related to the control when the scanning-line driving circuits 80 and the inspection circuit 90 output signals.
  • a substrate 20 and a sealing substrate 30 are adhered together via a sealing resin 40.
  • a drying agent 45 having light transmissivity is inserted into a region surrounded by the substrate 20, the sealing substrate 30, and the sealing resin 40.
  • inert gas filling layer 46 filled with inert gas such as nitrogen gas is formed in the region.
  • any kinds of plate-shaped members having insulation may be available as the substrate 20 only if they can form an electronic circuit by providing a silicon layer on the substrate 20. It is unnecessary for the members to have light transmissivity.
  • the sealing substrate 30 can adopt a plate-shaped member having light transmissivity and electric insulation, such as glass, quartz, or plastics.
  • the sealing resin 40 is composed of thermosetting resin or ultraviolet curable resin, and in particular, it is preferable that the sealing resin be composed of epoxy resin, which is a kind of thermosetting resin.
  • the substrate 20 has thereon formed a circuit part (circuit layer) 11 having a laminated structure including driving TFTs 123 for driving anodes 23.
  • Each of the anodes 23 connected to the driving TFTs 123 is formed on the circuit part 11 so as to correspond to positions of the display regions (R, G, B) of Fig. 2.
  • the functional layer 110 is formed on each anode 23 within a substantial display region 4.
  • a buffer layer 222 for facilitating electron injection and a cathode 50 for performing the electron injection are formed on each anode 23.
  • Banks 221 and an oval pixel display part 26 are formed between each anode 23.
  • An inorganic bank layer 221a and an organic bank layer 221b are laminated on the banks 221 from the substrate 20 to A-B direction and C-D direction in Fig. 2.
  • the oval pixel display part 26 partitions the functional layer 110, and regulates light emitted from the partitioned functional layer 110.
  • the inorganic bank layer 221a covers each dummy anode 23a, and the functional layer 110 is provided on an upper layer thereof.
  • the dummy anodes 23a are configured in the same way as the anodes 23, exception for being not connected to wiring of the circuit part 11.
  • the dummy region 5 By disposing the dummy region 5 around the substantial display region 4, it is possible to uniform the thickness of the functional layer 110 in the substantial display region 4, and to suppress display nonuniformity.
  • drying conditions of discharged compositions can be made regular within the substantial display region 4 in case that display elements are formed by an ink-jet method. Further, there is no problem that the deviation in the thickness of the functional layer 110 may occur at the peripheral edge of the substantial display region 4.
  • the circuit part 11 includes the scanning-line driving circuits 80, the inspection circuit 90, the driving voltage continuity parts 310, 340, 350 for driving the circuits by connecting them, and the driving control signal continuity parts 320.
  • the anodes 23 have a function to inject holes into the functional layer 110 by applied voltages.
  • the anodes 23 can adopt ITO (Indium Tin Oxide) and the like having excellent injection performance of the holes with an increased work function.
  • the functional layer 110 any configurations are available if only it has a light-emitting layer.
  • the functional layer can adopt a configuration comprising: a hole injection/transport layer 70 (see Fig. 5(b)) having a hole injection layer improving injection efficiency of the holes and a hole transport layer improving transport efficiency of the holes; and an organic EL layer 60 (light-emitting layer in Fig. 5b), sequentially from the anodes 23.
  • a hole injection/transport layer 70 see Fig. 5(b) having a hole injection layer improving injection efficiency of the holes and a hole transport layer improving transport efficiency of the holes
  • an organic EL layer 60 light-emitting layer in Fig. 5b
  • poly-thiophene derivatives for example, poly-thiophene derivatives, polypyrrole derivatives, or doping materials can be adopted.
  • poly-thiophene derivatives PEDOT:PSS in which PEDOT is doped with PSS (Polystyrene sulfone acid) can be adopted.
  • PSS Polystyrene sulfone acid
  • a kind of the PEDOT:PSS, bytron-p (made by Bayer AG) can be properly used.
  • any known materials for hole transport may be possible if only they can transport the holes.
  • various organic materials classified into amine, hydrazone, stilbene, and starburst series are known as such materials.
  • any known light-emitting materials capable of emitting fluorescence or phosphorescence are available. More specifically, there are proper materials such as poly-fluorene derivatives (PF), poly-paraphenylenevinylene derivatives (PPV), polyphenylene derivatives (PP), polyparaphenylene derivatives (PPP), polyvinyl carbazole (PVK), poly-thiophene derivatives, and polysilane series such as polymethyl phenylsilane (PMPS).
  • PF poly-fluorene derivatives
  • PV poly-paraphenylenevinylene derivatives
  • PP polyphenylene derivatives
  • PPP polyparaphenylene derivatives
  • PVK polyvinyl carbazole
  • PMPS poly-thiophene derivatives
  • polysilane series such as polymethyl phenylsilane (PMPS).
  • high polymer materials with high polymer series material such as perylene series pigment, coumarin series pigment, and rhodamine series pigment, or materials such as rubrene, perylene, 9, 10-diphenylanthracene, tetraphenylbutadiene, Nile red, coumarin 6, and quinacridon.
  • high polymer series material such as perylene series pigment, coumarin series pigment, and rhodamine series pigment, or materials such as rubrene, perylene, 9, 10-diphenylanthracene, tetraphenylbutadiene, Nile red, coumarin 6, and quinacridon.
  • both the inorganic bank layer 221a and the organic bank layer 221b forming the bank 221 are formed to bulge at the peripheral edge of the anode 23.
  • the inorganic bank layer 221a is formed to extend more toward the central side than the anode 23, compared to the organic bank layer 221b.
  • the bank 221 may be configured with materials not to transmit light or it may be configured to regulate the light by disposing a light-shielding layer between the inorganic bank layer 221a and the organic bank layer 221b.
  • the inorganic bank layer 221a can adopt inorganic materials such as SiO 2 , TiO 2 , and SiN. It is preferable to form the film thickness of the inorganic bank layer 221a within the range of 50 to 200 nm, and particularly, approximately 150 nm is the best. When the film thickness is less than 50 nm, the inorganic bank layer 221a can be thinner than the hole injection/transport layer 70, thus it cannot secure flatness of the hole injection/transport layer 70. If the film thickness exceeds 200 nm, step difference by the inorganic bank layer 221a get bigger, thus it is impossible to obtain flatness of the organic EL layer 60.
  • the organic bank layer 221b is formed of common resist such as acryl resin and polyimide resin. It is preferable to form the thickness of the organic bank layer 221b within the range of 0.1 to 3.5 ⁇ m, and particularly, approximately 2 ⁇ m is the best. If the thickness is less than 0.1 ⁇ m, it is not preferable since the thickness of the organic bank layer 221b is thinner than that of the functional layer 110.
  • the thickness of the organic bank layer 221b is more than 2 ⁇ m, it is more preferable due to the fact that insulation between the anode 23 and the cathode 50 can be increased.
  • the functional layer 110 is formed to be thinner than the bank 221.
  • a region showing a lyophilic property and a region showing a lyophobic property are formed around the bank 221.
  • the inorganic bank layer 221a and the anode 23 are the region showing a lyophilic property, and this region introduces a lyophilic group such as a hydroxyl group by a plasma treatment using oxygen as a reaction gas. Further, the organic bank layer 221b is the region showing a lyophobic property, and a lyophobic group such as fluorine is introduced by a plasma treatment using 4-fluoromethane as a reaction gas.
  • the lyophilic property of a lyophilic control layer means high lyophilic properties, compared to acryl and polyimide materials constituting at least the organic bank layer 221b.
  • the cathode 50 has a larger area than the total area of the substantial display region 4 and the dummy region 5, and the cathode is formed in such a manner to cover them.
  • the cathode 50 has a function to inject electrons into the functional layer 110 as an electrode opposite to the anode 23. Further, in the present embodiment, the light emitted from the functional layer 110 is taken out from the cathode 50, so that the cathode is required to have light transmissivity. Therefore, the cathode 50 is made of materials having low work functions as well as having light transmissivity.
  • laminations can be adopted in which a first cathode layer is formed by providing laminations of, for example, lithium fluoride and calcium on the functional layer 110, and a second cathode layer composed of laminations of, for example, Al, Ag, Mg/Ag, etc is formed on the first cathode layer.
  • a first cathode layer is formed by providing laminations of, for example, lithium fluoride and calcium on the functional layer 110
  • a second cathode layer composed of laminations of, for example, Al, Ag, Mg/Ag, etc is formed on the first cathode layer.
  • light transmissivity can be obtained by making each layer thickness thinner until they have light transmissivity.
  • the cathode 50 only the second cathode layer extends up to the outside of the pixel part 3.
  • the second cathode layer is provided for covering the first cathode layer to protect it from chemical reactions with oxygen or water, and for increasing the conductivity of the cathode 50. Accordingly, if it is chemically stable with a low work function and light transmissivity, it may be a single layer structure and it is not necessarily limited to metal materials. Furthermore, a protective layer made of SiO 2 and SiN for preventing oxidation may be provided on the second cathode layer.
  • Fig. 5(a) is a mimetic diagram seen from a plane of four adjacent pixel regions A in the substantial display region 4.
  • Fig. 5(b) is a sectional view seen from the direction E-F in Fig. 5(a).
  • Fig. 6(a) is an enlarged view around a switching TFT 112 and a driving TFT 123 in Fig. 5(a).
  • Fig. 6(b) is a sectional view taken along the line G-H of Fig. 6(a).
  • each pixel region A has the same laminated structure even though a material of functional layers 110 is different, according to any one of display regions (R, G, B).
  • one pixel region A will be described below on behalf of the rest pixel regions. Furthermore, since all the arrangements seen from the plane of the four pixel regions A are identical to each other, reference numerals will be omitted to the parts as considered to be clearly identical in order to more easily refer to the drawing.
  • the power source line (metal part) 103 is provided in the pixel region A so as to extend in the direction of intersecting the scanning line 101, under the anode 23 with the width of covering at least an area of the pixel display part 26.
  • the signal line 102 is provided substantially parallel to the power source line 103.
  • the switching TFT 112 is connected to a source electrode wiring line 102a, which is configured to extend as a portion of the signal line 102.
  • a gate electrode 242 of the driving TFT 123 is connected to a drain electrode of the switching TFT 112 through a connection wiring line 18.
  • a gate electrode 252 of the switching TFT 112 is connected to the scanning line 101.
  • the power source line 103 is connected to a source electrode of the driving TFT 123 through a power source wiring line 103b, which is configured as a portion of the power source line 103.
  • the anode 23 is connected to a drain electrode of the driving TFT 123.
  • Both the switching TFT 112 and the driving TFT 123 are disposed under the bank 221 at a position sandwiched between the signal line 102 and the pixel display part 26.
  • the storage capacitor 113 (see Fig. 1) is formed under the pixel display part 26 which will be described later.
  • a silicon layer 261 is formed on the surface of the substrate 20, based on a base protective layer 281 mainly composed of SiO 2 .
  • the silicon layer 261 is formed in an island shape with a larger area than that of the pixel display part 26 at a position overlapping the pixel display part 26 seen from the plane.
  • Island-shaped silicon layers 241, 251 are formed on the same layer as the silicon layer 261 for forming the driving TFT 123 and the switching TFT 112.
  • the surface of each silicon layer 261, 241, 251 is covered with a gate-insulating layer 282 mainly composed of SiO 2 and/or SiN.
  • the "main" component indicates a component including the biggest content among the components.
  • a first metal layer composed of, for example, an aluminum film, a chrome film, a tantalum film, etc. is provided on the gate-insulating layer 282.
  • the first metal layer forms the gate electrodes 242, 252, the scanning line 101, and a condenser electrode 150.
  • the condenser electrode 150 is formed on the silicon layer 261 so as to oppose the silicon layer 261 with an area equal to that of the silicon layer 261 or a slightly smaller area than that thereof.
  • the top of the first metal layer is covered with a first interlayer insulating layer 283 mainly composed of SiO 2 .
  • the power source line 103 and the signal line 102 are formed from a second metal layer composed of, for example, an aluminum film, a chrome film, a tantalum film, etc.
  • the power source line 103 is formed with the thickness having optical reflexibility. Further, the power source line is connected to the silicon layer 261 by a contact hole 103a which is bored in the gate-insulating layer 282 through the first interlayer insulating layer 283, and the power source line is of the same potential as the silicon layer. Accordingly, the power source line 103 and the condenser electrode 150 are configured to oppose each other with the first interlayer insulating layer 283 as an insulating material sandwiched therebetween so as to form an electrostatic capacitor, and the condenser electrode 150 and the silicon layer 261 are configured to oppose each other with the gate-insulating layer 282 as an insulating material sandwiched therebetween so as to form an electrostatic capacitor.
  • the storage capacitor 113 forms the storage capacitor 113 (see Fig. 1). More specifically, in the circuit part 11, the storage capacitor 113 is formed on a layer below the power source lines 103 for reflecting light, below the pixel display part 26. Further all of the power source line 103, the condenser electrode 150, and the silicon layer 261 for forming the storage capacitor 113 are formed in a flat beta-shaped pattern having a predetermined thickness within the range of area of covering at least the pixel display part 26.
  • the top of the second metal layer is covered with the second interlayer insulating layer 284 mainly composed of acryl-series resin components.
  • the second interlayer insulating layer 284 can use any materials other than an acryl-series insulating film, for example, SiN, SiO 2 , etc.
  • Fig. 6(a) is an enlarged view around the switching TFT 112 and the driving TFT 123.
  • Fig. 6(b) is a sectional view taken along the line G-H of Fig. 6(a).
  • the silicon layer 251 is provided with a source region 251S, a channel region 251a, and a drain region 251D. Moreover, the source region 251S and the drain region 251D have a gradient of concentration, so called a light doped structure (LDD).
  • the source region 251S is connected to the source electrode wiring line 102a via a contact hole 19a which is bored in gate-insulating layer 282 through a first interlayer insulating layer 283.
  • the drain region 251D is connected to the connection wiring line 18 which is formed from the second metal layer via a contact hole 19b which is bored in the gate-insulating layer 282 through the first interlayer insulating layer 283, and the drain region is connected to the gate electrode 242 via a contact hole 19c which is bored in the first interlayer insulating layer 283 through the gate-insulating layer 282 from the connection wiring line 18.
  • the channel region 251a is provided on its upper layer with a gate electrode 252 with the gate-insulating layer 282 being sandwiched therebetween.
  • the switching TFT 112 is formed according to the above configuration.
  • the silicon layer 241 is provided with a source region 241S, a channel region 241a, and a drain region 241D. Moreover, the source region 241S and the drain region 241D have a gradient of concentration, so-called a LDD structure.
  • the source region 241S is connected to the power source wiring line 103a via a contact hole 19d which is bored in the gate-insulating layer 282 through the first interlayer insulating layer 283.
  • the drain region 241D is connected to the connection wiring line 18 which is formed from the second metal layer via a contact hole 19e which is bored in the gate-insulating layer 282 through the first interlayer insulating layer 283, and the drain region is connected to the anode 23 via a contact hole 19f which is bored in the second interlayer insulating layer 284 through the inorganic bank layer 221a.
  • the channel region 241a is provided on its upper layer with the gate electrode 242 with the gate-insulating layer 282 being sandwiched therebetween.
  • the driving TFT 123 is formed according to the above configuration.
  • the circuit part 11 is configured by the layers from the substrate 20 to the second interlayer insulating layer 284, which have been described above.
  • circuit part 11 in order to form the signal lines 102 and the power source lines 103 of intersecting the scanning lines 101 or to form the TFTs, two metal layers arranged on the different layers and having insulation are formed.
  • FIG. 7(a) to Fig. 7(d) corresponds to a sectional view taken along the line E-F in Fig. 5, and is shown in sequence of the respective manufacturing processes. Further, the following description will be made mainly about a process particularly related to the present invention, that is, a process of forming the circuit part 11.
  • the base protective layer 281 made of a silicon oxide film, etc. is formed on the substrate 20.
  • crystal grains are caused to grow up by a laser annealing method or a rapid heating method to form a poly silicon layer.
  • the poly silicon layer is patterned through a photolithographic method to form the island-shaped silicon layers 241, 251, 261.
  • the gate-insulating layer 282 made of a silicon oxide film is formed.
  • the formation of the gate-insulating layer 282 is carried out by forming a silicon oxide film with a thickness of approximately 30 nm to 200 nm, which covers each silicon layer 241, 251 (both of them are not shown), and 261 and the base protective layer 281, using the plasma CVD method, a heat oxidizing method, etc.
  • the crystallization of the silicon layers 241, 251 is also carried out, so that it is possible to form the silicon layers as poly silicon layers. Further, impurity ions such as boron ions are implanted at this timing to perform a channel doping.
  • an ion injection/selection mask is formed in a portion of the silicon layers 241, 251.
  • impurity ions such as phosphorus ions are injected.
  • high concentration impurities are introduced into the ion injection/selection mask in a self-alignment manner, and a high concentration source and drain regions are formed in the silicon layers 241, 251.
  • the first metal layer is formed on the gate-insulating layer 282 with a thickness of approximately 500 nm. Further, the metal layer is patterned to form the scanning lines 101, gate electrodes 242, 252, a condenser electrode 150, etc. simultaneously.
  • the gate electrodes 242, 252 are used as masks, and impurity ions such as low concentration phosphorus ions are injected into the silicon layers 241, 251. As a result, low concentration impurities are introduced into the gate electrodes 242, 252 in self-alignment manner, and a low concentration source and drain regions are formed in the silicon layers 241, 251.
  • the second interlayer insulating layer 283 is formed on the entire surface of the substrate 20. Further, the second interlayer insulating layer 283 is patterned by the photolithographic method, the contact holes 103a are provided. At this time, though not shown in the drawing, the contact holes 19a, 19b, 19c, 19d, 19e are simultaneously formed.
  • the second metal layer with a thickness of approximately 200 nm to 80 nm made of metals such as aluminum, chrome, and tantalum is formed in such a manner to cover the contact holes 103a, 19a, 19b, 19c, 19d, 19e with the metals of the second metal layer.
  • a patterning mask is formed on the second metal layer. Then, the second metal layer is patterned by the patterning mask, and power source lines 103, signal lines 102 and connection wiring lines 18 are formed.
  • the first interlayer insulating layer 284 covering the second interlayer insulating layer 283 is formed from an acryl-series resin material. It is preferable that the first interlayer insulating layer 284 is formed with a thickness of approximately 1 to 2 ⁇ m.
  • the contact holes 19f are formed by removing a part of the connection wiring lines 18 corresponding to the drain regions 241D of the driving TFTs 123 through an etching process. As a result, the circuit part 11 is formed on the substrate 20.
  • a thin film composed of a transparent electrode material such as ITO is formed in such a manner to cover the entire surface of the circuit part 11. Then, the thin film is patterned to bury holes provided on the first interlayer insulating layer 284 to form the contact holes 19f. Further, the anodes 23 and the dummy electrodes 23a are formed. The anodes 23 are formed only at portions where the driving TFTs 123 are formed, and the anodes are connected to the driving TFTs 123 via the contact holes 19f. The dummy electrodes 23a are arranged in an island shape.
  • the inorganic bank layers 221a are formed on the first interlayer insulating layer 284, the anodes 23, and the dummy electrodes 23a.
  • the inorganic bank layers 221a are formed such that a portion of the anodes 23 opens on the anodes 23, and the dummy electrodes 23a are fully covered on the dummy electrodes 23a.
  • the inorganic bank layers 221a are formed by patterning the inorganic films.
  • the organic bank layers 221b are formed on the inorganic bank layers 221a.
  • the organic bank layers 221b are formed such that the pixel display parts 26 open with a predetermined size on all the anodes 23 and the dummy electrodes 23a.
  • the inorganic bank layer 221a and the organic bank layer 221b form the bank 221.
  • the respective regions are formed by a plasma treatment process. More specifically, the plasma treatment process comprises at least a lyophilic process of making the anode 23 and the inorganic bank layer 221a have a lyophilic property, and a lyophobic process of making the organic bank layer 221b have a lyophilic property.
  • the banks 112 are heated up to a predetermined degree of temperature (for instance, approximately 70 to 80°C).
  • a plasma treatment O 2 plasma treatment
  • oxygen as a reaction gas in the atmosphere
  • a plasma treatment using 4-fluoro methane as a reaction gas (CF 4 plasma treatment) in the atmosphere is performed.
  • the functional layers 110 are formed on the anodes 23, and the inorganic bank layers 221a on the dummy electrodes 23a, respectively, by an ink-jet method.
  • the functional layers 110 are formed by discharging and drying the composition ink including light-emitting layer materials constituting the organic EL layers 60.
  • the inert gas atmosphere such as nitrogen and argon atmosphere in order to prevent the hole injection/transport layers 70 and the organic EL layers 60 from being oxidized.
  • the cathode 50 for covering the banks 112 and the functional layers 110 are formed.
  • the first cathode layer is covered to form a second cathode layer to be connected to a cathode wiring line (not shown) on the substrate 20.
  • sealing resin 40 such as epoxy resin to the substrate 20 is applied to bond the sealing substrate 30 to the substrate 20 via the sealing resin 40.
  • the power source lines 103 formed from the second metal layer are located below the anodes 23 at the positions overlapping the pixel display parts 26, the light emitted downwardly from the organic EL layers 60 and transmitted through the transparent anodes 23 can be reflected upwardly by the power source lines 103, and the emitted light can be efficiently emitted to the cathode 50.
  • such reflecting surface uses the second metal layer necessary for forming the circuit part 11 and is also used as the power source lines 103.
  • the transparent electrode having excellent electrode properties are used.
  • the power source lines 103 disposed under the pixel display parts 26 can be formed by overlapping a flat beta-shaped pattern from the substrate 20. Accordingly, it is possible to form a reflecting surface having excellent flatness. As a result, the use efficiency of light can be improved without reflection nonuniformity and the display quality can be improved.
  • a storage capacitor 113 is provided in any layer under power source lines 103 by using the flat beta-shaped pattern, the storage capacitor 113 can be formed in a lower region of the wide pixel display part 26, and the space can be efficiently used to magnify the storage capacitor 113. As a result, the holding property of display can be improved and excellent display can be stably performed.
  • the electric resistance can be lowered and the energy-economizing type device can be obtained.
  • a reflecting surface is configured by a second metal layer located nearer to the anodes 23 and located relatively higher than the circuit part 11, a transmitting optical path of the reflected light can be relatively shortened, the optical loss can be reduced, and the height of a space under the reflecting surface can be relatively elevated.
  • Fig. 8 is a plan view mimetically illustrating a configuration of the EL display device 1 according to the present modified example.
  • the EL display device shown in Fig. 8 is different from the device shown in Fig. 2 only in that the substantial display region 4 is substituted with a substantial display region 400.
  • members similar to those in the first embodiment are given similar reference numerals, and the description thereof will be omitted.
  • the present modified example will be described mainly about different parts.
  • the modified example is different from the first embodiment in that the display regions (R, G, B) are respectively arranged to continue vertically in the substantial display region 4 (see Fig. 2), whereas they are configured to continue horizontally in the substantial display region 400. For this reason, four consecutive pixel regions A are configured as shown in Fig. 9.
  • Fig. 9(a) is a mimetic diagram seen from a plane of four adjacent pixel regions A on the substantial display region 400.
  • Fig. 9(b) is a sectional view taken along the direction I-J of Fig. 9(a).
  • Fig. 9 is greatly different from Fig. 5 in that power source lines 103 are provided substantially parallel to the signal lines 102 in Fig. 5, whereas power source lines 103 intersect the signal lines 102 and extend substantially parallel to scanning lines 101 in Fig. 9. Since an organic EL layer 60 is different for every color and driving voltages are also different for each display region (R, G, B), the power source lines 103 extend in the direction of the display regions having the same color.
  • the power source lines 103 are formed on a second metal layer. The others have the substantially same layer structure. However, in the present modified example, since it is necessary to make the signal lines 102 intersect the power source lines 103, the signal lines 102 are formed from a first metal layer at a position of intersecting the power source lines 103.
  • connection wiring 102b is formed from the second metal layer at a position where the signal lines 102 intersect the scanning lines 101 formed from the first metal layer. For this reason, it is configured that contact holes 102c, 102c bored in a first interlayer insulating layer 283 are provided around the scanning lines 101, and are connected with the signal lines 102, respectively, thereby detouring the scanning lines 101 of the same layer as the signal lines 102.
  • Such configuration can be easily obtained by changing a patterning when etching the first metal layer and the second metal layer.
  • the switching TFTs 112 and the driving TFTs 123 are disposed between the scanning lines 101 and the power source lines 103.
  • the silicon layers 261 and the condenser electrodes 150 are laminated in a beta-shaped pattern below the pixel display part 26 and the power source lines 103.
  • the power source lines 103 and the silicon layer 261 have the same potential by the contact holes 103a.
  • a configuration of a storage capacitor 113 is the same as that of Fig. 5.
  • the power source lines 103 do not intersect the scanning lines 101, though they have the same effects as the above, electrostatic capacitor formed between the power source lines 103 gets smaller, thereby quickly performing a switching operation.
  • switching elements are provided between the scanning lines 101 and the power source lines 103, a more compact insertion is enabled by locating the switching TFT 112 and the driving TFT 123. in parallel to the lateral direction of the pixel display part 26.
  • the TFTs 112, 123 are arranged to a long direction of the pixel display part 26, thereby reducing a space.
  • an opening ratio can be remarkably improved by making the pitch in the lateral direction of the pixel display part 26 narrow.
  • reflection nonuniformity can be permitted to some extent.
  • a lower part of the power source lines 103 has deteriorated flatness without a flat beta-shaped pattern.
  • an EL display device 1 as a second embodiment of an electro-optical device of the present invention Similar to the first embodiment, a reflecting surface is provided on a second metal layer according to the second embodiment. However, it is different from the first embodiment because the power source lines 103 are configured on a first metal layer. Besides, the second embodiment has the same configuration as that of the first embodiment. Hereinafter, descriptions about the same parts will be omitted by attaching the same reference numerals.
  • the EL display device 1 of the present embodiment is a device of type as shown in Fig. 8. Because of this, similar to the modified example of the first embodiment, the power source lines 103 are substantially parallel to the scanning lines 101 and are provided in the direction of intersecting the signal lines 102.
  • Fig. 10(a) is a mimetic diagram seen from a plane of four adjacent pixel regions A in the substantial display region 400 of the EL display device 1 according to the present embodiment.
  • Fig. 10(b) is a sectional view taken along the direction K-L in Fig. 10(a).
  • Each power source line 103 has a width to cover the total area of a pixel display part 26 by using a first metal layer, on a gate-insulating layer 282, and is consecutively provided substantially parallel to the scanning line 101 formed from the same first metal layer.
  • a first interlayer insulating layer 283 is provided thereupon.
  • a reflective part (metal part, 151), signal lines 102, and a connection wiring line 18 are formed thereupon, as covering each area of the pixel display part 26 by a second metal layer.
  • Anodes 23 are provided on the reflective part 151. Seen from the plane, a switching TFT 112 and a driving TFT 123 are formed between the scanning lines 101 and the power source lines 103.
  • a storage capacitor 113 is formed in a lower part of the reflective part 151 by a silicon layer 261 and the power source lines 103 with a gate-insulating layer 282 being sandwiched therebetween.
  • Fig. 11 (a) is an enlarged view around the switching TFT 112 and the driving TFT 123 of Fig. 10(a).
  • Fig. 11(b) is a sectional view taken along the line M-N of Fig. 11(a).
  • the switching TFT 112 has a source region 251S, a channel region 251a, and a drain region 251D.
  • the source region 251S is connected to a source electrode wiring line 102a extending from the signal line 102 by a contact hole 19a.
  • a gate-insulating layer 282 and a gate electrode 252 extended to form a portion of scanning line 101 are provided on the channel region 251a.
  • the drain region 251D is connected to a gate electrode 242 provided by a first metal layer.
  • the driving TFT 123 has a source region 241S, a channel region 241a, and a drain region 241D.
  • the source region 241S is connected to a contact hole 19i, which is bored from a gate-insulating layer 282 to a first interlayer insulating layer 283.
  • the contact hole 19i is connected to a connection wiring line 18.
  • the connection wiring line 18 is connected to the power source line 103 by a contact hole 19j which is bored from the first interlayer insulating layer 283 to the gate-insulating layer 282.
  • the gate-insulating layer 282 and a gate electrode 242 are provided on the channel region 241a.
  • the gate electrode 242 is connected to a silicon layer 261.
  • the drain region 241D is connected to a reflective part wiring line 151a extending from a reflective part 151 by a contact hole 19h, which is bored in the first interlayer insulating layer 283 from the gate-insulating layer 282.
  • the driving TFT 123 is formed. Since anodes 23 are provided on the reflective part 151, the drain region 241D is electrically connected to the anode 23.
  • FIG. 12(a) to Fig. 12(d) corresponds to the sectional view taken along the line K-L of Fig. 10, and shows each manufacturing process.
  • a process particularly related to the present invention that is, a process of forming a circuit part 11 will be described, and the description about parts common to the first embodiment will be omitted.
  • a base protective layer 281 is formed on a substrate 20.
  • silicon layers 241, 251, 261 are formed.
  • a gate-insulating layer 282 is formed.
  • a method of forming a source region and a drain region having the gradient of concentration on the silicon layers 241, 251, respectively, is performed similar to the first embodiment.
  • a first metal layer with a thickness of approximately 500 nm is formed on the gate-insulating layer 282.
  • the metal layer is patterned to form scanning lines 101, gate electrodes 242, 252, and power source lines 103 simultaneously (a first metal layer formation process).
  • a second interlayer insulating layer 283 is formed on an entire surface of a substrate 20, and the second interlayer insulating layer 283 is patterned to form contact holes 19a, 19h, 19i, 19j (not shown).
  • a second metal layer is formed in such a manner to cover the second interlayer insulating layer 283, thereby filling the previously formed contact holes 19a, 19h, 19i, 19j with metals of the second metal layer.
  • a patterning mask is formed on the second metal layer. The second metal layer is patterned by the patterning mask. As a result, and reflective parts 151, signal lines 102, and connection wiring lines 18 are formed (a second metal layer formation process).
  • anodes 23 are formed on the reflective parts 151. So, a circuit part 11 is formed on a substrate 20.
  • a process of forming a hole injection/transport layer 70, an organic EL layer 60, and the cathode 50 on the circuit part 11 as well as a process of bonding a sealing substrate 30 to the substrate 20 is the same as the first embodiment, thereby omitting the description.
  • the EL display device 1 according to the second embodiment of the present invention is obtained.
  • the EL display device 1 related to the present embodiment since a reflective part 151 formed on a second metal layer is arranged under an anode 23 at a position overlapping a pixel display part 26, the light emitted downwardly from an organic EL layer 60 and transmitted through the transparent anode 230 can be reflected upwardly by the reflective part 151, and the emitted light can be efficiently emitted to cathode 50.
  • such reflective part 151 uses a second metal layer essential for forming a circuit part 11. For this reason, it is unnecessary to separately provide a reflective film as a base layer to a transparent electrode, although the transparent electrode having excellent electrode properties is used, and to reduce materials and processes, thereby forming at a low price by suppressing the manufacturing cost.
  • a second interlayer insulating layer 284 for insulating the second metal layer from the anode 23 may not be provided, the manufacturing cost can be suppressed and the manufacturing cost can be simplified.
  • the reflective part 151 disposed under the pixel display part 26 can be formed by overlapping a flat beta-shaped pattern from the substrate 20. Accordingly, a reflecting surface having excellent flatness can be formed. As a result, the use efficiency of light can be improved without reflection nonuniformity and the display quality can be improved.
  • a storage capacitor 113 is provided in any layer under power source lines 103 by using the flat beta-shaped pattern, the storage capacitor 113 can be formed in a lower region of the wide pixel display part 26, and the space can be efficiently used to magnify the storage capacitor 113. As a result, the holding property of display can be improved and excellent display can be stably performed.
  • the electric resistance can be lowered and the energy-economizing type device can be obtained.
  • a reflecting surface is configured by a second metal layer located nearer to the anodes 23 and located relatively higher than the circuit part 11, a transmitting optical path of the reflected light can be relatively shortened, the optical loss can be reduced, and the height of a space under the reflecting surface can be relatively elevated.
  • the electrostatic capacitor formed between the power source lines 103 gets smaller and a switching operation is quickly performed.
  • switching elements are provided between the scanning lines 101 and the power source lines 103, a more compact insertion can be made by making a switching TFT 112 and a driving TFT 123 parallel to the lateral direction of the pixel display part 26.
  • the pitch in the lateral direction of the pixel display part 26 can be made narrow.
  • the reflective part 151 does not have to continue to a metal part located under the pixel display part 26 including the power source lines 103.
  • a luminous amount around a unit surface area of an organic EL layer 60 may be smaller, thereby improving an element life span.
  • Fig. 13 is an enlarged view mimetically illustrating a configuration of a substantial display region of an EL display device 1 according to the present modified example.
  • the present modified example is a device of type as shown in Fig. 2, and it is different from the abovementioned embodiments only in that the substantial display region 4 is substituted with a substantial display region 400.
  • members similar to those in the above embodiments are given similar reference numerals, the description thereof will be omitted, and the present modified example will be described mainly about different parts.
  • the display regions (R, G, B) are respectively arranged to continue vertically in the substantial display region 4, whereas they are configured to continue horizontally in the substantial display region 400 (see Fig. 8). For this reason, four consecutive pixel regions A are configured as shown in Fig. 13.
  • Fig. 13(a) is a mimetic diagram seen from a plane of four adjacent pixel regions A on the substantial display region 400.
  • Fig. 13(b) is a sectional view taken along the direction P-Q in Fig. 13(a).
  • Fig. 13 is greatly different from Fig. 10 in that the power source lines 103 are provided substantially parallel to the scanning lines 101 in Fig. 10, whereas power source lines 103 intersect scanning lines 101 and extend substantially parallel to signal lines 102 in Fig. 13. They are similar to each other in that the power source lines 103 are formed on a first metal layer, and a reflective part 151 is formed on a second metal layer. The others have substantially the same layer structure. However, in the present modified example, since the signal lines 102 intersect the scanning lines 101, the scanning lines 102 are formed from a first metal layer at a position of intersecting the signal lines 102.
  • contact holes 101a, 101a bored in a first interlayer insulating layer 283 are provided around the signal lines 102 and are connected to the scanning lines 101, respectively, thereby detouring the signal lines 102 of the same layer as the scanning lines 101.
  • Such configuration can be easily obtained by changing a patterning when etching the first metal layer and the second metal layer.
  • an insulating layer is not provided between the second metal layer and the anode 23
  • the reflecting surface can be configured without increasing the number of manufacturing processes even in such configuration, the manufacturing cost can be suppressed.
  • the first and the second embodiments have been described by way of an example in which, since an ink-jet method is used to form an organic EL layer 60, etc., the banks 221 have a two-layered structure including an inorganic bank layer 221a and an organic bank layer 221b so that lyophilic and lyophobic property can be easily given the banks 221.
  • the banks may be a single-layered structure.
  • it is cheaper to manufacture the banks 221 having a single-layered structure.
  • first and the second embodiments have been described by way of an example in which two transistors form a switching element, it is needless to say that a circuit using four or more transistors may be configured.
  • Fig. 14(a) is a perspective view illustrating an example of a mobile phone.
  • a reference numeral 1000 denotes a mobile phone main body
  • a reference numeral 1001 denotes a display part using the aforementioned EL display device.
  • Fig. 14(b) is a perspective view illustrating an example of a wristwatch-type electronic apparatus.
  • a reference numeral 1100 denotes a watch main body
  • a reference numeral 1101 denotes a display part using the aforementioned EL display device.
  • Fig. 14(c) is a perspective view illustrating an example of a portable information-processing device such as a word processor and a personal computer.
  • a reference numeral 1200 denotes an information-processing device
  • a reference numeral 1202 denotes an input unit such as a keyboard
  • a reference numeral 1206 denotes a display part using the aforementioned EL display device
  • a reference numeral 1204 denotes an information-processing device main body.
  • the respective electronic apparatus shown in Fig. 14(a) to Fig. 14(c) comprise a display part using an EL display device of the first, the second or the third embodiment, and has the characteristics of an EL display device of the first or the second embodiment. Therefore, electronic apparatuses whose display property and reliability are improved, and whose manufacturing cost is reduced, are obtained.
  • the electronic apparatuses are manufactured by assembling the EL display device 1 of the first or the second embodiment into the display parts of various electronic apparatuses such as mobile phones, portable information-processing devices, and wristwatch-type electronic apparatuses.
  • a circuit layer comprises metal parts, so that it is possible to reflect the light transmitted through a first electrode, to a second electrode.
  • a circuit layer comprises metal parts, so that it is possible to reflect the light transmitted through a first electrode, to a second electrode.
  • the electro-optical device of the present invention since it is unnecessary to transmit the light through a lower part of the metal part, it is possible to efficiently use the space thereof. For instance, the display performance can be improved by configuring a large capacity of storage capacitor.
  • an electro-optical device since a metal part for reflecting light is formed from a metal part necessary for forming a circuit layer, it is possible to manufacture an electro-optical device having the metal part for reflecting light without increasing the number of manufacturing processes.
  • an electronic apparatus of the present invention since it comprises an electro-optical device according to the present invention, an electronic apparatus having the same effect as the electro-optical device according to the present invention can be obtained.

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EP03253429A 2002-05-31 2003-05-30 Dispositif electro-optique, méthode de fabrication et appareil électrique Withdrawn EP1367647A3 (fr)

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US8212474B2 (en) 2004-01-08 2012-07-03 Samsung Electronics Co., Ltd. Display device, and method of manufacturing the display device
EP2270867A3 (fr) * 2005-11-30 2012-09-19 Seiko Epson Corporation Dispositif électroluminescent et appareil électronique
EP2228827A3 (fr) * 2009-03-13 2012-11-28 Sony Corporation Unité d'affichage
US8772789B2 (en) 2005-11-30 2014-07-08 Seiko Epson Corporation Light-emitting device and electronic apparatus
EP3531455A3 (fr) * 2017-12-28 2019-10-23 LG Display Co., Ltd. Afficheur électroluminescent

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JP2004006137A (ja) 2004-01-08
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TW200408298A (en) 2004-05-16
US20070069997A1 (en) 2007-03-29
TWI265748B (en) 2006-11-01
CN101017844A (zh) 2007-08-15
CN101017845A (zh) 2007-08-15
JP4123832B2 (ja) 2008-07-23
CN100576561C (zh) 2009-12-30
US20040070808A1 (en) 2004-04-15
US7158103B2 (en) 2007-01-02
CN1463172A (zh) 2003-12-24
US20120026149A1 (en) 2012-02-02
KR100530439B1 (ko) 2005-11-23

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