Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
  • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
  • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

• the present invention relates to the production of video screens characterized by a fully digital display device and finding a non-limiting application in the production of computer and television video screens of small thickness and large display area in a single holding and can be planar, cylindrical or spherical.
• CRT type video display devices liquid crystals, plasma, plasma controlled by liquid crystals, light emitting diodes, micro-mirror modules, field effect etc. use electronic circuits which transform digital signals either into analog signals or into frequency modulated signals making it possible to globally vary the emissive intensity of the red green and blue sub pixels, grouped in triplets or pixels, which constitute the video screen.
• These screens constituting the mosaic can be of CRT type, diode panels, overhead projectors, video or liquid crystal, micro mirrors etc.
• These giant screens are several tens of inches thick and large consumers of energy. In fact, it is the limits of the techniques specific to these different types of screens which impose this mosaic mounting as soon as one wants display dimensions greater than what they allow to obtain in a single piece. In general, the limitations of each of these technologies mean that it is not possible to make video screens more than 20 inches diagonal in one piece for LCD screens, 42 inches for CRT screens and plasma screens .
• the object of the present invention is therefore to present a new device produced in the form of an integrated circuit making it possible to make video screens having five main characteristics: firstly they have an entirely digital display device of very small thickness similar to that obtained with LCDs, secondly their refresh rate is very high and independent of the resolution, the frequency of change and the display size of the images, thirdly each displayed image appears at once without scanning the pixels nor matrix addressing of these, fourthly these video screens are always of thin thickness and of display surface in a single piece even for dimensions greater than 42 inches diagonal called giant screens, fifthly these thin screens can have a display surface of all possible shapes, flat, cylindrical and even e spherical.
• Figure 1 shows the block diagram of an elementary light unit with numerical control.
• Figures 2 shows the operating diagram of this elementary light unit with digital control.
• Figure 3 shows a set of elementary light units with digital control and connected to each other according to a preferred embodiment of the present invention.
• Figure 4 shows the addressing table of this set of elementary light units with digital control and connected together according to a preferred embodiment of the present invention.
• Figures 5 and 6 show the equivalent electronic diagram and operating diagrams of an elementary light unit with digital control according to a preferred embodiment of the present invention.
• Figures 7 shows the diagram of an elementary light unit with its digital control device.
• Figure 8 shows the equivalent diagram of the electronic circuit of an elementary light unit with its digital control device
• Figure 9 shows the schematic section of a preferred physical embodiment of an elementary light unit with its digital control device.
• FIG. 10 represents the schematic section of a preferred physical embodiment of a set of elementary light units with numerical control constituting a sub-pixel.
• FIG. 11 represents the correspondence established between a sub-pixel and a set of elementary light units with numerical control according to a preferred embodiment of the present invention.
• FIG. 12 represents the equivalent electronic diagram of a set of elementary light units with numerical control with their power supply and constituting a sub-pixel according to a preferred embodiment.
• Figure 13 represents the equivalent diagram of the electronic circuit of a sub pixel detailed by Figure 12.
• FIG. 14 represents the electronic diagram for mounting a sub-pixel represented by FIG. 13 associated with a dual memory device according to a preferred embodiment.
• Figure 15 shows the equivalent diagram of the electronic circuit detailed in Figure 14.
• FIG. 16 represents the electronic assembly diagram of a set of three sub-pixels represented by FIG. 16 associated with a validation device according to a first preferred embodiment.
• Figure 17 shows the equivalent diagram of the electronic circuit detailed in Figure 16.
• Figure 18 shows the electronic circuit diagram of a set of n by m (n, m) under pixels represented by Figure 17 and constituting a block of (n, m) under pixels according to a first preferred embodiment.
• Figure 19 represents the equivalent diagram of the electronic circuit of a block of (n, m) under pixels detailed by Figure 18.
• FIG. 20 represents the operating diagram of the electronic circuit constituting a block of (n, m) under pixels represented by FIG. 19.
• Figure 21 represents the electronic diagram of assembly of a set of (n, m) blocks of sub pixels represented by Figure 19 and constituting a screen of (n, m) blocks of sub pixels according to a first preferred embodiment.
• Figure 22 represents the electronic diagram of assembly of a video screen made up of (n, m) blocks of under pixels represented by Figure 21 according to a first preferred embodiment.
• Figure 23 represents the electronic diagram of assembly of a block of (n, m) under pixels represented by Figure 17 and constituting a block of (n, m) under pixels according to a second preferred embodiment.
• Figure 24 represents the equivalent diagram of the electronic circuit of a block of (n, m) under pixel represented by Figure 23 according to this second preferred embodiment.
• Figure 25 represents the electronic diagram of assembly of a video screen made up of (n, m) blocks of under pixels represented by Figure 24 according to this second preferred embodiment.
• Figure 26 represents the electronic diagram of assembly of a set of three sub pixels represented by Figure 15 with a validation device making it possible to form a triplet called pixel according to a third preferred embodiment.
• Figure 27 represents the equivalent diagram of the electronic circuit of a triplet called pixel detailed by Figure 26 according to this third preferred embodiment.
• Figure 28 shows the electronic circuit diagram for mounting a block of (n, m) pixels represented by Figure 27 according to this third preferred embodiment.
• Figure 29 shows the equivalent diagram of the electronic circuit of a block of (n, m) pixels detailed in Figure 28 according to this third preferred embodiment.
• Figure 30 represents the diagram of assembly of a video screen made up of (n, m) blocks of pixels represented by Figure 29 according to this third preferred embodiment.
• Figure 31 shows a video screen with its main components.
• FIG. 1 comprises a means 1 called elementary light cell UL which is connected directly to one of the terminals of a means 2 called a power source Va and which is connected to the other terminal of this means 2 through a means 3 called switch SW.
• FIG. 2 is a diagram showing the operation of the device described in FIG. 1.
• the supply source 2 Va being constantly present, whether this is a direct or periodic voltage, this is applied or not across the terminals of the UL elementary cell depending on whether the SW switch is closed or open.
• the means 1 called the elementary light unit UL emits one or more photon fluxes, that is to say a number of photons debited per unit time in photonic unit system, flux characteristic of its nature and of the type of supply Va applied to it.
• a supply Va adapted to the nature of the elementary light unit UL, it can be obtained that for the same unit of time, which will be called by elementary time convention Te during which it is supplied, it always emits the same photon flux which will be conventionally called elementary light flux ⁇ e and as the elementary light unit 1 emits this flux at a corresponding elementary solid angle the elementary flux ⁇ e will be assimilated by convention to an elementary light intensity.
• FIG. 3 is a diagram which represents the assembly of a set of means 1 called elementary light units UL arranged in a mosaic of 16 by 16 and which are connected to the power source 2 Va by means of means 3 which are SW switches numbered from 1 to 8 according to a preferred non-limiting arrangement of the present invention.
• the means 1 called UL which are blackened represent the ULs which are not activated by the power source 2 Va because the switches 3 to which they are connected are open while the ULs which are clear represent those which are activated by the source supply Go because the switches 3 to which they are connected are closed.
• the switches 3 numbered from 1 to 8 therefore make it possible to apply or not the power source Va to groups of ULs according to this preferred nonlimiting mounting mode.
• the switches 3 allow a number of ULs equal to the power of (n - 1) to be grouped, n being the number of the switch to which these ULs are connected to the power source Va.
• Figure 4 is an addressing table which shows that one can thus activate from 1 to 255 means 1 called UL light units with only 8 address bits applying to switches 3 numbered from 1 to 8 which allow to apply or not to apply the power supply Va to UL groups according to this preferred non-limiting mounting method.
• Each means 1 called UL emitting the same stream of elementary photons ⁇ e when it is activated, in this preferred non-limiting mounting mode, a resulting stream ⁇ sp can therefore be obtained from 1 to 255 times the elementary stream ⁇ e, which, added a resulting flow ⁇ sp 0 when everything is disabled, gives 256 values of resulting flow ⁇ sp.
• the nature of the ULs and the type of supply Va which is suitable for them to obtain this result could be of several kinds.
• the ULs could be simple filament or flash lamps, LED light-emitting diodes, TFEL Thin Electroluminescent films or plasma cells and their supply Va could be a frequency or alternating voltage so that the switches SW being transistors put or not these lamps, these diodes or these TFEL or plasma cells in relation to their supply Va so that they emit or not these elementary fluxes ⁇ e.
• the ULs could also be liquid crystal cells, LEP Light Emitting Polymers or micro mirrors which are activated or not depending on whether the switches SW put them in relation or not with their supply Va which would then be a DC voltage.
• FIG. 5 is an electronic circuit diagram which symbolizes this preferred embodiment and next to which is its specific operating diagram.
• a means 1 called UL elementary light unit is a cell containing a gas whose composition gives it luminescent properties particular when it is properly excited and ionized by a suitable diet.
• a means 4 called capacitance C is connected to one of the terminals of the means 1 and connected to one of the terminals of the power source 2 Va via the switch 3. The other terminal of the source 2 supply Va is connected directly to the other terminal of the elementary light unit 1.
• the supply source 2 Va generates, for example without limitation, an alternating voltage, represented on the diagram by the sinusoidal curve TENSION_Va-
• the curve TENSION_PT_A which is dotted shows in a simplified way the variation of the voltage measured at point A of the assembly diagram.
• the operation of the electronic assembly presents two cases according to whether the switch 3 is open or closed which is represented by the curve ETAT_DE_SW. In the first case if the switch 3 is open, no supply voltage Va is applied to the device and nothing happens since the elementary unit 1 is not connected to the power source 2 Va and is therefore deactivated, or constantly extinguished. In the second case, the switch 3 is closed and the supply voltage Va therefore applies to the entire circuit.
• the TENSION_PT_A curve shows that the voltage measured at point A remains at a constant value until the absolute value of the supply voltage
• the absolute value of the supply voltage I Va I is less than this ionization voltage I Vi
• the current no longer flows and the voltage measured at point A is then maintains the value ⁇ I Vi + ⁇ v I reached.
• the curve ETAT_DE_UL of the diagram shows that for a period of the supply voltage Va, whose peak-to-peak amplitude is slightly greater than 2 times the absolute value of the ionization voltage I Vi I, we obtain 4 luminescent ionizations of the gas from the elementary cell 1 when the switch 3 is closed.
• the ionization time Ti of the gas and therefore of luminescence of the elementary cell 1 is essentially a function of the resistance of the power source, the nature of the gas and its pressure as well as the value of the capacity C.
• Figure 6 shows the same thing as Figure 5 except that the switch SW has been replaced by an electronic transfer gate PT with digital control, constituted for example by no limitation by transistors, which puts or not the circuit in communication with the power source 2 Goes according to whether its logic input L is at one (1) or at zero (0) which is represented by the curve ETAT_DE_L of the diagram.
• This diagram therefore shows the operation of the device over several periods and we find the supply voltage Va, the voltage measured at point A and the ETAT_DE_UL curve of the luminescent ionization pulses. This diagram makes it possible to draw several conclusions.
• the ionization duration Ti is therefore also reduced, luminescent pulses of elementary flux ⁇ e, but generally they always have the same value.
• Te Ti an elementary flux ⁇ e.
• the transfer gate therefore serves by simple binary digital control to allow or not these luminescent pulses emitting these elementary fluxes of photons ⁇ e. As the frequency of these luminescent pulses ⁇ e can be very high, this digital control of the transfer gate can be too, in any case it can very easily be from 25 to 30 Hz if not more.
• FIG. 7 represents the diagram of an assembly composed of the elementary light unit 1 connected to one of the terminals of the power source 2 Va and connected to the capacitor 4 itself connected to the transfer gate 3 which is connected to the other terminal of the power supply 2 Va.
• Transfer door 3 has a digital control input L accepting two logic states zero (0) and one (1).
• FIG 8 shows the equivalent diagram of the electronic circuit detailed in Figure 7.
• Circuit 5 is made up of the entire light unit 1, capacity 4 and the transfer door 3. It can connect to the power source 2 Va and its input L receive a binary logic command.
• Figure 9 shows the schematic section of a preferred physical embodiment of an elementary light unit with its digital control device.
• a transparent support 6 receives on its inner face a layer of a luminescent substance 7 and a transparent electrode 8.
• the assembly of means 10 to 12 constitute a capacitor 4 which is surrounded by an insulator 13.
• the electrode 8 produced with a uniform conductive substance transparent to the flux of photons 15 or in the form of a fine conductive grid is connected directly to one of the terminals of the supply source 2 Va.
• the electrode 11 is connected to the transfer gate 3, which is connected to the other terminal of the power source 2 Va.
• This transfer door 3 is blocked or driven depending on whether a zero (0) or a (1) logic signal is applied to its input L. (We could have used reverse logic). Between the two sets of means 6 to 8 and 10 to 12 is a gas 14 of given composition and pressure similar to that used, for example without limitation, in plasma screens which, when it is suitably excited and ionized, emits by luminescence a stream of photons 15 of a wavelength characteristic of its composition and of its pressure. When the transfer door 3 is blocked, for example by applying a 0 to its input L, nothing happens since no voltage from the power source 2 Va is applied to the device.
• a series of gas ionization pulses 14 is obtained which then generate the same series of luminescent pulses 15, an elementary flux of photons D'unee of a particular wavelength.
• This elementary flux of photons ⁇ e of a particular wavelength 15 passes through the electrode 8 and is transformed by the luminescent substance 7 which in turn emits by luminescence an elementary flux of photons ⁇ e, represented by the arrows 16, d ' a wavelength characteristic of its composition and which pass through the transparent support 6 which may be glass or a poly carbonate.
• compositions of these luminescent substances 7 can for example be non-limiting, similar to those used for plasma screens and which emit, depending on their composition, photon fluxes corresponding to the primary colors of red, green or blue light, it can also be a mixture of these to obtain white or any other specific color.
• the activation voltage is much lower, of the order of a few volts or tens of volts, since it is the voltage ionization I Vi I, in addition there is no need for additional electrodes for the voltage for maintaining the discharges nor for a device for controlling the discharge current flows since it operates by elementary luminescent high frequency ionization pulses ⁇ e whose current flow rates are self limited by capacity 4 which makes a few nano or tens of nano Farad depending on the conductivity of the ionized gas and the value of the ionization time Ti that is desired obtain as elementary time Te for the elementary fluxes ⁇ e.
• FIG 10 shows the schematic section of a preferred physical embodiment of a set of elementary light units UL with numerical control identical and similar to that shown in Figure 9 and constituting a sub pixel.
• a means 17 delimits the whole.
• the support 6 covers the assembly and is coated with the same substance 7 and with an electrode 8 which is common to all of the light units and is connected directly to the power source 2 Va.
• This figure shows that when, for example, a logic command (1) is applied to the input L of one or more transfer doors 3, the luminescent ionization pulses 15 of the gas 14 are possible whereas they do not are not when applying the logic zero command (0) to the input L of one or more transfer gates 3.
• This section represents, according to a non-limiting example, an assembly constituting a Red or Green or Blue sub-pixel depending on whether the composition of the luminescent substance 7 will make it possible to emit by luminescence of the photon fluxes 16 of red, green or blue wavelength under the effect of the photon fluxes 15 emitted by luminescence by the gas 14 for each of the ULs which are activated by their transfer gate 3.
• FIG. 11 represents the correspondence which is established between each sub-pixel 18 constituting the RGB matrix of a video screen and a set of elementary light units with digital control UL according to a preferred embodiment of the present invention.
• Each sub-pixel 18 is broken down according to this preferential incorporation of the invention into a mosaic of 16 by 16 means 19 each composed of an elementary light unit 1 UL with its capacitor 4.
• These means 19 are connected according to this preferential incorporation of a goes directly to the supply source 2 Va and on the other hand to their transfer door 3 numbered PT1 to PT8 having their digital control inputs L1 to L8.
• the dimensions of the elementary light units 19 are such that the dimensions of their assembly correspond to the dimension desired for the corresponding sub-pixel.
• One can also increase or decrease the number of elementary light units to obtain a total flux ⁇ sp 2 n x ⁇ e having more or less values by using a binary word having the number of bits n corresponding to make video screens requiring more or less colors or even bi-chromic screens called monochrome or semitones used for displaying alphanumeric and / or graphic information for example.
• FIG. 12 represents the equivalent electronic diagram of a set of elementary light units with numerical control with their power supply and constituting a sub pixel according to the preferred embodiment described in FIG. 3.
• the light units 1 are each connected by a directly listed on a common terminal of the supply source 2 Va and on the other hand to their capacity 4 which are themselves connected to a transfer door 3 according to the preferred incorporation already mentioned for Figures 3 and 11 and which connects them or not with the other terminal of the supply source 2 Va depending on whether the digitally controlled input L1 to L8 of these transfer gates 3 is within range at the corresponding logic value.
• Figure 13 represents the equivalent diagram of the electronic circuit of a sub pixel.
• the circuit 20 represents all of the elements detailed in FIG. 12, with its inputs connected to the power supply 2 Va and the digitally controlled inputs L1 to L8 of the transfer doors 3.
• FIG. 14 shows the electronic diagram for mounting a sub-pixel detailed in Figure 13 associated with a dual memory device according to a preferred embodiment of the invention.
• the circuit 21 symbolizes all the elements detailed in FIG. 12 with its connections to the power source 2 Va and its digitally controlled inputs L1 to L8.
• the flip-flop outputs constituting a one-bit memory, the assembly of which constitutes an 8-bit display memory 22 having a common digital validation command M.AFF.
• the inputs of this display memory 22 are connected to the output of flip-flops with one-bit memory, the assembly of which constitutes an 8-bit display memory following 23 having a digital validation command M.SVT.
• the 8-bit words which are sent to this sub-pixel are sent to the inputs D1 to D8 of the following display memory 23.
• the operation of this arrangement makes it possible to store two words of 8 different bits depending on whether a command is applied validation on M.AFF or M.SVT.
• the 8-bit word which is stored in the following display memory 23 by the validation command M.SVT is that which corresponds to the binary value of the pulses of the following total stream ⁇ sp of this sub-pixel.
• the 8 bit word which is stored in the display memory 22 is the one which corresponds to the binary value of the total flux pulses ⁇ sp which is actually emitted, or displayed, by the sub pixel.
• the 8-bit word contained in the following display memory 23 is transferred to the display memory 22. While the sub-pixel emits the total flow pulses ⁇ sp determined by the value of the 8-bit word contained in the display memory 22 it is possible to load into the display memory according to 23 another 8-bit word corresponding to the value of the pulses of the total stream ⁇ sp which will then be sent by the under pixel. We have therefore clearly separated the refresh rate from the value that is displayed by the sub-pixel of the loading, or change, frequency from the value that it displays.
• the frequency of these pulses corresponds to the refresh frequency of the sub-pixel and the latter , depending only on the characteristics of the voltage applied by the power source 2 Va, can be several kHz and even MHz according to what has been explained in Figures 5 and 6.
• Figure 15 shows the equivalent diagram of the electronic circuit detailed in Figure 14.
• the circuit 24 corresponds to all of the means detailed in Figure 14 with its inputs for connecting to the power supply 2 Va, its inputs digital commands D1 to D8 making it possible to receive the words of n ⁇ 8 bits corresponding to the total flux values ⁇ sp which is emitted by pulses by the sub pixel as well as the validation input M.SVT for their storage in the display memory following 23 and the validation input M.AFF for their storage in the display memory 22.
• FIG. 16 represents the electronic assembly diagram of a set of three sub-pixels represented by FIG. 15 associated with a validation device according to a first preferred embodiment.
• the equivalent circuit described in Figure 15 is found in the three circuits 24 with their inputs connected to the power source 2 Va and their inputs D1 to D8 connected to a common data bus.
• the validation input of the display memories 22 of these three circuits 24 are connected together so as to send them at the same time a validation signal M.AFF.
• three means 25 are used which are type D flip flops connected in series as in a shift register.
• the CP inputs of these FFDs are connected to a common clock source H while their R inputs are connected to a common Reset source.
• the input D of the first (from the left) FFD is connected to the input called SP.PCD because it comes from the previous sub-pixel if it exists or otherwise from the electronic control circuit.
• the output Q of the first FFD is connected both to the input M.SVT of the first circuit 24 to validate the input of its next display memory 23 and to the input D of the second FFD.
• the second FFD and the third FFD are connected according to the same principle to validate each by their output Q the input of the following display memory 23 of the following two circuits 24 which correspond to them.
• the Q output of the third FFD is also connected to the output called SP.SVT and will allow you to connect to the SP.PCD input, therefore to the D input of the FFD for validation of the next sub-pixel if it exists.
• the first 8-bit word on the bus is sent to the inputs D1 to D8 and corresponding to the value of the following total flux ⁇ sp which will be emitted by the red pixel as well as a single pulse validation one (1) logic on input SP.PCD which is connected to input D of the first FFD.
• the validation pulse applied to D then appears on the output Q of the first FFD and validates the input M.SVT of next display memory of the first circuit 24 corresponding to the red sub-pixel thus allowing the storage of the following display memory 23 of the first 8 bit word intended for it.
• the other Q outputs of the other two FFDs are still at zero, they invalidate the M .SVT inputs of the other two circuits 24 corresponding respectively to the Green pixel and the Blue pixel and therefore prevents memorization in their display memory according to 23 of the data on the bus.
• the 8-bit word is sent on the bus corresponding to the value of the following total flux ⁇ sp which will be emitted by the Green sub-pixel.
• the validation pulse present on the Q output of the first FFD and which is applied to the D input of the second FFD and which corresponding to the green sub pixel then appears on its Q output and validates the memory input M.SVT of display following 23 of the Green sub-pixel allowing storage in display display 23 of the 8-bit word intended for it.
• FIG. 17 shows the equivalent diagram of the electronic circuit of a single sub-pixel with its validation device.
• the circuit 26 represents a single circuit 24 with a single FFD 25 according to FIG.
• Figure 19 shows the equivalent diagram of the electronic circuit of a block of (n, m) under pixels with a circuit 27 made up of all the elements detailed in Figure 18, its inputs connected to the power source 2 Va , the inputs D1 to D8 connected to the data bus, the outputs SP.SVT making it possible to transmit the validation signal of the display memories according to 23 to the sub pixels of the block of (n, m) under the pixels following the inputs SP.PCD allowing to receive the validation signal of the following display memories 23 coming from the block of (n, m) under previous pixels, the input M.AFF making it possible to receive the simultaneous validation signal from all the memories of display 22 of all the sub-pixels of the block, the Reset input allowing to reset all the FFDs 25 of all the circuits 26 of the block simultaneously to zero and the input allowing to receive the clock signal H applied simultaneously on the set of s FFD 25 of the block of (n, m) under pixels mounted according to this first preferred embodiment.
• Figure 20 represents the diagram of operation of the electronic circuit constituting a block of (n, m) under pixels represented by Figure 19.
• Figure 21 represents the electronic diagram of the assembly of a set of (K, P) block circuits of (n, m) under pixels composed of detailed circuits 27 by FIG. 18 and making it possible to constitute a screen of (K, P) blocks of (n, m) under pixels according to a first preferred embodiment.
• These circuits 27 of (n, m) under pixels are connected to the same power source 2 Va and their inputs D1 to D8 connected to a common data bus.
• Their validation inputs M.AFF of their display memories 22 are connected together.
• H clock and Reset inputs are also connected to the same.
• the validation signal M.SVT appears on the output SP.SVT to validate the first sub-pixel on the input SP.PCD of the block circuit of (n, m) under pixels 27 next.
• the set of values of all the sub pixels corresponding to the following image is available in the set of next display memories 23.
• a the display validation signal of the next image is then sent to the input M.AFF which simultaneously validates the transfer of the content of all the following display memories 23 from all the circuits 27 to the display memories 22.
• the new image then appears at once in its entirety as for a film on film.
• the displayed image is, in its entirety, refreshed at the frequency of the luminescent pulses 16 determined by the supply voltage Va is several kilo and even mega Hertz while it is loaded or changed to the frequency of the validation signal M.AFF of the display memories 22, that is to say from 25 to 30 images per second or 25 to 30 Hertz.
• the clock frequency H of the device which loads the data corresponding to the value of each sub pixel is directly dependent on the number of these sub pixels and therefore on the resolution of the image.
• Figure 22 represents the electronic diagram of assembly of a video screen made up of (K, P) blocks of under pixels represented by Figure 21 according to this first preferred embodiment.
• This preferred embodiment of a video screen achieves here three of the five characteristics set as objectives since firstly there is an entirely digital display device of very small thickness since it consists of a mosaic of (K, P) circuits integrated 27, secondly the refresh rate is very high and independent of the resolution, the frequency of change and the display size of the images since only a function of the supply voltage Va which triggers the luminescent pulses of total flux elementary ⁇ sp, thirdly, each displayed image appears at once without scanning the pixels or matrix addressing them since all the circuits 27 are mounted on a common data bus and this is the validation signal M.AFF display memories 22 which transfer the following image contained in all of the memories at once next display 23 to all of the display memories 22 making it appear globally as during the projection of a film on film.
• FIG. 23 represents the electronic diagram of assembly of a block of (n, m) under pixels represented by Figure 17 and making it possible to constitute a block of (n, m) under pixels according to a second preferred embodiment.
• the interconnection of the sub pixels and its operation are identical to what is described for Figure 18 except that this arrangement makes a grouping in (m) lines of (n) circuits of sub pixels 26.
• FIG. 24 represents the equivalent diagram of the electronic circuit of a block of (n, m) under pixels according to this second preferred embodiment.
• a circuit 29 consisting of the circuits detailed in FIG.
• the 23 has its inputs connected to the supply source 2 Va, the inputs D1 to D8 connected to the data bus, the outputs SP.SVT subscribed (n, 1 to m) making it possible to transmit the validation signal of the last sub-pixels (n) of the (m) lines of the current block to the next sub-pixel block, the indexed SP.PCD inputs (n, 1 to m) making it possible to receive the validation signals from the last sub pixels (n, 1 to m) of the previous sub pixel block, the input allowing to receive the signal M.AFF of simultaneous validation of all the display memories 22 of circuit 29, the input allowing receive the simultaneous Reset signal from all of the FFDs 25 of circuit 29 and the input making it possible to receive the clock signal H applied simultaneously to all of the FFDs 25 of circuit 29 according to this second preferred embodiment.
• Figure 25 represents the electronic diagram of assembly of a video screen made up of (K, P) blocks of (n, m) under pixels according to this second preferred embodiment.
• PCD (1) for validation of the first display memories along 23 of each line (m) of each block (K) of subpixels are connected to the last outputs M.SVT (n) of validation of display memories following 23 of the same line (m) of the previous block (K-1), the last output (n) of validation of next display memory 23 of line (m) of block (K) being connected to the input (1) for validation of the first display memory along 23 of line (1) of the block (1, P + 1).
• the data are loaded line by line of all the circuits 29 located on the same line (P) and propagate line by line (m) of blocks (P).
• This second mounting mode makes it possible to have a data stream on the bus arriving at the inputs D1 to D8 and corresponding to each sub pixel which is directly compatible with the data stream coming from a digital video source with line and frame scanning. since all the same lines (m) of the lines of the (K) blocks are filled one after the other which amounts to filling the screen line by line.
• the data flow is modified since each block of sub pixels must be filled before filling the next one. In this case too, it is possible to mount several similar screens in mosaic without using external video circuits because all the signals are available on the printed circuit 30.
• Figure 26 represents the electronic diagram of assembly of a set of three sub pixels represented by Figure 15 with a validation device making it possible to form a triplet called pixel according to a third preferred embodiment.
• a validation device making it possible to form a triplet called pixel according to a third preferred embodiment.
• Figure 27 shows the equivalent diagram of the electronic circuit of a triplet called RGB pixel according to this third preferred embodiment.
• the means 31 is detailed in Figure 26. Its connections are the same as for Figure 17 except that it has 24 inputs D1 to D24 and an input called P.PCD (instead of SP.PCD) and an output called P .SVT (instead of SP.SVT).
• Figure 28 shows the electronic circuit diagram for mounting a block of (n, m) pixels 31 represented by Figure 27 according to this third preferred embodiment. The assembly and operation is similar to that described in FIG.
• FIG. 29 represents the equivalent diagram of the electronic circuit of a block of (n, m) pixels according to this third preferred embodiment.
• the circuit 32 detailed in FIG. 28 is connected in an identical manner to FIG. 24 except that the data bus is now 24 bits connected to the inputs D1 to D24, that the validation inputs of the display memories according to 23 of the previous pixels are called P.PCD (n, 1 to m), that the pixel validation outputs of the following blocks are called P.SVT (n, 1 to m).
• Figure 30 represents the diagram of assembly of a video screen made up of (n, m) blocks of pixels represented by Figure 29 according to this third preferred embodiment.
• the assembly and operation are the same as those described in Figure 25 except that the interconnection printed circuit 33 on which the (K, P) circuits 32 are mounted carries a 24-bit data bus connected to the inputs D1 to D24 .
• the advantage of this arrangement with a 24-bit bus is only to allow a reduction in the frequency of loading of the data into the following memories 23 of the sub pixels since they no longer arrive one behind the other in words of 8 bits for Red, Green and Blue but at the same time in parallel on 24 bits.
• FIG 31 shows a video screen with its main components shown diagrammatically.
• Each integrated circuit 27, 28 or 32 produced according to one of the three preferred modes indicated in a nonlimiting manner is sealed by the electrode 8 which is allowed to pass the flux of photons 15 emitted by luminescence by the ionized gas 14 which is located between them inside and is common to all the light units UL of the integrated circuit since it is connected directly to the power source 2 Va.
• the assembly 27, 29 or 32 and 8 each constitute integrated circuits 34 which are mounted in mosaic on a printed circuit 28, 30 or 33 produced according to one of the three preferred modes indicated and carrying the supply tracks Va, 8 or 24 bit data bus, H clock and reset, M.AFF validation of the display memories 22 and M.SVT validation of the display memories according to 23.
• this mosaic of integrated circuits 34 a transparent support 6 on the inner face of which a matrix composed of three substances 7 which have emitted by luminescence 16 has a red, green or blue color depending on their composition when they are excited by the pulses photon flux 15 emitted by the integrated circuits 34.
• This support 6 produced for example without limitation in screen printing is superimposed exactly under pixels to sub pixel to the integrated circuits 34 and thus form a surface d uniform display in one piece, even if there are several similar printed circuits 28, 30 or 33 below.
• the fourth objective is achieved, which is to obtain video screens which are always of small thickness and display surface in a single piece even for dimensions greater than 42 inches diagonally called giant screens.
• this type of integrated circuit it is already possible to produce cylindrical screens because the integrated circuits 34 can be mounted on flexible printed circuits and the support 6 which comes above can also be flexible.
• the integrated circuits 34 can have a hexagonal shape, it is possible to mount these on a printed circuit of the same shape and thus obtain spherical screens.
• This digital video screen device therefore comprises one or more printed circuits on which are mounted one or more integrated circuits which are covered by a one-piece display surface coated with one or more luminescent substances which are excited by the integrated circuits placed below such that: a) each sub pixel 18 forming part of a point of the image displayed by the video screen a certain number of light elementary units 1 are matched, each of which emits a flux elementary photons ⁇ e corresponding to an elementary color intensity when activated, b) the elementary light units 1 constituting each sub pixel 18 are all connected on the one hand to the common terminal of a power supply source 2 Va which is adapted to them and on the other hand are activated or not by means of electronic switches 3 which may or may not each connect one or more at the same time several light elementary units 1 at the other terminal of the power source 2 Go according to the binary words applied to their logic controls and corresponding to the values of the color intensities desired for each sub pixel, c) each light elementary unit 1 activated emits a continuous or pulsed elementary flux of photon
• the total continuous or pulsed flux ⁇ sp corresponding to the intensity of the color emitted by a sub pixel is added to the total continuous or pulsed flux ⁇ sp corresponding to the intensity of the color emitted at the same time by the other two sub pixels with which it constitutes an RGB triplet to obtain by chromic tri addition the color of the corresponding point of the image
• the chromic tri addition of the set of total continuous or pulsed flux ⁇ sp corresponding to the intensity of the colors emitted in same time by all the sub-pixels constituting the RGB triplets of all the points of the image thus correspond to all the colors of the image displayed by the video screen
• all of the validation inputs for the flip-flops of the display memories 22 of all the sub-pixels of the screen are connected together to allow their simultaneous validation
• All the inputs of the flip-flops constituting the display memory 22 of each sub-pixel are connected to the so rties flip-flops constituting the following memory 23 of each sub-pixel whose
• a device 25 validates the entry allowing the memorization in the next memory 23 of the sub pixel of the binary word present on the bus which is intended for it so that when all the following memories 23 of all the sub pixels of the screen have received the binary word intended for them a signal is applied to the common input for validation of the display memories 22 of all the sub pixels of the screen allowing the simultaneous transfer of the content of the following memories 23 into the memories of display 22 which displays all of the following image on the screen at once, m) while the entire image is displayed permanently or in frequency the following memories 23 can be loaded with the words binaries corresponding as a whole to the colors of the following image at a frequency which depends on the frequency of change of the image and its resolution thus making it possible to separate the frequency of loading ent or change the next image to the refresh rate of the displayed image.
• Each elementary light unit 1 is a gas cell 14 contained between on the one hand a transparent support 6 coated with a luminescent substance 7 and an electrode 8 which is connected directly to the power source 2 Va and d on the other hand an insulating support 9 on which the capacitor 4 has been produced surrounded by an insulator 13 by constituting it with an electrode 10 deposited on a dielectric 12 itself deposited on the electrode 11 which is connected to the transfer door 3 which is itself connected to the other terminal of the power source 2 Va so that, depending on the state of its logic control input L, this transfer door 3 is conductive or blocked to apply or not the source 2 d goes to the whole.
• the gas 14 can then be similar to those used in plasma screens and has an ionization voltage
• the supply source 2 Va then generates a periodic supply voltage whose peak-to-peak value is slightly greater than a multiple of the absolute value of the voltage d I Vi
• the capacity 4 can have a value ranging from a few pico to tens of nano-Farad depending on the conductivity of the gas 14 when it is ionized and according to the value of the ionization time Ti which it is desired to obtain as elementary time Te for the elementary fluxes ⁇ e and determined to limit the current delivered by the source 2 through the ionized gas 14 and catch up with the supply voltage Va to maintain it at this value until the next ionization of the gas 14 which thus always behaves like a plasma operating in pulse mode of subnormal or normal luminescent ionizations with an instantaneous current consumption of the order of a few micro or tens of
• the frequency of the luminescent ionization pulses 15 transformed into luminescent pulses 16 is only a function of the peak to peak value of the supply voltage Va and its frequency as well as the value of the ionization voltage I Vi I of the gas 14 and the value of the capacity 4 and is the same for all the elementary light units 1 activated of all the sub-pixels constituting the screen and corresponding therefore at the refresh rate of the image it displays.
• n (2 n ) elementary light units 1 which are all connected on the one hand to the common terminal of a power source 2 Va which is their adapted and on the other hand are activated or not via n transfer doors 3 with logic controls L1 to Ln which may or may not each connect at the same time a number 2 power n-1 (2 ⁇ "1 ) light elementary units 1 constituting a sub-pixel at the other terminal of the power source 2 Va according to the binary words of n bits which correspond to the value of the color intensity desired for the sub-pixel and which are applied to the logic commands L1 to Ln so that 2 n values of the color intensity emitted by luminescent pulses 16 are obtained by the sub pixel.
• the set of 2 n light elementary units 1 constituting a sub pixel have a common electrode 8 who is connected source 2 supply Va, x)
• the phosphor 7 corresponding to a color covers all the 2 n light elementary units 1 constituting a pixel in which can be sealed by means 17 which may also serve as conducting link between common electrode 8 and the power source 2 Va if it is coated inside an insulator 13.
• the 2 "light elementary units 1 with the n transfer doors 3 including the logic controls L1 to Ln are connected to a display memory 22 itself connected to a following memory 23 constitute a basic circuit 24 having n inputs Dn as well as an input M.AFF allowing to validate the display memory 22 and an input M.SVT allowing to validate the following memory 23 as well as two terminals to connect to the power source 2 Va.
• each sub pixel is associated with a disp positive 25 which is a D type flip-flop which comprises an input D connected to the output Q of the device 25 of the previous sub-pixel if it exists or of the device which sends the 8-bit words on the bus to which the inputs D1 to D8 of the basic circuit 24 and which comprises an input CP receiving a clock signal H synchronized with each 8-bit word present on the bus and comprises an input R capable of receiving a Reset signal returning the flip-flop D to its initial state and comprising an output Q which is connected to the validation input M.SVT of the next memory 23 of the sub pixel and to the input D of the device 25 of the next sub pixel if it exists so that each sub pixel of the screen thus constitutes the link of
• a block of n lines of m (n, m) under pixel 18 is formed in the form of an integrated circuit 27 formed according to circuit 26, the inputs D1 to D8 of which are connected to a common bus comprising 8 bits and of which the input SP.PCD allows the validation of the next memory 23 coming from the block of (n, m) under the previous pixel and having an output SP.SVT allowing the transmission of the validation signal of next memory 23 to the block of (n , m) in the following pixel and having the inputs common to all the screen pixels making it possible to receive the clock H the Reset and the signal M.AFF for the validation of the display memory 22 as well as the terminals allowing to connect to the power source 2 Va and to which a common transparent electrode 8 is added over it which seals the assembly by means of the means 17 to form the integrated circuit 34.
• a video screen is formed having a display in one piece by placing on a circu it printed 28 comprising an 8-bit common bus making it possible to connect the inputs D1 to D8 of a mosaic of circuits 34 as well as their inputs SP.PCD to their outputs SP.SVT to chain them together and having the inputs common to all the sub pixels of the screen allowing them to receive the clock H the Reset and the signal M.AFF as well as the power source 2 Va, gg) the mosaic of circuits 34 constitutes the excitation source in pixel by sub pixel of the RGB triplets formed with the luminescent substances 7 deposited by screen printing on the transparent support 6 in one piece placed above all of the elements thus constituting a screen whose display surface is in one piece.
• the sub-pixels constituting the screen and each symbolized by the basic circuit 24 are associated with a device 25 which is a D-type flip-flop whose output Q is connected to the validation inputs M.SVT of the following memories 23 by groups of three sub-pixels thus constituting a circuit 31 for each of the triplets of the points of the screen, ii) the inputs of the following memories 23 are all connected to a 24-bit data bus so as to receive at the same time when they are validated the three 8-bit words in parallel corresponding to each triplet thus making it possible to have a clock frequency three times lower for loading the data into the following memories 23.
• the integrated circuits 34 can have a square shape, rectangular or hexagonal arranged on printed circuits 28 having a shape making it possible to produce thin video screens whose display surface can be flat, cylindrical and even spherical.

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