Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
  • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
  • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current
  • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
  • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators

Definitions

• the present invention relates to a device for controlling a circuit for generating reference voltages. More specifically, this control device makes it possible to switch reference voltages as a function of a logic control signal, to be applied in particular as bias voltages of cascode transistors in a high voltage level translator.
• An application example concerns integrated circuits comprising electrically programmable non-volatile memories.
• a high voltage translator is usually used, also called a level translator.
• This translator receives as inputs a logic control signal and a high voltage input. Depending on the logic level Vcc or 0 of the logic control signal, which in the case of a memory will come from a write command signal, the mass or the level of l are obtained at the output of the translator. 'high voltage input.
• These translators are well known to those skilled in the art. These translators usually include an intermediate stage, between the stage of the upper transistors and the stage of the lower transistors. This intermediate stage comprises one or more cascode stages. It allows the internal nodes of the translator to be limited to intermediate voltage levels, so that no transistor of the translator sees too high a voltage across its terminals.
• FIG. 1 An example of a cascode stage translator of this type, in CMOS technology, is shown in FIG. 1.
• the upper stage comprises in the first branch, a P-type transistor M, Ml, and in the second branch, a P-type transistor M, M2.
• the source of these transistors is connected to the high voltage input node EHV.
• the bottom stage comprises an N type M transistor, M3, and in the second branch, an N type M transistor, M4. These transistors have their source connected to GND ground.
• the cascode stage comprises four Mos transistors: two P-type Mos transistors, M5 and M6, one in each branch, under each top transistor and two N-type Mos transistors, M7 and M8, one in each branch, above of each bottom transistor.
• the MOS P transistors M5 and M6 receive the reference voltage VREF P on their gate.
• the MOS transistors N M7 and M8 receive the reference voltage VREF ⁇ on their gate.
• the output VOUT of the translator is taken between the cascode transistors N and P of a branch, at the drains of the transistors M6 and M8 in the example.
• the gate of the lower transistor M3 of the first branch of the translator receives a logic signal from switching denoted IN, and the gate of the lower transistor M4 of the second branch of the translator receives the reverse signal, denoted / IN.
• the role of the cascode stage is to limit the voltages seen by the transistors of the translator to intermediate levels.
• the cascode transistors of a translator are usually polarized by the logic supply voltages Vcc (cascode transistors Mos N) and GND (cascode transistors Mos P). In other translators, they are polarized by reference voltages VREF ⁇ , VREF P , generated from the high voltage.
• a control device comprising a voltage reference REF circuit and a COM control circuit, so as to obtain voltage references, depending on the level of high voltage input EHV.
• this control device makes it possible to switch the translator into the low values of the high voltage input (quiescent level), by switching as bias voltages of the cascode transistors, reference voltages equal to the voltages d logic supply Vcc and GND.
• the control device then switches as the bias voltages of the cascode transistors, the reference voltages VREF ⁇ , VREF P , defined by the series of transistors of the reference circuit mounted as a diode between the high voltage node and the ground.
• the output of the translator then follows the rise in voltage of the high voltage input EHV with the advantages of polarization of the cascode transistors by the reference voltages VREF ⁇ , VREF P.
• the translator can switch in one direction or the other, with these bias voltages.
• Vcc in the example it is the voltages Vcc and GND which apply as bias voltages.
• the operating window of the translator is widened (low voltage switching) and its translators do not undergo stress due to the passage of the high voltage node from its rest position, Vcc in the example, at its nominal value VPP.
• the circuit REF thus comprises three P-type Mos transistors M12, M13 and M14, connected in series between the high voltage input node N of EHV, and the ground GND.
• the first and third transistors M12 and M14 each have their gate connected to their drain.
• the second transistor M13 is controlled by a COM control circuit. Its drain and its source respectively provide a first reference voltage VPOL I and a second reference voltage VPOL 2 . These are the voltages which are applied in the example as gate bias voltages of the cascode transistors of the high voltage translator.
• the COM control circuit makes it possible to control the gate, drain and source voltage of the second transistor M13, according to the level of a control signal / WR.
• FIGS. 2 and 3 The operation of such a control device is illustrated in FIGS. 2 and 3, in an example in which the quiescent level of the high voltage input EHV is Vcc.
• the first operating mode corresponds to the high-voltage input at its quiescent level, Vcc, in the example
• the second operating mode corresponds to the high voltage input rising to its nominal value VPP.
• the COM control circuit mainly comprises four Mos transistors M15, Ml ⁇ , M17 and M18, as shown in FIG. 1.
• the P type transistor M15 is connected between the logic supply voltage Vcc and the first intermediate node A of the reference circuit REF, connected to the source of the transistor M13.
• the N type transistor Ml ⁇ is connected between the second intermediate node B of the reference circuit, connected to the drain of the transistor M13, and the GND ground.
• the P-type transistor M17 is connected between the logic supply voltage Vcc and the gate of the transistor M13.
• the transistor M18 is connected between the gate and the drain (node B) of the second transistor M13.
• the transistors Ml ⁇ and M18 are controlled on their gate by the logic control signal / WR of the control circuit and the transistor M15 is controlled by a signal VNP referenced at the high voltage input EHV and coming from the signal / WR and of reverse logic .
• the transistor M17 is connected on its gate to the second intermediate node B.
• this control circuit is as follows: When the signal / WR is at "1", the transistor Ml ⁇ is on and pulls the second intermediate node B at zero, and consequently the gate of the transistor M17.
• the transistor M18 is blocked. Also, the transistor M17, which is turned on, brings the voltage Vcc to the gate of the transistor M13, which is thus forced to the off state.
• the transistor M15 is also conducting, since the signal VNP is of inverse logic to the 'signal / WR. It therefore brings the voltage Vcc to the first intermediate node A.
• the intermediate nodes A and B are comforted in their respective levels Vcc and GND, whatever the voltage level on the high input voltage.
• the transistors M15 and Ml ⁇ go to the blocked state, and consequently the transistor M17 also goes into the off state.
• the transistor M18 turns on and actively connects the gate of the transistor M13 to the second intermediate node B, that is to say to its drain.
• the transistor M13 is then found connected as a diode like the other transistors M12 and M14 of the reference circuit. We find the normal functioning of the reference circuit: the voltages at nodes A and B follow the rise in voltage of the high voltage input EHV.
• the transistor M15 of the control circuit is connected between the logic supply voltage Vcc and the node A and that the transistor M12 of the reference circuit is connected between the high voltage input EHV and the node A
• this high voltage input EHV reaches the high values
• the transistor M15 must receive on its gate not the high level corresponding to the logic supply voltage Vcc, but that from the high voltage input EHV.
• a first P-type Mos transistor, M19, a second N-type Mos transistor, M20 and a third N-type Mos transistor M21 are connected in series between the high-voltage input node N EHV and the ground GND.
• the transistor M21 is controlled on its gate by the control signal / WR.
• the transistors M20 and M19 have their gates connected together to the first intermediate node A.
• the reverse logic signal VNP and referenced to EHV by the inverter is supplied by the serial connection point between the two transistors M19 and M20. It is the signal applied to the gate of transistor M15.
• the sizes of the MOS transistors 19, 20 and 21 are dimensioned so that, even if the high voltage input EHV takes a value greater than Vcc, VNP remains less than Vcc - V tp , so that the translator works even at high values high voltage input (i.e. it can switch).
• a problem with this control device lies in this complex control of the transistor M15, and which requires three transistors M19, M20 and M21, to ensure its secure blocking or its conduction as a function of the control signal / WR.
• An object of the invention is to reduce the number of transistors of the control circuit, while retaining the functionality of the control device, namely a source of reference voltages.
• control circuit is proposed by which it is provided in particular that the transistor M12 of the reference circuit is no longer directly mounted as a diode, but controlled by control means by which it operates either as a current source or as a diode.
• the invention therefore relates to a device for controlling a REF generation circuit for reference voltages VPOL, VPOL 2 comprising a first P type Mos transistor M12, connected between a node N receiving a high voltage signal EHV and a first intermediate node A, a second P-type Mos transistor M13 connected between • the first intermediate node A and a second intermediate node B and a third P-type Mos transistor M14 connected between the second node and ground, and having its gate connected at its drain, makes it possible to supply reference voltages VPOL X , VPOL 2 on the intermediate nodes A, B.
• This device comprises means for controlling the reference transistors for either, in a first operating mode, forcing the first transistor to reference M12 as current source, the second reference transistor M13 in the off state and short-circuit the third reference transistor M14 mass, or, in a second mode of operation, connect each of said transistors in diode, their gate and drain are connected, using a logic control signal / WR.
• r - Figure 2 shows the shape of the signal VOUT obtained at the output of the translator of Figure 1 as a function of the switching control signal IN;
• - Figure 3 shows the shape of the high voltage input, the control signal of the control circuit according to the control device of Figure 1, as well as the corresponding curves of the reference voltages obtained;
• - Figure 4 shows a control device according to the present invention;
• FIG. 6 shows the equivalent diagram of the device of Figure 5 when the control signal / WR is at "1";
• FIG. 7 shows the equivalent diagram of the device of Figure 5 when the control signal / WR is at "0"; and - Figure 8 schematically shows an integrated circuit comprising such a control device.
• FIG. 4 represents a control device according to the invention.
• This control device makes it possible to supply at the output reference voltages VPOL I , VPOL 2 which are a function of a logic control signal / WR applied at the input of said device:
• the second operating mode corresponds to the case where the high voltage input changes to its nominal value VPP.
• the reference voltages are then established by the reference transistors M12, M13 and M14 mounted as a diode, and as a function of the level of the high voltage input EHV.
• the reference circuit REF includes three M type transistors M12, M13 and M14, connected in series between the node N, receiving the high voltage input EHV, and the GND ground.
• the source and the drain of the second transistor M13 respectively supply the first reference voltage VPOL I , on the first intermediate node A of the reference circuit REF, and the second reference voltage VPOL 2 , on the second intermediate node B.
• These voltages reference may for example be applied as gate bias voltages of the cascode transistors of a high voltage translator.
• the third transistor M14 has its gate connected to its drain.
• the first and second transistors M12 and M13 are themselves controlled by a control circuit COM according to the invention.
• This control circuit comprises means for controlling the first transistor M12 of the reference circuit to either operate it as a current source or operate it as a diode.
• These control means comprise a first P-type MOS transistor, M22, connected between the gate and the drain of the P-type MOS transistor M12, and a second transistor.
• N-type MOS, M23 connected between the gate of the P-M12-type MOS transistor and GND ground.
• the transistors M22 and M23 have their gates connected in common and controlled by the control signal / WR.
• the control means of the second reference transistor M13 comprise the P-type MOS transistors M17 and M18, connected in series between the logic supply voltage Vcc and the drain of the second reference MOS transistor M13.
• the transistor M18 is controlled by the logic signal / WR, but the gate of the transistor M17 is no longer controlled by the source of the third reference transistor.
• the transistor M17 has its gate controlled like the gate of the first reference transistor M12. In other words, their grids are connected together.
• control circuit when the signal / WR is at "0", we find the normal operation of the reference circuit, with its three reference transistors M12, M13 and M14 actively connected as a diode, in series between the high voltage input and ground, allowing the establishment of reference voltages according to the level of this high voltage input.
• FIG. 6 illustrates the operation of the control device according to the invention.
• the equivalent diagram of the control device when / WR is at "1" is shown in FIG. 6.
• the EHV input is at its quiescent level Vcc.
• the equivalent scheme of control device when / WR is at "0" is shown in Figure 7.
• the high voltage input rises or is established at its nominal level VPP.
• the three reference transistors M12, M13 and M14 are mounted as a diode between the high voltage input EHV and ground, bringing node A and node B to reference levels VREF ⁇ and VREF P depending on the level of the input high tension.
• FIG. 5 a variant of a control device is shown, in which the gate of the transistor M17 is directly controlled by the control signal / WR, by means of an inverter II (for me, always the same PB for this' grid command).
• the number of transistors is reduced, linked to the simplification of the control circuit.
• the control device according to the invention is particularly suitable for supplying the bias voltages of the cascode transistors of at least one high voltage translator. It applies quite naturally, but not exclusively to the field of non-volatile memories, for their programming. Such an example of application is schematically represented in FIG. 8.
• the integrated circuit CI represented thus comprises electrically programmable non-volatile memory cells MEM, and at least one high-voltage translator 10 for applying at output VOUT a programming voltage VPP on these cells.
• This translator receives the polarization voltages VPOL I and VPOL 2 from its cascode transistors of a control device 30 according to the invention with source of voltage references, as a function of the control signal / WR.
• the level of these bias voltages supplied by this control device is a function of this control signal / WR.
• this control signal is itself a function of the level of the high voltage input EHV, and in the example, supplied by a circuit 50 for comparison with a determined threshold of the level of this input. It will be noted that the same control device can supply the bias voltages of several high voltage translators.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Electromagnetism (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Read Only Memory (AREA)
• Control Of Electrical Variables (AREA)
• Logic Circuits (AREA)

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  • 2001-01-24 FR FR0100953A patent/FR2819954B1/fr not_active Expired - Fee Related
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