EP1317875A1 - Verfahren zur herstellung einer elektrisch leitfähigen struktur auf einer nichtplanen oberfläche und verwendung des verfahrens - Google Patents

Verfahren zur herstellung einer elektrisch leitfähigen struktur auf einer nichtplanen oberfläche und verwendung des verfahrens

Info

Publication number
EP1317875A1
EP1317875A1 EP01964918A EP01964918A EP1317875A1 EP 1317875 A1 EP1317875 A1 EP 1317875A1 EP 01964918 A EP01964918 A EP 01964918A EP 01964918 A EP01964918 A EP 01964918A EP 1317875 A1 EP1317875 A1 EP 1317875A1
Authority
EP
European Patent Office
Prior art keywords
photoresist layer
photoresist
substrate
electrically conductive
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01964918A
Other languages
German (de)
English (en)
French (fr)
Inventor
Florian Wiest
Ignaz Eisele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
Original Assignee
Epcos AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos AG filed Critical Epcos AG
Publication of EP1317875A1 publication Critical patent/EP1317875A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041Printed circuit coils
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor
    • G03F7/164Coating processes; Apparatus therefor using electric, electrostatic or magnetic means; powder coating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0073Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0082Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0284Details of three-dimensional rigid printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09018Rigid curved substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333Deposition techniques, e.g. coating
    • H05K2203/135Electrophoretic deposition of insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Definitions

  • the invention relates to a method for producing an electrically conductive structure on a non-planar surface, a photoresist layer being applied to the surface in a first step, the photoresist layer being exposed and structured by development in a second step, and an electrically in a third step conductive material is applied to the parts of the surface free of photoresist.
  • the invention further relates to the use of the method.
  • the photoresist layer is structured by lithography with inclined surfaces.
  • the known method has the disadvantage that it is not possible to produce a uniform layer thickness over the entire coil body by spraying on a photoresist.
  • the layer thickness varies very greatly, which causes problems when exposing the photoresist, since different resist thicknesses also require a different exposure time. A varying exposure time can only be achieved with great effort.
  • the known method has the disadvantage that a photoresist layer applied by spraying tends to tear open, in particular at the abutting edges between the flat surfaces of the coil former, as a result of which short circuits can occur during the subsequent electrodeposition of the conductor tracks.
  • the aim of the present invention is therefore to provide a method for producing an electrically conductive structure on a non-planar surface, which allows the processing of a photoresist layer whose homogeneity is improved.
  • the invention specifies a method for producing an electrically conductive structure on a non-planar surface, with the following steps:
  • Electrochemical deposition of a photoresist layer on the surface b) Exposing parts of the photoresist layer c) Removing part of the photoresist layer by developing d) Deposition of an electrically conductive material on parts of the surface free of the photoresist layer.
  • Photoresist is a material that is common in semiconductor technology and that can be tron radiation or electron radiation can be exposed and that is also known under the name "resist”.
  • the process according to the invention has the advantage that the electrochemical deposition of a suitable photoresist on the non-planar surface enables the production of a photoresist layer with a layer thickness with good homogeneity.
  • the method according to the invention has the advantage that a photoresist layer deposited by electrochemical deposition on abutting edges between flat surfaces has only a slight tendency to form cracks.
  • the surface For the electrochemical deposition of the photoresist layer, it is necessary for the surface to be electrically conductive or to be provided with an electrically conductive layer. Such a layer can advantageously be deposited chemically with high uniformity with regard to the layer thickness.
  • the photoresist can be deposited particularly advantageously with a layer thickness which varies by less than 25% over the surface.
  • the photoresist layer being deposited with a layer thickness between 10 and 50 ⁇ m.
  • the photoresist layer can thus be made sufficiently thick, as is required for the production of electrically conductive structures which are intended to represent the turns of a miniaturized coil. With a smaller layer thickness of the photoresist, only thinner electrical trically conductive structures with an ohmic resistance that is too high for coils.
  • a beam of rays with a divergence ⁇ 10 mrad can be used particularly advantageously when exposing the photoresist layer.
  • Such beams with low divergence are available, for example, in the form of synchrotron radiation or in the form of laser radiation. They offer the advantage that it is not necessary to correct the varying distance of the non-planar surface from a planar photolithography mask that is usually used. Depending on the distance between the photoresist layer and the photolithography mask, a larger beam divergence leads to a different magnification of the structure to be imaged.
  • a method is particularly advantageous in which the exposure of the photoresist layer is carried out by imaging a photolithography mask with a transparent mask surface by means of a diverging beam, and the mask surface is thus reduced in relation to the corresponding surface to be exposed on the photoresist layer depending on the distance between the photoresist and the photolithography mask is that the enlarged image of the mask surface resulting from the divergence of the beam is counteracted.
  • the exposure of the photoresist by imaging a photolithography mask using a diverging beam allows the use of the exposure machines known from semiconductor technology and readily available. This has the advantage that these exposure machines can expose a large area of up to 20 cm x 20 cm enables simultaneous exposure of several small, non-planar surfaces. On the other hand, the exposure machines have the advantage that they are relatively inexpensive compared to synchrotron radiation or laser radiation.
  • This method also has the advantage that the enlarged image of the mask surface resulting from the use of a diverging beam can be at least partially corrected.
  • the method according to the invention can be used particularly advantageously for the production of conductive structures, a beam with a divergence angle ⁇ being used, and for exposing an area on the photoresist layer that is at the location of the distance d
  • the method according to the invention can advantageously be used to produce an electrically conductive structure on a surface of a body belonging to its lateral surface, a body having a longitudinal axis, a lateral surface and an end face being used and the body being oriented during the exposure so that at least half of the lateral surface can be exposed.
  • Such a method has the advantage that, for example, a coil body can be used as the body.
  • the orientation of the body during exposure makes it possible to cover the entire surface of the body with two to detect clearing steps from opposite sides.
  • the body is oriented during the exposure in such a way that the flat surfaces to be exposed belonging to the lateral surface enclose an angle of at least 40 ° with the beam direction of the beam bundle used.
  • This method has the advantage that it avoids an extremely flat angle of incidence of the radiation beam onto the photoresist, which would otherwise result in a greatly varying varnish thickness to be effectively exposed.
  • Body in the form of a cuboid is used, the abutting edges between the lateral surfaces belonging to the lateral surface are rounded.
  • a body with a lateral surface containing flat side surfaces has the advantage that a linear correction of the varying distance between the photoresist layer and the photolithography mask is sufficient at least on the flat side surfaces.
  • Such a linear correction of the mask design is easy to carry out since, for example, a rectangle to be exposed on the photoresist layer in the photolithography mask requires a mask surface in the form of a trapezoid.
  • the rounded abutting edges also have the advantage that cracks in the photoresist layer, such as occur preferably on sharp edges, can be largely avoided.
  • the method can advantageously be carried out in such a way that the body is exposed from two sides in such a way that a conductor track is formed as the electrically conductive structure, which runs at least once around the longitudinal axis of the body. As a result, coils can be produced in a simple manner with the aid of the method according to the invention.
  • a body is used in the method, which is suspended on its end face by means of a fastening web on a flat substrate. Hanging the body on a substrate enables the use of miniaturized bodies for the production of correspondingly small coils, the suspension on the substrate making it easier to handle such a small body.
  • a substrate which comprises several identical bodies suspended from it and if the method steps according to the invention are carried out simultaneously with several bodies. Such a procedure enables the implementation of a "batch process" in which several coils can be manufactured at the same time.
  • Polyimide which is structured by means of a laser can advantageously be used as the substrate.
  • the structuring by means of the laser particularly affects that Forming the bodies from a plate-shaped base substrate.
  • the advantage of polyimide is that, due to its permeability, it is well suited as a coil former and that it is also readily available and inexpensive to obtain.
  • an injection molded plastic with high temperature resistance z. B. liquid crystalline polymers or polyether ether ketone, can be used, both of which can be produced by an easy to carry out and inexpensive injection molding process in the form of a substrate with attached bodies.
  • All of the substrate materials mentioned are plastics which have the advantage that they have a high service temperature, as is required for soldering processes which take place at temperatures> 300 ° C.
  • the invention provides the use of the described method for the production of miniaturized
  • Figure 1 shows an example of the implementation of the method according to the invention on the non-planar surface of a body in a schematic cross section.
  • FIG. 2 shows a mask area 5, which is reduced compared to an area 7 to be exposed.
  • FIGS. 3A and 3B show a body with fastening webs used in the exemplary implementation of the method according to the invention in plan view and in side view.
  • Figure 4 shows several bodies according to Figure 3A, which are arranged in a frame in plan view.
  • Figure 5 shows a plurality of frames arranged in a substrate according to Figure 4 in plan view.
  • 6A to 6F show the flat part of a non-planar surface of a body according to FIG. 1 during the production of an electrically conductive structure according to the method according to the invention in each case after the completion of individual method steps in a schematic longitudinal section.
  • FIGS. 7 to 9 show electrical measurement data of coils produced by the method according to the invention.
  • FIG. 1 shows a body 8 with a non-planar surface 1, on which a photoresist layer 2 is electrochemically deposited.
  • a photolithography mask 4 with transparent mask surfaces is imaged on the photoresist layer 2 by means of a beam 6, which has a divergence angle ⁇ .
  • the divergence angle ⁇ applies not only in the drawn plane, but also in the plane perpendicular to it. Due to the varying distance d between the photoresist layer 2 and the photolithography mask 4, it is necessary to reduce the mask areas on the photolithography mask 4 compared to the areas to be exposed on the photoresist layer 2. This procedure is shown in Figure 2 as a top view of Figure 1.
  • a surface 7 in the form of a rectangle to be exposed on the upper side of the body 8 requires a corresponding reduction in the size of the mask surface 5, the width of which becomes smaller towards the outside, ie with increasing distance d.
  • the enlarged image of the mask surface 5 resulting from the divergence of the beam bundle 6 used can be compensated, so that the desired surface 7 to be exposed is finally achieved.
  • FIG. 3 shows the bodies 8 used as coil formers, which have the shape of cuboids and have a longitudinal axis 9.
  • the lateral surface 10 of the cuboid contains four rectangles that meet at an angle of 90 °.
  • the butt edges are rounded with a radius of curvature of 70 ⁇ m.
  • the bodies 8 used have a length of 1 mm and a width of 650 ⁇ m, measured in the diagonal direction.
  • the frames 14 are in turn combined to form the substrate 12 shown in FIG. 5, the frames 14 being arranged in a honeycomb structure to increase the mechanical stability of the substrate 12.
  • a polyimide which is questionable with all process steps is selected as substrate material, for example Cyrlex CL 3000 HN from the company DU PONT. Since the starting metallization described below is the only interface between the substrate and the manufacturing process, the process can also be carried out all similar materials can be used on which the start metallization can be deposited with sufficient adhesion.
  • the substrates are made by laser ablation from 730 ⁇ m thick foils and have a size of 3 "x 3" x 730 ⁇ m.
  • FIG. 5 is merely a schematic illustration, in particular as far as the number of frames 14 is concerned.
  • the substrate 12 used in this example contains 176 unit cells of the size 5 mm x 5 mm. Four of these unit cells are used as alignment marks 17, as are required for the double-sided photolithography process.
  • FIGS. 6A to 6F show the surface of a body 8 in a schematic longitudinal section in each case after carrying out individual process steps which are carried out to produce a coil with the body 8 as the coil body.
  • FIG. 6A shows a starting metallization on the surface of the body 8.
  • FIG. 6B shows an already structured photoresist layer 2 on the starting metallization 15.
  • FIG. 6C shows the structures of the photoresist layer 2 filled with a conductive material 3.
  • the conductive material 3 can be electrodeposited Be copper.
  • FIG. 6D shows the body 8 after removal of the photoresist layer 2.
  • FIG. 6E shows the body 8 after etching back the starting metallization 15.
  • FIG. 6F shows the body 8 after a protective passivation 16 has been applied.
  • a standard process for the chemical metallization of plastics is known, an approximately 50 nm thick metal Layer is chemically deposited using palladium nucleation and subsequent copper link.
  • the 50 nm thick metal layer must be reinforced to a thickness of 200 to 300 nm, since otherwise the lacquer will not deposit sufficiently homogeneously.
  • a 200 nm thick titanium layer is deposited on the substrate by means of DC sputtering. This layer serves as an adhesion promoter.
  • the actual so-called seed layer for the photoresist and the electroplating a 200 nm thick copper layer, is deposited thereon by means of thermal evaporation. This metal system has proven to be just as suitable as the chemically deposited copper layer.
  • the layer thickness of the starting metallization should be more than 200 nm, so that on the one hand one can work with higher current densities in the electrochemical processes and on the other hand the photoresist is deposited with sufficient homogeneity. In addition, thicker layers also improve the coverage of the side edges.
  • the electrodepositable photoresist of the EAGLE 2100 ED type from Shipley is used.
  • conventional coating techniques such as spin coating, dipping or spraying, insufficient results are achieved with regard to homogeneity.
  • the photoresist is deposited electrochemically at a temperature of up to 35 ° C.
  • Stainless steel is used as the anode material, the area ratio of cathode to anode being approximately 1.
  • two symmetrical anodes are used at a distance of 10 cm from the front and back of the substrate and the electrolyte is continuously stirred.
  • the deposition current is 300 mA, which can be varied over a wide range and is ultimately limited by the current carrying capacity of the starting metallization.
  • the separation process itself only takes about 30 seconds.
  • the photoresist Since the photoresist is insulating, the voltage between the cathode and anode increases exponentially with the thickness of the lacquer during the deposition process. To prevent electrolytic decomposition of the photoresist, the voltage is limited to 180 V and the electrolyte is separated from the power source after a current minimum of about 1-5 mA has been reached. For this reason, in contrast to galvanic metal deposition, it is not possible to achieve any layer thickness. This insulating behavior also means the strength of the paint or the deposition process, since it naturally leads to a homogeneous layer thickness. The varnish always attaches preferentially to the points with the smallest photoresist thickness, since the field line gradient is greatest there.
  • a softbake of 10-20 minutes at 105 ° C in a convection oven is suitable for planar substrates.
  • the softbake expels water from the paint and improves adhesion to the substrate. Due to the loss of water, however, the paint contracts, which on sharp edges leads to the paint retracting into areas with minimal surface curvature in order to minimize its own surface tension. This proves to be particularly problematic when covering the coil side edges.
  • a light beam diverges that falls through a gap on the mask Since the optics of the exposure machine used do not provide a flat wavefront at the location of the mask, a light beam diverges that falls through a gap on the mask.
  • the light beam divergence ⁇ is approximately 1 ° to 3 °.
  • the value K (b - ⁇ ) / b is the compensation factor.
  • the light beam divergence could be compensated well with a K of 75%.
  • the photoresist is developed in the developer bath offered by the manufacturer at a temperature of 40 ⁇ 2 ° C. Since the free-standing lacquer structures are very sensitive to mechanical stress, substrate movements must be carried out very gently and carefully both in the developer bath and during the subsequent development stop in deionized water.
  • the substrates are not dried after the development stop but are immediately electroplated. An additional cleaning step before the galvanic copper deposition is not necessary.
  • two symmetrical anodes (effective area: 5 cm x 10 cm) are used at a distance of 10 cm from the substrate.
  • nitrogen is continuously blown in to ensure sufficient ion transport and ion concentration compensation.
  • the copper is deposited at an electrolyte temperature of 22 ° C and a current density of 20 mA / cm 2 .
  • the separator rate averaged over the wafer is about 0.4 ⁇ m / min, but is lower by a factor of 3 in the area of the small winding structures. Since the structure sizes on a bobbin are almost the same, a relatively homogeneous deposition rate of 0.1 - 0.2 ⁇ m / min is achieved on the bobbins.
  • the photoresist structures can largely be removed using the MP 1165 remover from Micro Resist Technology. Detachment can be accelerated if the remover is heated to 50 ° C. There are a number of other organic removers that can be used here. The organic remover is ideal because it does not attack the copper of the conductor tracks.
  • the seed layer of the starting metallization is removed in an electropolishing step. This has the advantage that the surface of the Copper turns is polished.
  • the substrate is polished for 30 seconds at a current of 9.0 A.
  • the 200 nm thick titanium layer can be etched in a 1% hydrofluoric acid solution. This does not attack the copper turns or the polyimide, which is why this process is not critical. The reaction starts after about 1 min with vigorous evolution of gas when the natural titanium oxide (1 nm) has been etched. The titanium layer is completely removed after about 3 minutes.
  • the chemically deposited starting metallization can be completely removed in about 10 seconds in a solution of sulfuric acid (10% by volume) and hydrogen peroxide (1% by volume).
  • the coils should be protected either with a photosensitive polyimide or with the negative coating SU8 known in microsystem technology.
  • the protective passivation can thus be deposited over the entire surface of the substrate and then opened via a further photolithography step at the contact points or end faces.
  • the inductive values apply at 100 MHz.
  • Figure 7 shows the electrical resistance of the four coils.
  • the DC resistance is approximately 0.5 ⁇ for all coils. From a frequency of one GHz, the resistance begins to increase drastically.
  • Measurement curve 72 shows the resistance for coil 11, measurement curve 73 the resistance for coil 08, measurement curve 74 the resistance for coil 07 and finally measurement curve 75 the resistance for coil 06.
  • FIG. 8 shows the measured inductance of the coils with the inductance values at the typical measuring frequency of 100 MHz.
  • Measurement curve 82 shows the inductance for coil 11
  • measurement curve 83 the inductance for coil 08
  • measurement curve 84 the inductance for coil 07
  • measurement curve 85 the inductance for coil 06.
  • Another important parameter of an inductance is its quality, which is calculated from the quotient of the imaginary part to the real part of the complex impedance.
  • FIG. 9 shows the grades of the coils produced using the method described above.
  • Curve 91 shows the quality for coil 11
  • curve 93 the quality for coils 07 and 06, which cannot be distinguished from one another on the selected scale
  • curve 92 shows the quality of coil 08.
  • electrochemical or chemical processes are used for the deposition of the photoresist layer and advantageously also for the starting metallization.
  • advantages in terms of layer homogeneity are achieved on three-dimensional surfaces, in particular on surfaces with edges, compared to directed processes such as sputtering or vapor deposition.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Materials For Photolithography (AREA)
  • Physical Vapour Deposition (AREA)
  • Manufacturing Of Printed Wiring (AREA)
EP01964918A 2000-09-12 2001-08-17 Verfahren zur herstellung einer elektrisch leitfähigen struktur auf einer nichtplanen oberfläche und verwendung des verfahrens Withdrawn EP1317875A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10045072 2000-09-12
DE10045072A DE10045072A1 (de) 2000-09-12 2000-09-12 Verfahren zur Herstellung einer elektrisch leitfähigen Struktur auf einer nichtplanen Oberfläche und Verwendung des Verfahrens
PCT/DE2001/003166 WO2002023961A1 (de) 2000-09-12 2001-08-17 Verfahren zur herstellung einer elektrisch leitfähigen struktur auf einer nichtplanen oberfläche und verwendung des verfahrens

Publications (1)

Publication Number Publication Date
EP1317875A1 true EP1317875A1 (de) 2003-06-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP01964918A Withdrawn EP1317875A1 (de) 2000-09-12 2001-08-17 Verfahren zur herstellung einer elektrisch leitfähigen struktur auf einer nichtplanen oberfläche und verwendung des verfahrens

Country Status (7)

Country Link
US (1) US6998222B2 (zh)
EP (1) EP1317875A1 (zh)
JP (1) JP2004509455A (zh)
CN (1) CN1283133C (zh)
AU (1) AU2001285710A1 (zh)
DE (1) DE10045072A1 (zh)
WO (1) WO2002023961A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI658483B (zh) * 2016-04-08 2019-05-01 許銘案 充電線圈及其製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61247090A (ja) * 1985-04-24 1986-11-04 日本ペイント株式会社 半田スル−ホ−ルを有する回路板の製造方法
JPS63220249A (ja) 1987-03-10 1988-09-13 Japan Radio Co Ltd 曲率面における回路パタ−ンの形成方法
US4800836A (en) * 1987-03-27 1989-01-31 Kabushiki Kaisha Toshiba Resist coating apparatus
US5004672A (en) * 1989-07-10 1991-04-02 Shipley Company Inc. Electrophoretic method for applying photoresist to three dimensional circuit board substrate
JPH0476985A (ja) * 1990-07-18 1992-03-11 Cmk Corp プリント配線板の製造法
JPH05247386A (ja) * 1991-11-27 1993-09-24 Hitachi Chem Co Ltd ポジ型感光性アニオン電着塗料樹脂組成物、ポジ型感光性アニオン電着塗料、電着塗装浴、電着塗装法及びプリント回路板の製造法
US5323047A (en) * 1992-01-31 1994-06-21 Sgs-Thomson Microelectronics, Inc. Structure formed by a method of patterning a submicron semiconductor layer
JP3202839B2 (ja) 1993-01-26 2001-08-27 松下電工株式会社 立体回路板の製造方法
JPH07273432A (ja) 1994-03-30 1995-10-20 Kansai Paint Co Ltd プリント配線板の製造法
DE69518708T2 (de) * 1994-04-15 2001-06-07 Koninkl Philips Electronics Nv Verfahren zur herstellung einer vorrichtung durch direktes bestrahlen von einigen teilen der oberflaeche der vorrichtung durch eine maske und durch indirektes bestrahlen von anderen teilen durch die maske via einer reflektierenden oberflaeche unter herstellung eines musters
GB2291216B (en) * 1994-06-30 1998-01-07 Matsushita Electric Works Ltd Method of manufacturing a printed circuit board
CN1086101C (zh) 1994-07-08 2002-06-05 松下电工株式会社 一种制造印刷电路板的方法
JPH11218938A (ja) 1998-01-30 1999-08-10 Hitachi Cable Ltd 立体成形品の固定治具
DE19817852B4 (de) * 1998-04-22 2009-04-16 Theodor Dr. Doll Nutzenfertigung von Induktivitäten mit Mikrotechniken

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0223961A1 *

Also Published As

Publication number Publication date
JP2004509455A (ja) 2004-03-25
US6998222B2 (en) 2006-02-14
DE10045072A1 (de) 2002-04-04
US20040096781A1 (en) 2004-05-20
AU2001285710A1 (en) 2002-03-26
WO2002023961A1 (de) 2002-03-21
CN1283133C (zh) 2006-11-01
CN1456032A (zh) 2003-11-12

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