EP1297579A1 - Puce a semi-conducteur emettant un rayonnement, et son procede de realisation - Google Patents

Puce a semi-conducteur emettant un rayonnement, et son procede de realisation

Info

Publication number
EP1297579A1
EP1297579A1 EP01943138A EP01943138A EP1297579A1 EP 1297579 A1 EP1297579 A1 EP 1297579A1 EP 01943138 A EP01943138 A EP 01943138A EP 01943138 A EP01943138 A EP 01943138A EP 1297579 A1 EP1297579 A1 EP 1297579A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor chip
substrate
active layer
radiation
emitting semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01943138A
Other languages
German (de)
English (en)
Inventor
Dominik Eisert
Volker HÄRLE
Frank Kühn
Ulrich Zehnder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP1297579A1 publication Critical patent/EP1297579A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the invention relates to a radiation-emitting semiconductor chip having an active layer and a multiplicity of side surfaces which laterally delimit the extension of the active layer.
  • the invention further relates to a method for producing a radiation-emitting semiconductor chip, in which an active layer is first formed above a surface of a substrate and in which the substrate is then separated into semiconductor chips together with the active layer.
  • a radiation-emitting semiconductor chip is known from JP 10-32 69 10 A, which has the shape of a truncated pyramid.
  • the active layer of the known semiconductor chip is located in a central region of the semiconductor chip. Crystalline layers are located above the active layer.
  • the base area running parallel to the active layer is diamond-shaped. The special design of the base area facilitates the light emission from the semiconductor chip. After a few total reflections, the light rays hit an outer surface at an angle that is smaller than the critical angle. Due to the special design of the truncated pyramid-shaped semiconductor chip, the efficiency when decoupling the photons is relatively high.
  • a disadvantage of the known semiconductor chip is that the cross-sectional area varies between the base area used for attaching an electrode and an opposite top side, which is also provided with an electrode. Due to the decreasing cross section of the base Semiconductor chips make it difficult to dissipate heat. In addition, the current flow is hindered by the reduced cross section, so that the ohmic resistance increases locally in the semiconductor chip. Both together lead to a locally different, increased thermal load on the semiconductor chip. The resulting voltages in the semiconductor chip, however, affect the life of the semiconductor chip. In addition, the conversion efficiency of the active layer is reduced by the increased thermal load.
  • the object of the invention is to create a semiconductor chip with good optical coupling and uniform thermal stress.
  • the semiconductor chip has at least two parallelogram-shaped side surfaces provided with an acute angle.
  • the prism-shaped design of the semiconductor chip with two tilted parallelogram-shaped side faces ensures on the one hand that the light emanating from the active layer can leave the semiconductor chip with a small number of reflections.
  • the light rays that leave the active layer in the direction of the base surface largely hit the beveled side surfaces and are reflected on an opposite side surface, where they strike at an angle that is smaller than the critical angle for the total reflection.
  • the semiconductor chip has a uniform cross section, so that the thermal load across the semiconductor chip is homogeneous. This effectively prevents voltages in the semiconductor chip.
  • the semiconductor chip according to the invention therefore has not only good optical coupling but also a homogeneous and low thermal load.
  • the invention is also based on the object of creating a method for producing the semiconductor chip.
  • This object is achieved according to the invention in that the semiconductor chips are separated along a separating surface which runs obliquely to the surface.
  • FIG. 1 shows a perspective view of a semiconductor chip
  • FIG. 2 shows a top view of the semiconductor chip from FIG. 1;
  • FIG. 3 shows a side view of the semiconductor chip from FIG. 1;
  • FIG. 4 shows a cross section with possible light paths in the semiconductor chip from FIG. 1;
  • FIG. 5 is a diagram in which the degree of decoupling as a function of different base angles of the geometric shape of the semiconductor chip
  • FIG. 1 shows a semiconductor chip 1 which has a substrate 2.
  • the substrate 2 is prism-shaped and, in addition to a base area 3 and an upper side 4, has side areas 5, each of which has the shape of a tilted parallelogram.
  • a layer sequence 6 with an active layer, on which a circular electrode 7 is arranged, is applied to the upper side 4 of the substrate 2.
  • Another electrode, which is not shown in FIG. 1, is located on the base 3 of the substrate 2.
  • FIG. 2 shows a cross section through the substrate 2 parallel to the base 3 and to the top 4.
  • the cross section like the base area 3, is designed as a tilted parallelogram with an acute angle ⁇ .
  • the side faces 5 are also formed as tilted parallelograms with an acute angle ⁇ .
  • the formation of the substrate 2 as a parallelepiped with parallelogram-shaped side surfaces which have an acute angle is advantageous for the coupling out of light.
  • This is clear from Figure 4.
  • a point-shaped light source 8 within the substrate 2. If, for example, a light beam 9 occurs at an angle a to the surface normal on the upper side 4, the angle ⁇ being greater than the angle of the total reflection a c , it becomes at the Top 4 reflected.
  • the angle of incidence oi x is also greater than the critical angle for total reflection a c .
  • the light beam 9 is therefore also reflected on the side surface 5.
  • the angle of incidence is smaller than the critical angle o c for total reflection.
  • the influence of the horizontal base angle ⁇ is less than that of the vertical base angle ⁇ .
  • the base area 3 of the substrate 2 was assumed to be 50% absorbent. This is actually the case when the semiconductor chip 1 is mounted with a silver conductive adhesive on a carrier. As a result, the light rays reflected back into the substrate 2 are weakened. It is therefore advantageous if the base area 3 is designed to be reflective.
  • the layer sequence 6 is produced on the basis of AlInGaN or, for example, AlGalnP with transparent window layers made of GaP.
  • Materials such as sapphire, gallium nitride, zinc oxide, diamond or quartz glass can also be used for the substrate 2 instead of silicon carbide.
  • the formation of the substrate as a parallelepiped with tilted parallelograms as side surfaces also has the advantage that the cross section of the substrate 2 remains the same from the base surface 3 to the top 4. As a result, the heat can be dissipated evenly from the layer sequence 6.
  • the ohmic resistance of the substrate 2 is also the same from the top 4 to the base 3. As a result, the voltage drop across the substrate 2 remains low and is evenly distributed. Overall, the semiconductor chip 1 is therefore subjected to uniform thermal stress. There are therefore no voltages in the semiconductor chip 1.
  • the current can flow freely between the active layer and the electrode arranged on the base area 3 owing to the uniform cross section of the substrate 2.
  • the semiconductor chip 1 is therefore also distinguished by a low forward voltage.
  • the substrate 2 is first provided with the layer sequence 6. Subsequently, the substrate 2 can be sawn with the aid of a sawing device with an inclined saw blade. With such a sawing method there is no loss of active area and of the substrate. This is particularly advantageous if the production of the substrate 2 and the growth of the layer sequence 6 are associated with high costs.
  • the semiconductor chips presented here are particularly suitable for producing luminescent diodes in the spectral range mentioned, from the ultraviolet to the infrared.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne une puce à semi-conducteur (1) comprenant un substrat (2) qui se présente sous la forme d'un parallélépipède dont les surfaces latérales (5) sont des parallélogrammes inclinés. La puce à semi-conducteur (1) présente un rendement d'émission élevé et une charge thermique homogène.
EP01943138A 2000-07-06 2001-05-22 Puce a semi-conducteur emettant un rayonnement, et son procede de realisation Withdrawn EP1297579A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10032838 2000-07-06
DE10032838.5A DE10032838B4 (de) 2000-07-06 2000-07-06 Strahlung emittierender Halbleiterchip und Verfahren zu dessen Herstellung
PCT/DE2001/001952 WO2002003477A1 (fr) 2000-07-06 2001-05-22 Puce a semi-conducteur emettant un rayonnement, et son procede de realisation

Publications (1)

Publication Number Publication Date
EP1297579A1 true EP1297579A1 (fr) 2003-04-02

Family

ID=7647987

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01943138A Withdrawn EP1297579A1 (fr) 2000-07-06 2001-05-22 Puce a semi-conducteur emettant un rayonnement, et son procede de realisation

Country Status (6)

Country Link
US (2) US6858881B2 (fr)
EP (1) EP1297579A1 (fr)
JP (1) JP2004503094A (fr)
DE (1) DE10032838B4 (fr)
TW (1) TWI229459B (fr)
WO (1) WO2002003477A1 (fr)

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Publication number Priority date Publication date Assignee Title
DE10139723A1 (de) * 2001-08-13 2003-03-13 Osram Opto Semiconductors Gmbh Strahlungsemittierender Chip und strahlungsemittierendes Bauelement
JP3705791B2 (ja) * 2002-03-14 2005-10-12 株式会社東芝 半導体発光素子および半導体発光装置
JP4689597B2 (ja) * 2003-03-28 2011-05-25 レセプター バイオロジックス インク． ガストリンホルモン免疫アッセイ
US7033912B2 (en) 2004-01-22 2006-04-25 Cree, Inc. Silicon carbide on diamond substrates and related devices and methods
US7612390B2 (en) * 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
US8294166B2 (en) 2006-12-11 2012-10-23 The Regents Of The University Of California Transparent light emitting diodes
US7294324B2 (en) * 2004-09-21 2007-11-13 Cree, Inc. Low basal plane dislocation bulk grown SiC wafers
US7422634B2 (en) * 2005-04-07 2008-09-09 Cree, Inc. Three inch silicon carbide wafer with low warp, bow, and TTV
US7709269B2 (en) 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US7592211B2 (en) * 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US20120313213A1 (en) * 2011-06-07 2012-12-13 Raytheon Company Polygon shaped power amplifier chips
KR101189014B1 (ko) 2011-06-14 2012-10-08 서울옵토디바이스주식회사 반도체 발광 소자, 그 제조 방법 및 이를 포함하는 반도체 발광 소자 패키지
JP5995563B2 (ja) * 2012-07-11 2016-09-21 株式会社ディスコ 光デバイスの加工方法
CN103811613A (zh) * 2012-11-15 2014-05-21 展晶科技(深圳)有限公司 发光二极管磊晶结构
TWD161897S (zh) 2013-02-08 2014-07-21 晶元光電股份有限公司 發光二極體之部分
USD847102S1 (en) 2013-02-08 2019-04-30 Epistar Corporation Light emitting diode
US11037911B2 (en) * 2017-12-27 2021-06-15 Nichia Corporation Light emitting device
US11592166B2 (en) 2020-05-12 2023-02-28 Feit Electric Company, Inc. Light emitting device having improved illumination and manufacturing flexibility
US11876042B2 (en) 2020-08-03 2024-01-16 Feit Electric Company, Inc. Omnidirectional flexible light emitting device

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US5087949A (en) 1989-06-27 1992-02-11 Hewlett-Packard Company Light-emitting diode with diagonal faces
EP0405757A3 (en) 1989-06-27 1991-01-30 Hewlett-Packard Company High efficiency light-emitting diode
JPH0478174A (ja) * 1990-07-19 1992-03-12 Nec Corp 半導体発光素子
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
JP3557011B2 (ja) * 1995-03-30 2004-08-25 株式会社東芝 半導体発光素子、及びその製造方法
JP3176856B2 (ja) * 1995-12-14 2001-06-18 沖電気工業株式会社 端面発光型ｌｅｄ、端面発光型ｌｅｄアレイ、光源装置及びそれらの製造方法
JP3504079B2 (ja) * 1996-08-31 2004-03-08 株式会社東芝 半導体発光ダイオード素子の製造方法
JPH10326910A (ja) * 1997-05-19 1998-12-08 Song-Jae Lee 発光ダイオードとこれを適用した発光ダイオードアレイランプ
US6229160B1 (en) 1997-06-03 2001-05-08 Lumileds Lighting, U.S., Llc Light extraction from a semiconductor light-emitting device via chip shaping
JPH11340576A (ja) * 1998-05-28 1999-12-10 Sumitomo Electric Ind Ltd 窒化ガリウム系半導体デバイス
US20030137031A1 (en) * 2002-01-23 2003-07-24 Tai-Fa Young Semiconductor device having a die with a rhombic shape

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See also references of WO0203477A1 *

Also Published As

Publication number Publication date
DE10032838A1 (de) 2002-01-24
US6972212B2 (en) 2005-12-06
US20050042843A1 (en) 2005-02-24
TWI229459B (en) 2005-03-11
US20030107045A1 (en) 2003-06-12
WO2002003477A1 (fr) 2002-01-10
US6858881B2 (en) 2005-02-22
JP2004503094A (ja) 2004-01-29
DE10032838B4 (de) 2015-08-20

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