EP1289020B1 - A lateral overflow drain, antiblooming structure for CCD devices having improved breakdown voltage - Google Patents

A lateral overflow drain, antiblooming structure for CCD devices having improved breakdown voltage Download PDF

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Publication number
EP1289020B1
EP1289020B1 EP02078413A EP02078413A EP1289020B1 EP 1289020 B1 EP1289020 B1 EP 1289020B1 EP 02078413 A EP02078413 A EP 02078413A EP 02078413 A EP02078413 A EP 02078413A EP 1289020 B1 EP1289020 B1 EP 1289020B1
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EP
European Patent Office
Prior art keywords
overflow drain
lateral overflow
image sensor
type
lod
Prior art date
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EP02078413A
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German (de)
English (en)
French (fr)
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EP1289020A3 (en
EP1289020A2 (en
Inventor
Edmund K. Banghart
Eric Gordon Stevens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
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Eastman Kodak Co
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Publication date
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Publication of EP1289020A2 publication Critical patent/EP1289020A2/en
Publication of EP1289020A3 publication Critical patent/EP1289020A3/en
Application granted granted Critical
Publication of EP1289020B1 publication Critical patent/EP1289020B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/15—Charge-coupled device [CCD] image sensors
    • H10F39/158—Charge-coupled device [CCD] image sensors having arrangements for blooming suppression

Definitions

  • the invention relates generally to the field of image sensors and, more particularly, to such image sensors having a lateral overflow drain substantially underneath a thick field dielectric.
  • CMOS image sensors In full frame type, charge-coupled device (CCD) image sensors, lateral overflow drain (LOD) structures are formed along with vertical CCD shift registers to provide means for conducting excess electrical charges away from the imaging area. Such removal is necessary to prevent the image defect known as blooming in the CCD pixels, in which the column becomes either partially or completely flooded with charge thereby destroying the intended image.
  • Fig. 1 an illustration of a conventional lateral overflow drain structure is shown drawn at the center of two adjacent columns.
  • an implant consisting of n-type impurities is made through the thin gate dielectric at the edge of the device active area and is aligned to a region of thick field oxidation that has been grown to provide electrical isolation between the vertical CCD columns of the imaging area.
  • Electrostatic isolation is also provided by a p-type implant made under the field oxidation.
  • photogenerated electrical charge is collected in the implanted n-type buried channel regions.
  • a region of the buried channel is compensated with p-type impurities to form an electrostatic potential barrier to the LOD.
  • excess electrical charges that would normally overfill the buried channel regions and bloom up and down the columns, instead find an outlet over the LOD barrier into the n-type LOD drain where they can be safely conducted away from the imaging area.
  • a plot of the electrostatic potential, or channel potential, versus position for the structure under typical operational condition appears in Fig. 2 .
  • the breakdown condition ordinarily is produced as the applied bias on the device electrodes is increased. It should be evident to those skilled in the art that the conditions for avalanche breakdown are most severe for the accumulation mode of operation, where the gate electrodes are typically placed at -10 volts. Because the lateral overflow drain is usually biased at 10 volts, a total of 20 volts is placed across the thin gate dielectric, with the highest electric field occurring at the silicon surface above the center of the lateral overflow drain implant. A representative plot of the surface electric field strength versus position is included in Fig. 1 .
  • the present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to the present invention, the invention resides in an image sensor having an anti-blooming structure as defined in claim 1.
  • the present invention has the advantage of placing the lateral overflow drain underneath a thick dielectric layer so that a substantially lower electric field results at the silicon surface which permits a greater amount of n-type impurities to be used for providing enhanced conductance.
  • thick field dielectric means a field dielectric layer that is thicker than the active area dielectric.
  • the CCD 10 includes a p-type substrate 20 having a plurality of n-type buried channels 30 for collecting incident light in the form of electrons.
  • a plurality of barriers 40 is disposed in the substrate 20 and defines a maximum energy level for charge collection in the burried channel 30, over which excess photogenerated electrical charges flow.
  • a dielectric 50 is formed (deposited or grown) atop the buried channel 30 and extends over the barrier 40, lateral overflow drain 60 and channel stop 70. Both latter components are described in detail herein below.
  • the dielectric 50 includes a thin, active area dielectric region 80 positioned substantially above the buried channel 30 and barrier 40, and includes a thick dielectric region 90 positioned substantially between the spaced-apart buried channels 30.
  • a gate electrode 100 is disposed atop the entire dielectric 50.
  • the active area dielectric 80 is preferably comprised of either oxide-nitride-oxide (ONO), oxide-nitride (ON), or oxide, and the thick dielectric 90 is preferably comprised of oxide, as this simplifies the manufacturing process.
  • the n-type drain 60 is positioned substantially (either wholly or for the most part) in its entirety beneath a portion of the thick field dielectric 90 for collecting the excess photogenerated electrical charges flowing over the barrier 40.
  • the p-type channel stop 70 is preferably positioned adjacent the lateral overflow drain 60 also substantially in its entirety beneath a portion of the thick field dielectric 90 for forming a boundary for the drain region 60. It is instructive to note that the p-type channel need not be positioned under the thick field dielectric as other positions are also viable.
  • the lateral overflow drain 60 is insulated from the gate electrode 100 by a thick dielectric layer 90 (for example, 3000 to 4000 angstroms of oxide instead of 500 angstroms as in the prior art), a much lower electric field results at the silicon surface.
  • a representative plot of the surface electric field strength versus position is also included in Fig. 3 for the CCD and its antiblooming structure 10 of the present invention and should be compared with the plot in Fig. 1 for the conventional lateral overflow drain structure.
  • the lower electric field means that a greater amount of n-type impurities can be used in the LOD formation, which provides substantial improvements in the conductance when compared with the conventional design.
  • the improved conductance can be used to significantly narrow the LOD width, and therefore permit the design of higher resolution (i.e., smaller pixels) imaging arrays without sacrificing charge capacity in the pixels.
  • the higher breakdown voltages for the new structures could be used to improve device yield by permitting a larger operational range of applied voltages on the gate and LOD electrodes.
  • Another important advantage of the lateral overflow drain structure of the present invention is the preferential use of arsenic impurities rather than phosphorus impurities as the n-type dopant.
  • phosphorus had been favored due to its higher conductance and higher breakdown voltage relative to those of arsenic.
  • the disadvantage of phosphorus is its long diffusion length that causes the LOD barrier potential to be pulled down, thereby reducing the charge capacity.
  • Use of boron co-implanted with the phosphorus, and/or an adjustment in the LOD barrier implant dose, is generally required to counteract the pull-down effect of the phosphorus, adding complexity to the device processing.
  • the potential in the channel stop region likewise, is subject to pull-down by the LOD formed with phosphorus impurities.
  • An LOD under the field dielectric with arsenic impurities diffuses much more slowly than one formed with phosphorus impurities, and therefore exerts much less of an influence on neighboring potentials in the pixel.
  • the use of co-implanted boron impurities to compensate for the presence of the phosphorus impurities is therefore unnecessary, which further improves drain conductivity.
  • the need for adjustment in the barrier implant is also reduced.
  • the use of arsenic for the LOD formation is clearly preferred for pixel scaling efforts intended to improve image resolution.
  • an n-type substrate could be used by using the opposite conductivity types for the various other implants. It is also to be understood that, although the drawings show only one CCD and its corresponding lateral overflow drain, there are a plurality of such CCDs and their corresponding lateral overflow drain, anti-blooming structures.

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
EP02078413A 2001-08-31 2002-08-19 A lateral overflow drain, antiblooming structure for CCD devices having improved breakdown voltage Expired - Lifetime EP1289020B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US945034 1978-09-22
US09/945,034 US6624453B2 (en) 2001-08-31 2001-08-31 Lateral overflow drain, anti-blooming structure for CCD devices having improved breakdown voltage

Publications (3)

Publication Number Publication Date
EP1289020A2 EP1289020A2 (en) 2003-03-05
EP1289020A3 EP1289020A3 (en) 2004-04-21
EP1289020B1 true EP1289020B1 (en) 2009-08-19

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EP02078413A Expired - Lifetime EP1289020B1 (en) 2001-08-31 2002-08-19 A lateral overflow drain, antiblooming structure for CCD devices having improved breakdown voltage

Country Status (4)

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US (1) US6624453B2 (enExample)
EP (1) EP1289020B1 (enExample)
JP (1) JP2003086782A (enExample)
DE (1) DE60233371D1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7899339B2 (en) * 2002-07-30 2011-03-01 Amplification Technologies Inc. High-sensitivity, high-resolution detector devices and arrays
GB2428516A (en) * 2004-03-18 2007-01-31 E2V Tech Uk Ltd Radiation tolerant CCD structure
JP4967237B2 (ja) * 2005-01-28 2012-07-04 パナソニック株式会社 固体撮像装置
US7893981B2 (en) * 2007-02-28 2011-02-22 Eastman Kodak Company Image sensor with variable resolution and sensitivity
JP2009177018A (ja) * 2008-01-25 2009-08-06 Sanyo Electric Co Ltd 固体撮像素子及びその製造方法
US8329499B2 (en) * 2008-12-10 2012-12-11 Truesense Imaging, Inc. Method of forming lateral overflow drain and channel stop regions in image sensors
EP2359402B1 (en) * 2008-12-10 2012-10-24 Truesense Imaging, Inc. Method of fabricating image sensors with lateral overflow drains
JP5243983B2 (ja) * 2009-01-30 2013-07-24 浜松ホトニクス株式会社 電子増倍機能内蔵型の固体撮像素子
US8829637B2 (en) 2011-07-29 2014-09-09 Semiconductor Components Industries, Llc Image sensor with controllable vertically integrated photodetectors using a buried layer
US8946612B2 (en) * 2011-07-29 2015-02-03 Semiconductor Components Industries, Llc Image sensor with controllable vertically integrated photodetectors
US9070611B2 (en) 2011-07-29 2015-06-30 Semiconductor Components Industries, Llc Image sensor with controllable vertically integrated photodetectors
US8847285B2 (en) 2011-09-26 2014-09-30 Semiconductor Components Industries, Llc Depleted charge-multiplying CCD image sensor
US10341590B2 (en) * 2016-08-12 2019-07-02 Semiconductor Components Industries, Llc Methods and apparatus for a CCD image sensor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774557A (en) * 1986-05-15 1988-09-27 General Electric Company Back-illuminated semiconductor imager with charge transfer devices in front surface well structure
US4984047A (en) * 1988-03-21 1991-01-08 Eastman Kodak Company Solid-state image sensor
JP3592772B2 (ja) * 1994-12-19 2004-11-24 株式会社東芝 固体撮像装置
US6608337B2 (en) * 2001-04-12 2003-08-19 Ise Tex, Inc Image sensor with an enhanced near infra-red spectral response and method of making

Also Published As

Publication number Publication date
US6624453B2 (en) 2003-09-23
EP1289020A3 (en) 2004-04-21
EP1289020A2 (en) 2003-03-05
DE60233371D1 (de) 2009-10-01
US20030042510A1 (en) 2003-03-06
JP2003086782A (ja) 2003-03-20

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