Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00349—Creating layers of material on a substrate
  • B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C99/00—Subject matter not provided for in other groups of this subclass
  • B81C99/0075—Manufacture of substrate-free structures
  • B81C99/008—Manufacture of substrate-free structures separating the processed structure from a mother substrate
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/24—Deposition of silicon only
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23C16/511—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using microwave discharges
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2201/00—Manufacture or treatment of microstructural devices or systems
  • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
  • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
  • B81C2201/0102—Surface micromachining
  • B81C2201/0105—Sacrificial layer
  • B81C2201/0109—Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2201/00—Manufacture or treatment of microstructural devices or systems
  • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
  • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
  • B81C2201/0111—Bulk micromachining
  • B81C2201/0115—Porous silicon
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/01—Packaging MEMS
  • B81C2203/0127—Using a carrier for applying a plurality of packaging lids to the system wafer

Definitions

• the present invention is directed to deposited thin films of semiconductors and dielectrics.
• the present invention further relates to the use of these thin films in separation, release, and sacrificial layer applications.
• Separation layer and release layer applications of these thin films include functions for separating materials and structures in fabrication processing for fields such as microelectronics, displays, solar cells, sensors, detectors, opto-electronics, biotechnology, and micro-electromechanical (MEMs) devices and systems.
• Sacrificial layer applications of these thin films include sacrificial film functions for the creation of void regions for uses such as channels, tubes, "air-gaps", and cavities for microfluidics, separation/sorting structures, fuel cells, dielectrics, acoustic structures and optical structures.
• Separation layer approaches are used to physically separate systems of materials into at least two distinct systems.
• the approach is based on the use of some separation material positioned between other materials such that the separation material may be etched, mechanically abraded, or dissolved away leaving at least two, physically separated, distinct groupings of materials.
• Release layers are similarly used; however, in release layer applications the two materials systems are not totally separated.
• the separation or release layer material is often a polymer (e.g., photoresist), silicon dioxide, or polycrystalline silicon (Sang-Gook Kim and Kyu-Ho Hwang, Information Display, 15, 30 (1999).
• electrochemically etched porous silicon has been used as a separation layer for producing silicon on insulator (SOI) wafers for microelectronics applications (T. Yonehara and K. Sakaguchi, Abstract # 438, The Electrochemical Society, Fall Meeting, Oct., 2000, Phoenix, Az.).
• Sacrificial layer approaches are used to create micro-scale and nano-scale void or cavity regions. Such voids or cavities are an enclosed empty space, which may be subsequently filled. Void creation is accomplished by removing a sacrificial material thereby leaving an empty region enclosed by an envelope of one or more materials.
• the size and shape of the void or cavity can be designed for the specific application. The shape may be varied and serve a variety of functions such as a channel, tube, "air-gap", or cavity.
• Commonly used sacrificial layer materials include polymers, silicon dioxide, and poly-crystalline silicon (M.B. Stern, M.W.Geis and J.E.Curtin, J.VacSci.Technol. Vol. B15(6), pp. 2887 (1997) and S. W. Turner and H. G. Craighead, Proc. SPIE Vol.3258, pp.114 (1998)).
• silicon dioxide and deposited poly silicon are probably the most commonly used sacrificial materials (P.J. French, J. Micromech. Microeng. Vol. 6, pp.197 (1996) and S. Sugiyama, O.Tabata, K.Shimaoka and R.Ashahi, IEDM Tech. Dig. pp.127 (1994)) and their etch rate can be relatively very high when they are deposited on an open region.
• a void structure such as, a channel, tube, cavity, or "airgap"
• these materials will, of course, be covered by a cap layer, which forms the "roof of what will become the void region.
• the void or cavity region is then formed by etching away the sacrificial layer material through a window or through holes in or beside the cap layer.
• This window provides etchant access and reaction product exit. Consequently, the etch rate can become very low because the etch rate depends on the transport processes of the etchant solution, of the reaction products, or of both rather than just chemical reaction rate. That is, the removal of the sacrificial layer depends on the access of the etchant to and the removal of the reaction product from the sacrificial layer material as well as chemical etch rate. Consequently, materials that may have fast etch rates when deposited in open regions often have considerably slower etch rates when used as sacrificial layers.
• the substrate-to-substrate or wafer-to-wafer bonding technique creates features in surfaces using standard processes such as etching, milling, embossing, stamping, etc. and then bonds a substrate and capping wafer or substrate, thereby creating nano- or microchannel features.
• this bonding approach is a relatively simple process. However, it requires anodic or direct (fusion) bonding and has the critical disadvantage of needing alignment of top and bottom.
• the second technique is the method based on the use of sacrificial layers. Since it is based on sacrificial layer use, it can produce channel dimensions down to a few nanometers although to date the sacrificial layer removal step has been a relatively complex process (M.J. de Boer, W. Tjerkstra et al., J. of
• the present invention is based on using separation and release layer material and sacrificial material approaches in device fabrication. Specifically, it is based on using a new material for separation, release and sacrificial applications and a new, simple processing flow for separation layer, release layer and sacrificial layer implementation.
• the new materials of the present invention are deposited large material surface to material volume ratio thin films. The large surface to volume ratio insures a large empty region between material (i.e., material volume) regions allowing easy access by etching chemicals and easy reaction product removal. It insures the materials essentially wet very uniformly leading to very uniform attack and removal. In addition, the large surface area assures efficient chemical attack of the material when exposed to removing chemicals.
• the large surface to volume structure also leads to a mechanically weakened material for which mechanical agitation can be helpful in removal or for which gases trapped in this material may be used to enhance removal.
• procedures for separation layer applications and the removal procedure for sacrificial layer applications are more reliable than the other release and removal processes, are faster than other release and sacrificial layer approaches, and allow close process control.
• these novel materials are deposited and, therefore, can be used with a variety of substrates, including, but not limited to, plastics, glasses and metal foils.
• the present invention is directed to a method for processing a substrate comprising the steps of (a) providing the substrate; (b) forming a high surface area to volume ratio material layer over a surface of the substrate; and (c) during subsequent processing of the substrate, removing at least a portion of the high surface area to volume ratio material layer.
• high surface area to volume ratio material layer is deposited over the substrate in step (b).
• the high surface area to volume ratio material layer is a columnar void layer, deposited metal, dielectric, semiconductor or organic material.
• the columnar void layer comprises a plurality of uniform essentially non-contacting basic columnar-like units penetrating a continuous void wherein the units have adjustable regular spacing, adjustable uniform height, and adjustable variable diameter, and the plurality of basic columnar-like units are uniformly orientated and disposed on the substrate.
• the basic columnar-like units are comprised of silicon, germanium, carbon, hydrogen, other inorganics, or mixture thereof.
• the columnar void layer has a thickness of at least 10 nm and is deposited in a vacuum environment of pressure less than atmospheric pressure at a temperature of less than about 250°C.
• the high surface area to volume ratio material layer is formed upon at least one intervening layer located between the high surface area to volume ratio material layer and the substrate.
• the removal of the high surface area to volume ratio material layer in step (c) is conducted by chemical means, physical means or a combination thereof.
• a portion of the substrate may also removed before, while or after removing at least a portion of the high surface area to volume ratio material layer in step (c).
• a portion of the intervening layer between the high surface area to volume ratio material layer and the substrate is also removed.
• the above described method further comprises the step of depositing at least one coating over the high surface area to volume ratio material layer after forming the high surface area to volume ratio material layer over a surface of the substrate in step (b).
• the coating or coatings are either organic or inorganic.
• the above described method further comprises the step of fabricating a device, structure or both over the at least one coating to form a device/coating structure/coating or mixture thereof. Removing of at least a portion of the high surface area to volume ratio material layer in step (c) thereby frees the device/coating structure/coating or mixture thereof from the substrate.
• the method further comprises the step of creating through-holes through the device/coating structure/coating or mixture thereof to remove the high surface area to volume ratio material layer. The through-holes can be created through the substrate, coating or coatings, or both.
• the method may further comprises the step of forming a second coating over the device/coating structure/coating or mixture thereof.
• the first coating, second coating or both act as a substrate thereby carrying the combination comprised of devices and structures, after removal of the high surface area to volume ratio material layer of step (c).
• separating the device/coating structure/coating or mixture thereof from the substrate thereafter further comprising the step of using the carrier substrate to dispose the separated device/coating structure/coating or mixture thereof over a second substrate.
• the step of removing a portion of the high surface area to volume ratio material layer in step (c) of the above described method comprises a step of selectively etching the high surface area to volume ratio material layer, such that a portion thereof is retained.
• the method further comprises the step of forming at least one layer over the retained portion of the high surface area to volume ratio material layer.
• Another further step comprises creating through-holes to access the high surface area to volume ratio material layer.
• the step of removing the retained portion of the high surface area to volume ratio material layer uses the through-holes to produce a cavity structure.
• a step of depositing at least one further layer over the at least one layer, thereby blocking the through-holes may follow.
• the step of providing a substrate in step (a) of the above described method comprises the step of: depositing a stencil layer on the substrate; patterning the stencil layer and selectively removing a portion of the stencil layer thereby leaving an exposed portion of the substrate and at least one retained portion of the stencil layer.
• the exposed portion of the substrate may be subsequently etched using the stencil layer as a mask.
• the step of forming a high surface area to volume ratio material layer comprises forming the high surface area to volume ratio material layer upon the exposed surface of the substrate and on the at least one retained portion of the stencil layer, further comprising the step of lifting off the stencil layer, thereby also removing a portion of the high surface area to volume ratio material layer deposited thereon.
• a further step is depositing a second layer over the substrate and the high surface area to volume ratio material layer, through-holes are then created through the second layer.
• step (c) After removal of the columnar void layer in step (c) through the created through-holes to produce a cavity structure, thereafter further comprising the step of adding a gas or liquid in the cavity structure, thereafter further comprising the step of depositing a layer that blocks the through-holes and seals the cavity structure.
• the step of providing a substrate comprises the step of depositing a material system over the substrate; and selectively removing portions of the deposited material system retaining a portion of the material system.
• the step of forming the high surface area to volume ratio material layer over the substrate comprises the step of forming the high surface area to volume ratio material layer over the substrate and the retained material, and further comprising the step of removing a portion of the high surface area to volume ratio material layer to expose a portion of the retained material.
• the method further comprises the step of depositing additional material over the high surface area to volume ratio material layer and exposed portions of the previously deposited material, so that a portion the additional material contacts an exposed portion of the previously deposited material.
• the present invention is also directed to a method of transferring a system of materials from a substrate comprising (a) forming a high surface area to volume ratio material layer onto a substrate; (b) forming at least one coating over the high surface area to volume ratio material layer; (c) fabricating a device, structure or both over the at least one coating to form a device/coating structure/coating or mixture thereof; and (d) removing the high surface area to volume ratio material layer thereby separating the system from the substrate.
• the high surface area to volume ratio material layer is a columnar void layer.
• the columnar void layer is deposited.
• the columnar void layer is a nano-scale composition comprising (a) a plurality of uniform essentially non-contacting basic columnar-like units penetrating a continuous void wherein the units have adjustable regular spacing, adjustable uniform height, and adjustable variable diameter, and (b) the plurality of basic columnar-like units are uniformly orientated and disposed on the substrate.
• the first substrate is rigid.
• the first substrate is selected from the group consisting of: silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, insulator materials, and mixtures thereof.
• forming at least one coating over the high surface area to volume ratio material layer in step (b) is performed by a technique selected from the group consisting of: deposited, applied, spin-coat, screen, printed, sputtered, evaporated, and spread.
• the at least one coating is organic or inorganic and is preferably a material selected from the group consisting of: chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferroelectrics, metals, pyroelectrics, biological materials and semiconductors.
• the device is a structure selected from the group consisting of: sensors, actuators, electronics, chemical micro-fluidics, circuits, displays, optics, acoustics, solar cells, displays or opto-electronic devices, fuel cells and combinations thereof.
• the above described method further comprises a step of creating through-holes used to remove the high surface area to volume ratio material layer.
• the through-holes are created through at least a layer selected from the group consisting of: the substrate, the high surface area to volume ratio material layer, an intervening layer between the substrate and the high surface area to volume ratio material layer, layer or layers over the high surface to volume ratio material or a combination thereof; whereby creating through-holes are performed using a technique selected from a group consisting of dissolving, dry etching, wet etching, reactive ion etching, deep silicon etching, and magnetically enhanced reactive ion etching.
• removing the high surface area to volume ratio material layer in step (d) is performed by chemical means, mechanical means or a combination thereof.
• the present method further comprises the step of disposing a separated device/coating structure/coating or mixture thereof over a second substrate.
• the method further comprises the step of depositing at least one coating over the device/coating structure/coating or mixture thereof, where the at least one coating is a carrier substrate used to dispose onto a second substrate after separating the system from the substrate in step (d).
• the second substrate is flexible and an organic, glass, or metal foil material.
• Uses for the system over the second substrate include, but are not limited to, the fabrication of thin film transistors, electronics, sensors, actuators, acoustics, detectors, microelectro-mechanical devices, displays, fuel cells, opto-electronics or solar cells.
• the present invention is further directed to a method for creating a cavity structure comprising (a) forming a high surface area to volume ratio material layer over at least a portion of a substrate; (b) forming at least one layer over the high surface area to volume ratio material layer; and (c) removing a portion of the high surface area to volume ratio material layer thereby creating a cavity structure.
• the high surface area to volume ratio material layer deposited over the substrate in step (a) is patterned using a soft masking material, hard masking material, or a combination thereof.
• removing the portion of the high surface area to volume ratio material layer in step (c) is performed by chemical means, physical means, mechanical means or a combination thereof.
• removal of the portion of the high surface area to volume ratio material layer in step (c) also removes a portion of the substrate.
• the one layer over the high surface area to volume ratio material layer is a material selected from the group consisting of: chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferroelectrics, metals, pyroelectrics, biological materials and semiconductors.
• gas or liquid is added into the cavity structure after the high surface area to volume ratio material layer is removed in step (c).
• the method further comprises the step of creating through-holes through at least one layer, the substrate or both to access the high surface area to volume ratio material layer. And, the method further comprises the step of forming an additional layer over the substrate after removing the high surface area to volume ratio material layer of step (c), thereby blocking the through-holes.
• the height of the cavity structure is at least 10 nm, and the width of the cavity structure is at least about 10nm.
• the creation of the cavity structure provides for the fabrication of a use selected from the group consisting of: MEMS, bolometric structures, chemical reaction systems, accelerometers, display, micro-mirror formations, biomedical and medical devices, sorting, capillary functions, cell and other species studies and identification; gettering regions for solid phase crystallization or silicon on insulator structures; interlayer stress control; optical and acoustic waveguide and device applications; and fluid channels for chemical sensors; chromatography, acoustics, fuel cells and molecular sorting.
• the present invention also relates to a method of creating a cavity structure in a substrate comprising (a) forming at least one stencil layer over at least a portion of a substrate; (b) removing a portion of the stencil layer thereby created an exposed portion of the substrate; (c) forming a high surface area to volume ratio material layer over the portion of the stencil layer and the exposed substrate; (d) lifting off a portion of the stencil layer, thereby also removing a portion of the high surface area to volume ratio material layer formed thereover and leaving the portion of the high surface area to volume ratio material layer formed on the exposed substrate; (e) forming at least one layer over the substrate and the high surface area to volume ratio material layer; and (f) removing the high surface area to volume ratio material layer to form a cavity structure.
• the stencil layer comprises a material selected from the group consisting of photoresists, nitrides, oxides, metals, polymers, dielectrics, semiconductors and mixtures thereof.
• the substrate is selected from the group consisting of Si wafer, quartz, glass, organic materials, polymers, ceramics, semiconductor, metals, and mixtures thereof.
• the stencil layer in step (b) is performed using a technique selected from a group consisting of: dissolving, dry etching, wet etching, and combinations thereof.
• the lifting off the stencil layer in step (d) is performed by dissolving, etching, mechanical means or a combination thereof.
• the method further comprises the step of creating through-holes to access the high surface area to volume ratio material layer.
• the method further comprises the step of adding gas or liquid into the cavity structure after the high surface area to volume ratio material layer is removed in step (f).
• the method further comprises the step of depositing a further layer, wherein the further layer blocks the through-holes.
• This further layer is a material selected from the group consisting of: dielectric, polymeric, metal, photoresist, nitride, oxide, and mixtures thereof.
• the present invention is also related to a method of producing at least one contact region between a first and a second material system over a substrate comprising the steps of: (a) forming a first material system over the substrate; (b) etching a portion of the first material system; (c) forming high surface area to volume ratio material layer over the first material system and the substrate; (d) removing a portion of the high surface area to volume ratio material layer to expose a portion of the first material system; (e) forming a second material system over the high surface area to volume ratio material layer and exposed portions of the first material system, so that a portion of the second material system contacts a portion of the first material system; and (f) removing the high surface area to volume ratio material layer, thereby freeing a portion between the first and second material systems while maintaining the at least one contact region.
• the first and second material systems are selected from the group consisting of metals, semiconductors, chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferroelectrics, pyroelectrics, biological materials, semiconductors and combinations thereof.
• the substrate is a material selected from the group consisting of: Si wafer, quartz, glass, organic materials, polymers, ceramics, semiconductor, metals, and mixtures thereof.
• removal of the high surface area to volume ratio material layer by chemical means has an etch rate of about 25 ⁇ m per minute or less.
• the production of at least one contact region between a first and a second material system provides for fabrication of a structure selected from the group consisting of: MEMS devices, cantilever structures, micro-switch structures, field emission sources, micro-mirror structures, and actuators.
• the present invention is further related to a method for fabricating an assembly including the step of forming channels within or over a substrate for bearing reactants, reaction products or both, the channels being formed by methods set forth above. More particularly, the method for fabricating a fuel cell comprising (a) depositing a masking layer on a substrate; (b) defining the locations of the channel regions in the masking layer; (c) covering the defined regions in the masking layer and a stencil layer in adjoining regions with a sacrificial layer material; (d) lifting off the sacrificial layer material in the stencil covered regions by dissolving or etching away the underlying stencil layer; (e) depositing anode and catalytic material over the entire resulting surface; (f) patterning this material system of step (e) to form the anode; (g) depositing an electrolyte on the resulting surface; (h) employing means to access the sacrificial layer; (i) using such means to etch or dissolve the sacrificial layer in the regions that are
• the present invention is directed to the use of "as deposited" large surface to volume ratio materials for separation, release layer and sacrificial materials applications.
• the separation, release, and sacrificial materials are removed by chemical attack, dissolution, mechanical agitation or disruption, gas pressure or chemical effects, or some combination of these.
• the removal of the material creates at least two, physically separated, material systems.
• the removal of the material creates material systems that remain attached in at least one place.
• the removal of the material creates an enclosed void or cavity (which may or may not be subsequently filled) in a materials system.
• the invention is demonstrated using deposited columnar void network thin films with controllable void volume as separation and sacrificial materials. These materials have a morphology that is variable and tailorable from a continuous film (no voids) to a film comprising: (a) a network of columnar-like units in a continuous void; and (b) a substrate to which the network of columnar-like units is adhered.
• These columnar void films can be conductors, semiconductors, or metals. They can be based on chemical elements, such as silicon, germanium, carbon, hydrogen or mixtures thereof.
• the films may be converted by chemical reaction into other materials such as oxides, nitrides, and inter-metallic compounds.
• the substrate supporting these films can be composed of various materials, including but not limited to, glass, metal, insulator material, polymeric material, semiconductor semiconductor-containing material.
• the concept of large surface to volume ratio separation/sacrificial films is demonstrated in this invention using nanostructured columnar/void material with a network of units collected in clusters and formed by deposition in plasma systems.
• the spacing and height of the network of columnar-like units are adjustable by variables selected from the group consisting of: oxidation, silicidation, etching, voltage, current, sputting voltage, voltage between plasma and substrate, substrate temperature, plasma power, process pressure, electromagnetic field in the vicinity of the substrate, deposition gases and flow rates, chamber conditioning, and substrate surface.
• Another approach to utilizing the high performance structures that can be created on plastic laminates with the separation approach of the present invention is to dice the individual device-containing islands of the plastic or other material laminate into independent die. These can then be assembled into systems as needed using self-assembling technologies such as those based on electrostatics, chemistry, or steric compatibility.
• Figure 1 a-d shows an approach to using separation layers and through- hole access. Structures, circuits, devices, etc. (shown here are TFTs) are fabricated on a mother substrate and then subsequently separated. A plastic material, deposited or formed before the device fabrication process flow, is used to provide the mechanical integrity needed after separation.
• Fig. 1a exhibits the rigid substrate having the columnar void layer or sacrificial layer, polymer coating and device, sensor or actuator deposited thereon.
• Fig. 1b shows the through-holes etched into the system.
• Fig. 1c shows the removal of the columnar void layer or sacrificial layer thereby separating the device from the substrate.
• Fig. 1d shows the separated device deposited onto a rugged or flexible substrate.
• Figure 2 a-d shows another approach to using separation layers and through-hole access. Structures, circuits, devices, etc. (shown here are TFTs) are fabricated on a mother substrate and then subsequently separated.
• a plastic material deposited or formed after the device fabrication process flow, is used to provide mechanical integrity after separation.
• Fig. 2a exhibits the rigid substrate having the columnar void layer or sacrificial layer, polymer coating and device, sensor or actuator and an additional polymer coating on the device, sensor or actuator deposited thereon.
• Fig. 2b shows the through-holes etched into the system.
• Fig. 2c shows the removal of the columnar void layer or sacrificial layer thereby separating the device from the substrate.
• Fig. 2d shows the separated device inverted and deposited onto a rugged or flexible substrate.
• Figure 3 depicts a CAPS structure which is made up of several plastic laminates containing circuits and power devices such as fuel cells.
• the final laminate contains pixels making the system into a display.
• the individual laminates that have been assembled to make this system have each been fabricated and separated following methodologies outlined in Figure 1 or 2.
• Figure 4 a-f illustrates use of a columnar void network deposited silicon film to form an empty cross section using a deposition/etch approach.
• Fig. 4a shows the columnar void layer or sacrificial layer deposition on the substrate.
• Fig. 4b shows the lithography and etching of the columnar void layer or sacrificial layer.
• Fig. 4c shows the wall/capping layer deposited on the etched columnar void layer or sacrificial layer.
• Fig. 4d shows wet etchant access window etching to produce through-holes as needed in top or sides for effective etching.
• Fig. 4e shows the etching of the columnar void layer or sacrificial layer.
• Fig. 4f shows the window filling or the deposition of another coating over said void structure.
• Figure 5 a-h illustrates use of a columnar void network deposited silicon film to form an empty cross section using a deposition/etch/I ift-off approach.
• Fig. 5a shows the base layer deposition.
• Fig. 5b shows the lithography and base layer and stencil layer etching.
• Fig. 5c shows the deposition of a columnar void layer or sacrificial layer.
• Fig. 5d shows the lift-off process for removing the stencil layer with a portion of the sacrificial layer.
• Fig. 5e shows the capping layer deposition.
• Fig. 5f shows the wet etchant access window etching to produce through-holes as needed.
• Fig. 5g shows the etching of the columnar void layer or sacrificial layer.
• Fig. 5h shows the window filling of the void structure.
• Figure 6 a-h illustrates use of a columnar void network deposited silicon film to form an enclosed empty structures such as channels, tubes, cavities, etc. of relatively large cross-section that can be fabricated with simple wet chemical etching without the need for the so-called, deep-etch reactive ion etching process.
• Fig. 6a shows the base layer deposition onto a substrate including substrate, optimal etch stop or barrier layer, deposited (e.g., a-Si or poly Si) and base layer (e.g., silicon nitride).
• Fig. 6b shows the lithography and base layer etching.
• Fig. 6c shows the columnar void layer or sacrificial layer deposition.
• FIG. 6d shows the lift off of the stencil layer with a portion of the columnar void layer or sacrificial layer.
• Fig. 6e shows the capping layer deposition.
• Fig. 6f shows the etchant access window etching.
• Fig. 6g shows the sacrificial layer etching and trench creation.
• Fig. 6h shows the window filling.
• Figure 7 is a cross-sectional SEM micrograph of a void or cavity structure fabricated following the deposition/etch approach outlined in Fig. 4.
• Figure 8 is a cross-sectional SEM micrograph of a void or cavity structure fabricated following the deposition/etch/lift-off approach outlined in Fig. 5.
• Figure 9a illustrates a fuel cell fabricated using a silicon wafer.
• Figure 9b illustrates a fuel cell fabricated using deposited silicon on a lightweight substrate such as a polymer, glass, or metal foil.
• Figure 10 illustrates a detailed fuel cell processing sequence for Figure
• Figure 11 a-c are pictures of an actual sorting structure formed using the columnar void layer as the sacrificial material. Such a structure could be on a laminate formed by the separation procedure.
• Fig. 11b shows the boundary between the deep channel and shallow channel.
• Fig. 11c shows an enlarged image of Fig. 11b.
• Figure 12 illustrates a molecular immobilization for detection. Detection can be accomplished by monitoring the ac or dc electrical response between the electrodes immobilizing the molecular entity.
• Figure 13 a-h illustrates the formation of a Release layer for application of the present material.
• Fig. 13a shows the Cr/Au deposition.
• Fig. 13b shows the lithography and etching.
• Fig. 13c shows the column void network material deposition.
• Fig. 13d shows the contact tip etching.
• Fig. 13e shows the beam support etching.
• Fig. 13f shows the lithography of the column void network material.
• Fig. 13g shows the Au deposition.
• Fig. 13h shows the column void network material etching.
• the approach to producing materials with large void volumes and therefore large surface area to volume ratios in the present invention is to use deposition to grow as-deposited porous films.
• void regions are reasonably uniform through the thickness of the film and across the film.
• the process for deposition is unique because it is performed at low temperature, the present inventors have demonstrated that the present invention can be used to control void size and void fraction, the void-column network morphology does not vary over thicknesses of interest, the columns can be polycrystalline or amorphous material.
• Plasma approach including dc and rf discharge, sputting and high density plasma tools can be used to control the interaction between deposition and etching during growth.
• the process demonstrated using high density plasma deposition etching interaction, is able to give high porosity (of up to approximately 90%), controlled pore size material without any back contacts and anodization-based wet processing.
• the present process is based on high-density plasma deposition-etching interaction and is, therefore, able to give a high degree of controllable porosity (up to 90%), a morphology that does not vary with thickness, and doped or un-doped polycrystalline columns.
• Also unique to the present invention is its ability to fabricate high surface to volume material on various types of substrates including glass, metal foils, insulators, plastic, and semiconductor-containing materials.
• the high density plasma (HDP) deposition tool used in this demonstration was an electron cyclotron resonance plasma machine.
• a high density plasma tool e.g., Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition (ECR- PECVD) tool (PlasmaTherm SLR-770)
• ECR- PECVD Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition
• H 2 :SiH hydrogen diluted silane
• This tool plays off silicon etching and deposition to create a two-dimensional silicon array and analysis has demonstrated that silicon column size is controllable, the spacing between columns is controllable, and morphology does not vary significantly with thickness.
• the column spacing can be maintained as the film grows in thickness and column phase composition can be controllably varied from polycrystalline to amorphous.
• the resulting columnar void network structure is nanoscale in feature size and fully developed after a film thickness in the range of 10-20 nm is established. This enables the direct deposition of high surface to volume ratio of crystalline or amorphous silicon on any substrate and at any thickness greater than about 10 nm, and preferably between 10-20 nm.
• the high void volume semiconductor films produced by the present invention may be converted to insulators or metallic compounds through in situ or ex situ processing.
• the present invention provides a deposited high surface to volume ratio film comprising a plurality of perturbations extending therefrom into a void having a porosity of up to about 90%.
• the plurality of perturbations are disposed substantially perpendicular to a substrate, or in the alternative, to a base layer.
• the plurality of perturbations are rod-like shaped columns, and may be polycrystalline or amorphous, such as a silicon material.
• the porosity is the result of a continuous void.
• the perturbations have a height adjustable by the film thickness and are of a diameter from about 1 nm to about 100 nm. More specifically, the columns have a diameter of about 3 nm to about 7 nm. Further, the perturbations are found in clusters having a diameter between about 50 to 500 nm or more.
• the special attributes of the deposited columnar void network-type of high surface to volume thin films are controlled by a number of factors. These include the (a) voltage between plasma and substrate, (b) substrate temperature, (c) plasma power and process pressure, (d) magnetic field in the vicinity of the substrate, (e) deposition gases and flow rates, (f) chamber conditioning, (g) sputtering voltage, and/or (h) substrate surface. The influence of a number of these factors is not what would be expected.
• the present invention further provides materials and methodologies for separating material systems into physically independent systems, for releasing materials into partially separated systems, and for creating enclosed cavities in materials. A number of applications resulting from the use of these materials and methodologies are presented.
• the invention uses deposited large surface area to volume ratio materials as the separation, sacrificial or release material. It is shown that particularly effective deposited large surface area to volume ratio materials are provided by deposited columnar void network films.
• the present invention is demonstrated with a specific example of a deposited large surface to volume material, the deposited columnar void network silicon.
• This material has the large, and adjustable, surface to volume ratio (i.e., large surface area).
• This large surface to volume ratio means that the material has the large surface area, making it very vulnerable to chemical attack and easily mechanically weakened.
• the large surface to volume ratio also means that chemical species can move relatively freely through the void region penetrated by the columns. It means that the material quickly and uniformly "wets" due to capillary action leading to uniform removal procedures based on chemical attack or dissolution.
• due to the large void volume (i.e., high porosity) of this material it can store gases which can be used in removal processes, if gas pressure or gas interactions are used to split apart material systems in release layer applications.
• Porous Si was first obtained in 1956 electrochemically by Uhlir at Bell Labs • but it was not until 1970 that the porous nature of the electrochemically etched Si was realized [Y. Watanabe and T. Sakai, Rev. Electron.
• the starting material for this wet etched conventional porous Si material is either conventional silicon wafers or thin film Si produced by some deposition process such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
• LPCVD low pressure chemical vapor deposition
• PECVD plasma enhanced chemical vapor deposition
• the electrochemical wet etching process requires that the silicon sample is exposed to a wet solution and a current is passed through a contact to the etching sample, through the etching sample, through the solution (e.g., a mixture of hydrofluoric acid, water and ethanol), and through an electrode contacting the solution (the cathode; e.g., platinum). This current causes the "pitting" or etching of the Si sample producing a porous network structure.
• the structure e.g., pore size and spacing
• the porous-Si layer thickness are controllable by the resistivity of the silicon itself (magnitude and type), current density, applied potential, electrolyte composition, application of light, temperature, and exposure time.
• this electrochemical etching process can be continued to the point where nanoscale structure (i.e., features of the order of nanometers) is obtained.
• the silicon features are a continuous single crystal when the sample is etched from a single crystal wafer, as is usually done, or polycrystalline silicon when the sample is etched from a deposited film.
• the approach to producing a high surface area to volume ratio material in the present invention is to use deposition to grow as-deposited high surface-area films.
• the ratio in high surface are to volume ratio materials is based on considering the excess area over and above what would be present if the film were continuous and had no voids.
• a preferred ratio in high surface area to volume ratio materials is up to 10,000 to 1.
• High surface area films are deposited films that can be placed anywhere they are needed for release layer or sacrificial layer applications. They can be deposited on planar or curved surfaces and on substrates of any composition.
• columnar void network silicon material prepared by plasma enhanced chemical vapor deposition (PECVD).
• PECVD plasma enhanced chemical vapor deposition
• the present approach is demonstrated by preparing columnar void network material using a high density plasma tool (e.g., Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition (ECR-PECVD) tool (PlasmaTherm SLR-770)).
• ECR-PECVD Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition
• Deposition of the material utilized hydrogen diluted silane (H 2 :SiH ) as the precursor gas at substrate deposition temperatures less than or equal to about 250°C.
• the high density plasma tool approach plays off silicon etching and deposition to create a two-dimensional silicon array and analysis has demonstrated that silicon column size is controllable and the spacing between columns is controllable.
• the resulting columnar/void network structure is nanoscale in feature size and fully developed after a film thickness in the range of 10-20 nm is established. Columns range in diameter between 30D to about 100D. This enables the direct deposition of a large surface to volume material (i.e., high porosity material) in crystalline or amorphous phase on any substrate and at any thickness greater than about 10 nm.
• the columnar/void semiconductor films produced by the present invention may be converted to insulators or metallic compounds through in situ or ex situ processing.
• functionalizing layers may be formed or deposited after or before deposition of the columnar/void network material.
• the columnar void network silicon used in the present invention is deposited rather than formed by wet electrochemical etching thereby allowing it to be formed anywhere on any substrate.
• the present deposited has a unique columnar structure and contains an inherently formed void (i.e. empty space) in between the columns. That is, the morphology has the distinctive feature of being rods (columns), which are essentially perpendicular or close to perpendicular to a thin transition layer on the surface on which the film was deposited. These columns penetrate through the void.
• the film void is continuous facilitating fast removal of material in sacrificial, separation or release layer applications by allowing fast transport of reactants and reaction products through the layer and to and from wet-etchant, access windows or through- holes.
• the fast removal of the sacrificial, separation or release layer increases the reliability of the fabrication process because it reduces the possibility that other structural layers could be damaged during wet etching.
• the present deposited columnar void silicon can be laid down on any type of substrate, such as plastic, glass, silicon wafer and metal foil. This is another unique advantage of the deposited columnar void network silicon over conventional electrochemically wet etched porous silicon, which requires silicon substrates or films with at least one underlying electrical contact for its electrochemical formation.
• the electronic, chemical, display, micro-fluidic, and optoelectronic devices and structures that are advantageous to have on these substrates can comprise diodes, transistors, sensors, actuators, heat transfer systems, micro-electro-mechanical devices (MEMS), fuel cells, solar cells, and combinations of these.
• MEMS micro-electro-mechanical devices
• Fabrication of such devices and structures on non-conventional substrates offers a number of new applications because systems can be created that are foldable, shockproof, lightweight, or some combination of these.
• the fabrication of such devices and structures on flexible substrates also allows the integration of substrates (laminates) into more complex systems, as in the example of Fig. 3, and enables the concept of Customization and Adaptability using Plastic Substrates (what we term the CAPS approach).
• these new devices and circuits can be on polymer substrates such as elastomers that can be shrunk-fit to various shapes.
• Devices and structures on flexible substrates can be operated on curved surfaces as well as be used in harsh environments.
• the present invention renders the fabrication of electronic, chemical, mechanical, fluidic, display, and opto-electronic devices and structures on flexible substrates into a very reproducible and manufacturable technology in spite of the rough, uneven substrate surfaces, dimensional integrity, mechanical strength, and thermal stability issues of such flexible substrates.
• This invention disclosed here provides the necessary separation layer materials, manufacturing technology, and applications concepts.
• Figs. 1 a-d and Fig. 2 a-d show that there are two general approaches to using large surface area to volume ratio material as a separation layer. In both cases, structures, circuits, devices, etc. (shown here are TFTs) are fabricated on a mother substrate and then subsequently separated. In Fig.
• a carrier substrate material such as a plastic material, deposited or formed before the device fabrication process flow, is used to provide the mechanical integrity needed after separation from the mother substrate.
• a carrier substrate material such as a plastic material, deposited or formed after the device fabrication process flow, is used to provide mechanical integrity after separation from the mother substrate.
• the processing flow may incorporate at least some high temperature steps.
• the plastic carrier material for example, bearing the devices, circuits, or both may be attached to other laminates (Fig. 3), other substrates, or other objects.
• a conventional rigid smooth substrate such as a Si wafer, quartz, or a Corning glass substrate is chosen as the rigid mother substrate due to its having a smooth surface and compatibility with microelectronics processing.
• This mother substrate is intended to be reusable and may or may not have a covering layer on its surface.
• the through-holes for chemical access to the sacnficial layer can be in the mother substrate, which, as noted, may be reusable
• the device structures and circuits on the laminate can be separated from the rigid substrate as displayed in step (c) of Fig 1 Since the separated device structures sit on the flexible polymer transport layer, we can attach this device to any rugged-surface substrate as shown in step (d) of Fig 1 , to any surface — flat or curved, or to other laminates (See Fig 3)
• Fig 2 displays the general features of a second version of this approach
• a sacnficial layer is first deposited on a rigid mother substrate prior to a device fabrication processes.
• This mother substrate may be reusable and may have a coating.
• a carrier substrate such as a polymer layer is coated over the devices and structures.
• through-holes from the polymer coating down to the sacrificial layer are created.
• the carrier layer such as a flexible polymer transport layer
• Such laminates may be formed together to create the system seen in Fig. 3. Also the laminates can be attached to any curved surfaces.
• This invention is directed to the use of general separation layers in the process outlined in Fig. 2. It is also directed to the specific use of high surface area to volume materials, such as columnar void network materials as separation layers in processes such as those outlined in Figs. 1 and 2.
• This separation process using through-hole conduits can be employed to fabricate a variety of devices and systems including thin film transistors, sensors, actuators, microelectro-mechanical devices (MEMS), fuel cells, and solar cells on the transfer (laminate) layer of Figs.1 and 2.
• MEMS microelectro-mechanical devices
• solar cells on the transfer (laminate) layer of Figs.1 and 2.
• the use of this sacrificial layer/through-hole and transfer layer approach can be used to establish devices and circuits on pre-existing devices, wafers, and die.
• the high performance structures that can be created on plastic laminates with the separation approach can also be used in an alternative way, i.e., the structures of Fig. 1 or 2 can be formed and then the individual device-containing islands of the plastic or other material laminate can be cut, scribed, or otherwise separated into independent die. These can then be assembled into systems as needed using self-assembling technologies such as those based on electrostatics, chemistry, or steric compatibility.
• cavities may be formed using the deposited thin film material according to the present invention by using two sacrificial layers.
• One of these layers is a columnar void layer and it and a second material are used in part of the region to be the channel.
• the other layer is some other material, such as a metal. It is the only sacrificial material in that other part of the channel.
• the purpose of using two materials for forming the channel is so that a very precise and very shallow channel depth in a particular region may be created where the sacrificial layers are used.
• the shallow region can be as shallow as 10 nm in the region using the metal and the deep region in the same channel or cavity structure can be as deep as hundreds of microns in the region using both sacrificial layers. Consequently, channels with widely varying depths for sorting and sensor applications that can occur as molecules flow down the channel. In sensor application, the sensor may be placed within the shallow regions.
• the release layer applications of the films according to the present invention also can have a multitude of applications. These applications are very similar to those of separation layers except the separated material systems are not completely separated and remain contacted in at least one place.
• the advantages and processing of the materials of the present invention in release layer applications are similar to those of separation layers. The key difference is only that the materials systems involved in release layer applications are not completely separated and remain contacted in at least one place.
• the present invention is also specifically directed to the use of as- deposited large surface to volume materials as sacrificial materials for void (i.e., cavity) creation.
• void-based structures that are created have an empty space (cavity) region defined by an envelope of one or more materials.
• the size and shape of the cavity can be modified for the application purposes.
• Such structures can be used as channels applied to microfluidic applications such as in nozzle structures; in cooling or heating applications; in mimicking circulatory system capillary functions (e.g., nutrient transport, temperature control, oxygenation, etc.) for culture, tissue, and organ physical and nutrient support; in systems for drug diffusion and delivery; in nebulizers for drug delivery; in chromatography tube applications; in filtering or catalytic structures; in liquid or gas delivery systems and in reaction chambers in chemical devices such as fuel cells; and in sorting and delivery structures for bead, particle, cell, or molecule separation.
• These structures can also be applied to many MEMS devices such as actuators, detectors, bolometers, and cantilever sensors.
• the approach to cavity (void) formation disclosed here for structures such as air-gaps, cavities, channels, and tubes is a surface micromachining technique based on the use of sacrificial layers.
• the patterns defining the cavity formation can be established by variety of pattern transfer approaches including conventional lithography, jet printing, beam lithography, and soft and contact printing methods.
• the key feature of the present new process flow is that the structures are formed using deposited large surface to volume material as the sacrificial material.
• the specific demonstration is done with the unique columnar void network morphology film which is an excellent large surface to volume material. For cavities, channels, etc.
• the columnar void material is removed by using etchant/etch-product access holes, where the etching may be combined with mechanical agitation. If the deposited columnar void material is left in the channel (i.e., is left to occupy the cross section), such as may be useful in sorting and filtering applications, then no etching of this material is required. In this case the columnar void network material is not sacrificed but used to establish and support the void capping layer and allowed to remain.
• the present inventors have discovered that the key to creating manufacturable, reproducible and controllable enclosed empty regions in materials is the deposited large surface to volume material approach.
• the present invention demonstrate this approach using columnar void network silicon, which, unlike conventional porous silicon, is deposited, involves no electrochemical etching, and has a unique, regular and controllable columnar void morphology wherein the silicon penetrates the void.
• Using plasma deposition processes at low temperatures allows the material to be laid down on a wide variety of substrates including previously formed circuits and devices, plastics, glass, organic and polymeric materials, and metal foils.
• Its columnar void structure makes it a filter medium in filled channel applications or an excellent precursor for the creation of empty channels, voids, cavities, and tubes in empty cross section applications.
• the bottom, side-walls, and top of the channels formed by this approach can be comprised of a variety of organic and inorganic materials including elastomers, insulators, semiconductors or metals They can be comprised of active layers such as those encompassing current carrying structures, gate structures, piezoelectrics, pyroelectrics, ferroelectrics or magnetic materials
• the bottom, side-walls, and top of the channels, voids, cavities, air-gaps and tubes can also be comprised of materials such as small organic molecules, or polymers
• the sacnficial layer use can be employed in deposition/etching formation approaches (Fig 4 a-f), in deposition/etching/ lift-off formation approaches (Fig 5 a-h), or combinations thereof
• the key to a successful process is to insure that the thickness of the deposited film to be lifted off should be much thinner than the stencil layer at the sides of the step pattern (see Fig 5a-h), or to insure this film to be hfted-off should be discontinuous Therefore, lift-off processes are often not used in the fabrication of MEMS or bioMEMS devices, since these can require relatively thick films
• the deposited columnar void silicon of the present invention has a very unique continuous void (silicon columns penetrating the void from a transition layer) morphology and this morphology allows easy access of gases and liquids to the stencil layer (the layer causing the fting-off) for chemicals designed to remove this layer
• the stencil layer is photoresist
• acetone is able to readily attack the photoresist located under even thick columnar void silicon layers In this case, acetone travels through the void region penetrated by the silicon columns and reaches the photoresist (stenc)
• nano- or micro- voids, cavities, channels, etc can be fabricated either by some variant of deposition/etching processing (Fig 4 a-f) or they can be fabricated by some variant of very advantageous deposition/etching/lift-off processing (Fig. 5 a-h). In either case the fabrication can involve only low temperature processes and has flexible design rules.
• the deposition/etching/lift-off processing is especially advantageous since it also offers very simplistic processing, super flat surfaces, and thin capping layers. Both deposition/etching processing (Fig. 4 a-f) or deposition/etching/lift-off processing (Fig.
• 5 a-h can be applied to a wide range of substrates including organics, plastics, glass, deposited semiconductors, semiconductors with previously fabricated circuits and chips, silicon chips or wafers, and metal foils. It is to be noted that these substrates can be curved, either prior to or after fabrication.
• the flat surfaces and the thin capping layer structures are advantageous to cooling or heating applications because the flat surface and thin capping layer increase heat transfer efficiency by increasing the interface area in contact with whatever is to be heated or cooled.
• the channels can be fabricated with low temperature, non-destructive processes in the methodologies, the present approach allows cooling (or heating) structures to be built directly onto circuits and devices after their fabrication.
• the channels of the present invention can be fabricated on metal or plastic foils, heat sinking channel-based structures, for example, can be fabricated on foil substrates such as the laminates of Fig. 3 and then adhered onto circuit and device structures for cooling and temperature control.
• the flexible design rules permitted by the present approach also allow applying the voids, cavities, channels, etc. to a wide range of other nano- or micro fluidic applications such as nozzles; mimicking circulatory system capillary functions (e.g., nutrient transport, temperature control, oxygenation, etc.) for culture, tissue, and organ support; capillary systems for drug diffusion and delivery; nebulizers for drug delivery; tubes for chromatography and fuel cells; filtering or catalytic structures; and sorting structures for bead, particle, cell, or molecule separation.
• channels can function as scaffolds as well as capillaries for cell, tissue, and organ growth.
• FIG. 4 a-f A detailed discussion of an example of the process flow involved in the deposition/etching approach to fabricating nano- and micro- void structures can be undertaken using Fig. 4 a-f.
• silicon dioxide first was actually deposited as a coating layer (not shown in Fig.4 a-f) on the substrate using a Plasma Therm SRL770 electron cyclotron resonance-plasma enhanced chemical vapor deposition (ECR-PECVD).
• ECR-PECVD Plasma Therm SRL770 electron cyclotron resonance-plasma enhanced chemical vapor deposition
• the silicon dioxide was used as a bottom layer for the void structure, and it (or other layers that may be used for the same function) can be used to prevent any possible substrate etching when the columnar void network silicon release layer is being removed, i.e., such materials can be used as etch stop layers.
• the etchant used to remove the deposited columnar void network silicon was tetra methyl ammonium hydroxide (TMAH).
• TMAH tetra methyl ammonium hydroxide
• the etch selectivity of TMAH to etching deposited columnar void network silicon over silicon oxide is very high, and the 500A of silicon dioxide used in this demonstration was thick enough to protect the substrate.
• Another purpose of silicon dioxide (or other first layer) deposition can be to act as an interdiffusion barrier layer and to improve the interface with the substrate being used. The latter can be very important, for example, for stress control
• Micro- and nano-cavities made with the present approach, can also be used for dielectric isolation and for the tailoring of optical response and interactions.
• they can be applied to the intermetal dielectric (IMD) microelectronic chip applications and optical device applications such as anti-reflection and absorption structures, optical switches, waveguides, and amplifiers.
• IMD intermetal dielectric
• the fundamental optical frequency of cavities can be tuned by changing cavity size and shape, and surrounding material refractive index, and this ability to tune the resonant mode is very useful for the optical devices such as tunable optical filters, optical gates, optical switches, channel drop filters, and optical interconnects.
• Low dielectric constant (i.e., low k) applications can require multiple cavities, and wider sizes of cavity structures than optical applications because the structures have to provide a low dielectric constant yet have mechanical stability.
• the columnar void network silicon layer was the next layer to be deposited in this demonstration. It was deposited after ECR-PECVD chamber conditioning using hydrogen plasma and oxygen plasma runs. Such conditioning can be useful for process control for release, separation, or sacrificial layer deposition.
• the detailed chamber conditioning parameters that were used in this demonstration are described in the Table 2. The conditioning using hydrogen plasma and oxygen plasma was performed for 30 min and 10 min., respectively.
• this columnar void network deposited silicon layer will be removed by a subsequent etching process (in this demonstration TMAH wet etching was used) to create the cavity region, this silicon deposition dictates what space will be the cavity region for the airgap, channel, etc.
• the thickness of the deposited columnar void network silicon is the height dimension of the cavity in this approach; consequently, the height of the cavity region can be changed very easily and accurately.
• a material may be deposited before the columnar void network silicon and it too may be designed to etch when the columnar void material etches giving a deeper final cavity (for a channel, airgap, etc.) whose depth is not controlled by the columnar void silicon thickness.
• An example of such a void (cavity) is seen in Fig. 6 a-h; in this case the processing approach of Fig. 5 a-h was followed but that of Fig.4 also may be used.
• the thickness of the silicon nitride layer could be adjusted to modify properties such as strength, dielectric constant, optical properties, diffusion barrier properties, thermal conductivity, or some combination of these. Other coating materials may be used and similarly adjusted. Alternatively lift-off processes may be used to form the deposited porous silicon region and only a capping role would then be played by this layer.
• Small window structures are required in, or adjacent to, the cap layer to etch out the deposited columnar void network silicon sacrificial layer, as seen in Fig.4d.
• these were established using a lithography process performed using Shipley 1813 photoresist.
• the window patterns were etched by Plasma Therm 720 Reactive Ion Etching (RIE) system. CF /O 2 plasma was used and the detail etching parameters were described in Table 3.
• Nanostrip removed the photoresist used to define the RIE step by dipping the samples in the solution for 10 minutes. Next a 0.1 % solution of BOE (Buffered Oxide Etcher) followed to remove the native oxide layer on the columnar void network silicon surface exposed by the windows.
• BOE Bovine Oxide Etcher
• the BOE process was a very important step because it could damage other structural layers. Therefore, the BOE etching time and the concentration of the solution were very important in this particular demonstration.
• the deposited columnar void network silicon sacrificial layer was removed by TMAH solution.
• TMAH solution For the void (cavity region) of this demonstration the columnar void network silicon sacrificial layer removal took less than 30 minutes to complete, as compared to conventional release layer processes which can take upwards of 20 hours.
• the rinse and dry processes following etching removal of the release layer were important process steps because the structure became very fragile after etching the release layer. Rinsing was accomplished by immersion of the samples into Dl water with constantly flowing, additional Dl water entering the bath. The samples were rinsed more than one hour, and dried by very weak nitrogen blow dry. The angle of the nitrogen flow was also very important and the blowing direction was almost parallel to the sample surface.
• Fig. 7 The structure of the void-column deposited porous silicon consists of an array of columns in a continuous void (pore); hence, it is a void column network material.
• Shipley 1813 photoresist was used for the first lithography process (i.e., to pattern the nitride) and this pattern was used again for the lift-off process.
• the characteristics of the photoresist were a crucial factor for the lift-off process because, if the photoresist was exposed to a high ion energy plasma for a long time, it could be hardened and could be difficult to remove using acetone cleaning even in an ultrasonic bath. Most of the columnar void silicon film deposited on the stencil (here the photoresist) lifted off within a minute of immersion in this bath, and the process was completed after 3 minutes.
• the lift-off process provided super flat surfaces without chemical mechanical polishing (CMP) processing, and it allowed the option of a thin capping layer keeping the flat surface and it allowed multiple layers of tubes or cavity structures with crossovers.
• the substrate was cleaned using acetone, isopropylalcohol and deionized water after liftoff, and baked on the hot plate for 10 minutes.
• 2000 A of silicon nitride was deposted on top of the substrate as a capping layer.
• the deposition condition was the same as the first silicon nitride layer and the deposition rate was calculated from the first silicon nitride layer deposition.
• the Si 3 N 4 was etched at 200W and 50G for 160 seconds, and CF and O 2 are used as process gases in the demonstration.
• One lithograph step could be used to define both the channel bottom and the stencil layer, if, for example, the photoresist served as the defining layer for the nitride etch and as the stencil.
• the nitride was etched with reactive ion etching (RIE) using CF /O 2 mixed gases under conditions in the Table 5.
• RIE reactive ion etching
• the silicon nitride layer was over-etched to make sure of the removal of the layer.
• the photoresist mask for this nitride bottom definition etching was not used as the stencil for lift-off. Instead it was removed using acetone even though the same photoresist layer pattern was required for the following lift-off process. There were two reasons for the photoresist removal used in this particular example.
• the first one is that, for the etch parameters and materials used in this example, the photoresist used as the nitride mask was hardened due the etch plasma exposure and was difficult to remove making it a poor candidate for a lift-off process.
• the etch parameters and materials used there was a thickness change in the photoresist in this example processing due to the plasma exposure. This could be a factor that might lead to failure of the following lift-off process; hence, the nitride mask photoresist was removed after nitride etching to obviate these two factors.
• a second photoresist and exposure was done to form the stencil. Alternatively parameters or materials could be changed to eliminate the need for this second photoresist application and exposure.
• a thicker photoresist serving as both the nitride etch mask and stencil could have been used to remove the need for this double lithography process employed in the present demonstration.
• non-polymeric materials could be used as the stencil for lift-off.
• a columnar/void network type silicon was deposited using the same ECR-PECVD that was used for silicon nitride deposition, and the detailed deposition parameters are described in Table 4. Subsequently, lift-off was done in an ultrasonic acetone bath. Most of the columnar void silicon film deposited on the stencil (here the photoresist) lifted off within a minute of immersion in this bath, and the process was completed after 3 minutes.
• the lift-off process provided super flat surfaces without chemical mechanical polishing (CMP) processing, and it allowed the option of a thin capping layer keeping the flat surface, multiple layers of tube or cavity structure with crossovers.
• CMP chemical mechanical polishing
• the substrate was cleaned using acetone, IPA and Dl water after lift-off, and baked on the hotplate for 10 minutes.
• 2000A of silicon nitride was deposited on top of the substrate as a capping layer.
• the deposition condition was the same as the first silicon nitride layer and the deposition rate was calculated from the first silicon nitride layer deposition.
• An additional lithography step was then performed to make widows (access holes for the chemical to be used to attack the sacrificial material) at predetermined locations to allow wet etchant access to the columnar void film. RIE was used for the etching of these spaced windows.
• the etching condition was also the same as the previous one, and the etch time was also calculated from the first silicon nitride etch rate.
• the substrate was immersed to the 1 % BOE for 2 minutes to remove any oxide layer that may have grown on the columnar void silicon surface before the sacrificial layer etching. Then 5% tetramethyl ammonium hydroxide (TMAH) was used to do the etching, through the access holes, of the sacrificial layer columnar void silicon. This TMAH solution was heated at 75°C. The etched samples were subsequently cleaned in flowing Dl water for 30minutes, and dried in a vacuum environment.
• TMAH tetramethyl ammonium hydroxide
• the access windows were sealed (see Fig. 5) by use of a spin on glass (SOG), and the thickness of the SOG film could be tuned by changing the spin speed of the chuck.
• the sample was cured on a hotplate.
• These access hole windows may be left unfilled, if advantageous in applications such as nutrient delivery, drug delivery, nebulization.
• Fig. 8 shows a micro tube.
• the width of this tube is in the range of about less than 100 ⁇ m and preferably between 10Dm and 50Dm, and has a base layer under the tube structure.
• the height of the tubes range between 0.5 ⁇ m and 50 ⁇ m and may be as low as 50nm. Since a silicon wafer was used as the substrate, the base layer Si 3 N was used for the tube to prevent substrate etching during the sacrificial layer etching process. Capping layers used for these tubes were 5000A in thickness. This thickness is seen to be too thin for the 50Dm wide tube, which is seen to have some cap layer bending in the middle.
• the bending is caused by the bubbles produced during the sacrificial layer etching. This bending increases as the width of the tube increases. For example, for the 5000A capping film, the height of the bend is about 1.5Dm. This is about three times higher than the original tube height.
• the fast etch rate of this columnar void network material prevents thinning or damaging of the other structural materials and allows the fabrication of up to 10O ⁇ m wide tubes.
• a 5000A capping layer results in a cracked tube ceiling and ceiling collapse due to stress from the capping layer bending.
• the thicker capping layer can improve the capping layer bending problem and allow the fabrication of wider widths to tubes.
• a thicker capping layer can allow the fabrication of wider widths of tubes, and modifying the design for and placement of the access holes can be another factor in allowing tube structures, wider than 100Dm.
• the lift-off based approach which has never been demonstrated or even proposed for conventional, electrochemically prepared porous silicon, has several advantages, i.e., it is simple and manufacturable, it allows the use of thick sacrificial layer silicon films, when needed, and it can be used, when desired, to create extremely flat surfaces for the empty region's defining walls, bottom, and top. Alternatively, it can be used, as seen in Fig. 6, to produce channels, tubes, sorting structures, etc. of relatively large cross-section without the need for the so-called deep etch reactive ion etching process.
• the very effective lift-off processing is possible, even when thick silicon sacrificial films are to be lifted-off (i.e., removed in selected areas), because of the columnar void network morphology of the present film.
• the unique columnar/void ' structure allows etching liquids to efficiently reach the stencil (lift-off causing) layer under the columnar void silicon in inter-channel regions.
• the stencil layer which defines where the silicon material will be removed, is attacked by chemicals penetrating the columnar void silicon layer. This results in the dissolution or etching away of the stencil layer and the floating away (i.e., the lift-off) of the now unsupported silicon layer in the inter- channel or inter-air gap, etc. regions.
• the columnar void silicon in what will become the channel regions is not lifted off as seen in Fig. 5 or Fig. 6.
• the lift-off process results in very flat surfaces in the inter-channel, etc. region, which removes the need for any planarization step and allows one to freely choose the thickness of capping layer of Fig. 5 or 6.
• Very thin capping layers, if necessary, are thereby permitted.
• the capping layer is the film, which defines the top (i.e., the roof) of the void structure (e.g., channel, tube, air-gap, etc.) as seen in Figs. 4, 5, or 6.
• a thin capping layer can be a key factor for some applications such as nutrient delivery, drug delivery, and micro-cooler or heater applications because a thick capping layer can impede substance or heat transport to or from a capillary (i.e., channel).
• the capping layer may actually be composed of a multitude of materials or sublayers some of which may be patterned (e.g., grid-like or screen-like in their pattern).
• the capping layer may be patterned (e.g., grid-like, or screen-like) or a permeable membrane separating the lower void region from another such region above.
• Fuel cells This invention demonstrates a novel fabrication process for micro- scale fuel cells based on using the sacrificial layer approach according to the present invention. Fabrication processes that may be used include photolithography, reactive ion etching (RIE), chemical vapor deposition (CVD), selective wet etching, and deep silicon etching.
• RIE reactive ion etching
• CVD chemical vapor deposition
• the unique feature of the work according to the present invention is its use of large surface to volume ratio material for the sacrificial layer.
• the present low-deposition temperature, deposited columnar void network material is used as a sacrificial layer for channel formation.
• the columnar void network silicon is removed with high etching selectivity to other structure materials to define channels for fuel cell fabrication.
• deposited SiO 2 material was used as the proton transport medium.
• Other proton transport materials including Nafion could be utilized.
• deposited Si 3 N 4 was used as a unique proton confinement layer. This application of nitride may or may not be used, depending on the situation.
• the advantages of this particular fuel cell design and fabrication include: (1) ease of fabrication, (2) compatibility with lightweight substrates such as plastics and metal foils, (3) ease of combining into stacked structures and ease of integration with transistors, diodes, or both for power management, (4) ease of integration with sensors for chemical reaction control, (5) ease integration with a variety of micro-fluidics, display pixels, sensors, and detectors for powering various functions, and (6) ease of combining into stacked structures such as those seen in Fig. 3.
• Figure 9a shows a fuel cell structure fabricated on a silicon wafer according to this invention.
• a basic unit of electrode, solid electrolyte and electrode is fabricated on the silicon wafer, in which the channels have been patterned by selective etching of a sacrificial layer.
• the channels embedded in the silicon substrate play the role of feeding paths for fuels to the fuel cell.
• the fuel a hydrogen-bearing source such as hydrogen gas or alcohols like methanol, is fed through the channels for the electron-yielding reaction seen in Fig. 9a.
• This reaction is the oxidation of hydrogen source to produce protons, electrons and byproducts such as hydrocarbons.
• the electrode where this occurs is comprised of catalytic materials, such as platinum or palladium.
• the protons generated by this oxidation reaction diffuse into the proton transport layer toward the opposite electrode. However, the electrons are blocked from entering the proton transport layer because of its low electrical conductivity.
• Fluorocarbon-polymeric material for example NafionTM from DuPont, has been used for the membrane electrolyte for fuel cell for many years and can be the proton transport layer in Fig. 9a. In this invention, other materials, such as deposited silicon dioxide, with its high proton conductivity, can also be used for this solid proton transport layer.
• the protons penetrate the electrolyte (e.g., NafionTM or silicon dioxide) toward the other electrode, at which the reduction reaction occurs.
• a deposited Si 3 N 4 layer may be used with the hydrogen source channels to block lateral proton movement. Alternately, this layer may be replaced by deposited Si ⁇ 2 designed to create a more laterally uniform proton supply.
• This fuel cell unit also can be fabricated on other types of substrates such as polymers, glasses, and metal foils.
• a silicon layer or other material can be deposited on a plastic, glass or metal foil substrate and the fuel cell fabricated in the deposited silicon layer.
• the sacrificial layer is removed as in Fig 9a and the removing chemical is used to etch the deposited silicon instead of a wafer material, as necessary.
• a detailed process sequence is shown in Fig. 10a and another in Fig. 10b.
• thick silicon nitride layer is first deposited on a silicon wafer to play the role of defining the channels and of a masking layer for channel etching.
• ECR-PECVD electron cyclotron resonance plasma enhanced chemical vapor deposition
• the process conditions for silicon nitride deposition are shown in Table 6.
• 2500A of silicon nitride was deposited using a 15 min deposition.
• the channel area was defined by photolithography and Magnetically Enhanced Reactive Ion Etching (MERIE) techniques.
• MERIE Magnetically Enhanced Reactive Ion Etching
• 1.3um thick photoresist and l-line contact aligner were used for photolithography process.
• a 30 sec exposure to MERIE etching was carried out to etch 2500A of silicon nitride including overetching.
• the catalyst/electrical contact layer aiding proton formation and electron liberation is deposited over the whole surface including the columnar void network silicon material remaining in what will became the channels
• 300A of platinum layer was deposited on photoresist by e-gun evaporation
• the photoresist was patterned to form a screen-like or grid-like catalyst layer, which resulted in the metal having this pattern after another lift-off process At this step, this metal is sitting on and is supported by the sacnficial layer
• a solid electrolyte was deposited
• silicon dioxide is used for the proton transport medium
• an ECR-PECVD process was used for deposition
• a spin-coating method was used when Nafion film was employed for the proton transport medium
• Table 9 shows the process condition for silicon dioxide deposition using ECR-PECVD
• the coating procedure was carried out for 30 ⁇ 50sec with the spin speed of 500 ⁇ 4000 rpm, depending the target thickness
• This columnar void network material has a high etching rate at TMAH solution.
• the etchant is also able to uniformly attack the silicon layer as seen in part d of Fig 10a.
• these blotting and etchant-source functions of the columnar void material can be adjusted by adjusting film porosity and through-hole positioning and size.
• a 20min etching in 5% TMAH solution at 75°C resulted in 15 ⁇ 20um deep-channels in the silicon substrate.
• the channels fabricated by this etching allow fuel supply after completion of fuel cell fabrication (Fig. 10a, part 5).
• the channel shapes can be that seen in Fig. 10a, parts 4 and 5.
• the substrate is silicon or other material deposited on a coated or uncoated mechanical substrate such as glass, plastic, metal foil, or other material
• the channel shape will be that seen in Fig.10b, parts 4 and 5.
• the overhanging layer (Si 3 N 4 in Fig.10b) mechanically supports the grid and solid electrolyte.
• Si 3 N 4 is used, it also blocks communication among channels.
• the laminate can be separated as outlined and used as seen in Figs. 1 , 2 and 3.
• the top (reduction grid) layer is deposited on the top of electrolyte and patterned with the same method of patterning used for the other electrode.
• the micro-scale fuel cell fabricated with this invention has a broad range of applications.
• the size of fuel cells produced by this approach outlined here can be reduced to make the cell as small as is needed by the specific application.
• Current technology is easily capable of defining patterns below hundred nanometers. In this size regime, the channel can be defined as "nano-channel".
• a typical PEM fuel cell comprises one or more layered films and separators alternatively stacked with each other.
• This layered sandwich consists of a polymer electrode membrane (PEM), an anode and a cathode, with the PEM film interposed between two electrodes.
• PEM polymer electrode membrane
• Such small fuel cells which can show better efficiency than the usual conventional macro-scale fuel cells, can be on-site power generators in integrated structures with MEMS devices, displays, sensor arrays, detector arrays, and multifunction systems all on the same substrate.
• fuel cells can be stacked onto each other to generate higher voltages or can be connected in parallel to generate higher currents, as preferred. Further, these cells can be fabricated on plastic or other types of laminates and integrated into systems as shown in the CAPS concept of Fig. 3.
• Fuel cells are a promising means for a portable power in mobile electronics due to their lightweight and high energy density. Applications in portable power uses include the full range of consumer electronics, such as cell phones, laptop/palmtop computers, video camcorders, and so on. Integrating the micro-scale fuel cell approach onto lightweight substrate such as plastics, glasses, and foils will allow the powering of light weight displays, sensor and detector structures, telecommunications, and systems incorporating these and other functions.
• the fuel cell structures discussed above can be fabricated with transistors, diodes, or both integrated into the fuel cell layout. With the presence of such electronics, circuits can be integrated with the fuel cell structures to give a smart power laminate. This smart power would on- demand couple fuel cells in the laminate together in parallel or series, or variations thereof to give the instantaneous current, voltage, and power needed in an application. Sensors, detectors, and MEMs devices can also be incorporated into such systems to allow chemical reaction control and fuel diversion and consumption control.
• cavities and channels that can be created by the sacrificial layer approach can be used in display applications.
• these structures can be created with electrodes in the enveloping layers. They can accommodate field emission sources or be filled with gases selected such that, when voltages are impressed on these electrodes, the gases ionize forming a light emitting plasma.
• individual cavities or channels can be used as pixels, separately controlled, to form plasma color displays.
• Control can be built into or on the material in which the cavities or channels have been built. If transistors or diodes are used for this control, active matrix plasma displays can be built. Obviously, this can be accomplished on laminates which are then separated from the mother substrate using also the separation methodology. Such display laminates can be part of the systems shown in Fig. 3, if desired.
• sorting, filtering, and sensor structures can be fabricated even on plastic, glass, or metal foils. Combining these procedures with the separation layer methodologies, means such structures can be formed in and on materials on mother substrates and then separated for use in systems such as in the concept of Fig. 3. Combining these structures with active circuit elements in and on the same materials means these structures can be adaptive and smart.
• Fig. 11 shows an actual DNA sorting structure fabricated using the sacrificial layer materials, design, and fabrication methodology outlined earlier.
• Electrodes or conductive grids incorporated into the enveloping cavity walls, ceiling, or floor. With careful control of electrode or grid spacing, as is possible with the deposited sacrificial layers, these spacings can accommodate molecular units. With the proper choice of self- assembling molecules and electrode and grid materials, molecules can be selected for attachment across these spacings. The molecules can be selected for detection and sensing. For example, single strand DNA can be attached in these channels such as those of Fig. 11 and used to detect incoming DNA samples. Detection, for example, could be attained by a change of conductivity between electrodes. Such detection can be attained for other entities by selection of the molecules immobilized between electrodes. The general scheme is seen in Fig. 12.

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