EP1272022A3 - Mehrschichtige Leiterplatte und Verfahren zu deren Herstellung - Google Patents

Mehrschichtige Leiterplatte und Verfahren zu deren Herstellung Download PDF

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Publication number
EP1272022A3
EP1272022A3 EP02013457A EP02013457A EP1272022A3 EP 1272022 A3 EP1272022 A3 EP 1272022A3 EP 02013457 A EP02013457 A EP 02013457A EP 02013457 A EP02013457 A EP 02013457A EP 1272022 A3 EP1272022 A3 EP 1272022A3
Authority
EP
European Patent Office
Prior art keywords
porous layers
wiring board
multilayer wiring
manufacturing
same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02013457A
Other languages
English (en)
French (fr)
Other versions
EP1272022A2 (de
Inventor
Kenich Ikeda
Toshiyuki Kawashima
Nobuharu Tahara
Kazuo Oouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of EP1272022A2 publication Critical patent/EP1272022A2/de
Publication of EP1272022A3 publication Critical patent/EP1272022A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0116—Porous, e.g. foam
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1147—Sealing or impregnating, e.g. of pores
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
EP02013457A 2001-06-18 2002-06-13 Mehrschichtige Leiterplatte und Verfahren zu deren Herstellung Withdrawn EP1272022A3 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001183318 2001-06-18
JP2001183318 2001-06-18
JP2002003067A JP2003078244A (ja) 2001-06-18 2002-01-10 多層配線基板及びその製造方法
JP2002003067 2002-01-10

Publications (2)

Publication Number Publication Date
EP1272022A2 EP1272022A2 (de) 2003-01-02
EP1272022A3 true EP1272022A3 (de) 2004-09-01

Family

ID=26617101

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02013457A Withdrawn EP1272022A3 (de) 2001-06-18 2002-06-13 Mehrschichtige Leiterplatte und Verfahren zu deren Herstellung

Country Status (4)

Country Link
US (1) US7017264B2 (de)
EP (1) EP1272022A3 (de)
JP (1) JP2003078244A (de)
CN (1) CN1276696C (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039897A (ja) * 2002-07-04 2004-02-05 Toshiba Corp 電子デバイスの接続方法
JP4042785B2 (ja) 2004-02-13 2008-02-06 株式会社村田製作所 電子部品及びその製造方法
WO2006061589A1 (en) * 2004-12-06 2006-06-15 Plastic Logic Limited Electronic devices
WO2006080073A1 (ja) * 2005-01-27 2006-08-03 Matsushita Electric Industrial Co., Ltd. 多層回路基板の製造方法、多層回路基板
JP4276195B2 (ja) * 2005-03-04 2009-06-10 Ｔｄｋ株式会社 基板の保管方法及びコイル部品の製造方法
JP2008085310A (ja) * 2006-08-28 2008-04-10 Clover Denshi Kogyo Kk 多層プリント配線基板
US20080053688A1 (en) * 2006-09-01 2008-03-06 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same
JP2015088750A (ja) * 2013-10-28 2015-05-07 サムソン エレクトロ−メカニックス カンパニーリミテッド． コア基板およびコア基板の製造方法
US9666514B2 (en) * 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
JP2020123633A (ja) * 2019-01-29 2020-08-13 Dic株式会社 配線構造の製造方法
CN110355932B (zh) * 2019-06-21 2020-06-19 西安交通大学 一种多层电介质材料的制备装置及方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303078A (en) * 1962-05-18 1967-02-07 David Wolf Method of making electrical components
GB1476888A (en) * 1974-05-16 1977-06-16 Minnesota Mining & Mfg Method for making printed circuitry
EP0299595A2 (de) * 1987-07-17 1989-01-18 Junkosha Co. Ltd. Mehrschichtschaltungsplatte
JPH05299796A (ja) * 1992-04-22 1993-11-12 Hitachi Chem Co Ltd 多層印刷配線板用接着シートおよびそれを用いた金属張積層板
JPH06209148A (ja) * 1993-01-12 1994-07-26 Matsushita Electric Ind Co Ltd 両面プリント基板およびその製造方法
EP0610929A1 (de) * 1993-02-10 1994-08-17 Unitika Ltd. Filmformende Lösung, daraus enthaltener poröser Film und diesem porösen Film beschichtetes Material
EP0768334A2 (de) * 1995-10-16 1997-04-16 Sumitomo Chemical Company Limited Prepreg, Verfahren zur Herstellung und gedrucktes Leiterplattensubstrat und dessen Verwendung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3677892B2 (ja) 1995-10-16 2005-08-03 住友化学株式会社 プリプレグおよびその製造方法、並びにそれを使用するプリント回路用基材およびプリント回路用積層板
JP3889856B2 (ja) * 1997-06-30 2007-03-07 松下電器産業株式会社 突起電極付きプリント配線基板の製造方法
JP2001127389A (ja) 1999-11-01 2001-05-11 Matsushita Electric Ind Co Ltd 回路基板用絶縁材と回路基板および回路基板の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303078A (en) * 1962-05-18 1967-02-07 David Wolf Method of making electrical components
GB1476888A (en) * 1974-05-16 1977-06-16 Minnesota Mining & Mfg Method for making printed circuitry
EP0299595A2 (de) * 1987-07-17 1989-01-18 Junkosha Co. Ltd. Mehrschichtschaltungsplatte
JPH05299796A (ja) * 1992-04-22 1993-11-12 Hitachi Chem Co Ltd 多層印刷配線板用接着シートおよびそれを用いた金属張積層板
JPH06209148A (ja) * 1993-01-12 1994-07-26 Matsushita Electric Ind Co Ltd 両面プリント基板およびその製造方法
EP0610929A1 (de) * 1993-02-10 1994-08-17 Unitika Ltd. Filmformende Lösung, daraus enthaltener poröser Film und diesem porösen Film beschichtetes Material
EP0768334A2 (de) * 1995-10-16 1997-04-16 Sumitomo Chemical Company Limited Prepreg, Verfahren zur Herstellung und gedrucktes Leiterplattensubstrat und dessen Verwendung

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 018, no. 095 (E - 1509) 16 February 1994 (1994-02-16) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 570 (E - 1623) 31 October 1994 (1994-10-31) *

Also Published As

Publication number Publication date
EP1272022A2 (de) 2003-01-02
JP2003078244A (ja) 2003-03-14
CN1276696C (zh) 2006-09-20
CN1392763A (zh) 2003-01-22
US20020192870A1 (en) 2002-12-19
US7017264B2 (en) 2006-03-28

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