ATE520290T1 - Mehrschichtige leiterplatte und verfahren zur herstellung dazu - Google Patents
Mehrschichtige leiterplatte und verfahren zur herstellung dazuInfo
- Publication number
- ATE520290T1 ATE520290T1 AT06256011T AT06256011T ATE520290T1 AT E520290 T1 ATE520290 T1 AT E520290T1 AT 06256011 T AT06256011 T AT 06256011T AT 06256011 T AT06256011 T AT 06256011T AT E520290 T1 ATE520290 T1 AT E520290T1
- Authority
- AT
- Austria
- Prior art keywords
- layers
- circuit board
- producing
- resin
- layer circuit
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2005343062A JP4835124B2 (ja) | 2005-11-29 | 2005-11-29 | 半導体ic内蔵基板及びその製造方法 |
JP2006004378A JP2007188986A (ja) | 2006-01-12 | 2006-01-12 | 多層回路基板及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
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ATE520290T1 true ATE520290T1 (de) | 2011-08-15 |
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AT06256011T ATE520290T1 (de) | 2005-11-29 | 2006-11-23 | Mehrschichtige leiterplatte und verfahren zur herstellung dazu |
Country Status (3)
Country | Link |
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US (2) | US8188375B2 (de) |
EP (1) | EP1791409B1 (de) |
AT (1) | ATE520290T1 (de) |
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-
2006
- 2006-11-22 US US11/603,884 patent/US8188375B2/en active Active
- 2006-11-23 AT AT06256011T patent/ATE520290T1/de not_active IP Right Cessation
- 2006-11-23 EP EP06256011A patent/EP1791409B1/de active Active
-
2009
- 2009-12-08 US US12/632,948 patent/US8530752B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP1791409A1 (de) | 2007-05-30 |
US20070119541A1 (en) | 2007-05-31 |
EP1791409B1 (de) | 2011-08-10 |
US20100083490A1 (en) | 2010-04-08 |
US8188375B2 (en) | 2012-05-29 |
US8530752B2 (en) | 2013-09-10 |
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