EP1258036A1 - Verfahren zur herstellung einer ferroelektrischen schicht - Google Patents
Verfahren zur herstellung einer ferroelektrischen schichtInfo
- Publication number
- EP1258036A1 EP1258036A1 EP01911688A EP01911688A EP1258036A1 EP 1258036 A1 EP1258036 A1 EP 1258036A1 EP 01911688 A EP01911688 A EP 01911688A EP 01911688 A EP01911688 A EP 01911688A EP 1258036 A1 EP1258036 A1 EP 1258036A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- ferroelectric
- ferroelectric layer
- layer
- substrate
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims abstract description 33
- 230000005684 electric field Effects 0.000 claims abstract description 29
- 238000003860 storage Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 32
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 22
- 238000010438 heat treatment Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 19
- 229910052697 platinum Inorganic materials 0.000 claims description 13
- 229910000510 noble metal Inorganic materials 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical group [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 claims description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims description 2
- 239000013598 vector Substances 0.000 abstract description 13
- 238000002425 crystallisation Methods 0.000 abstract description 6
- 210000000352 storage cell Anatomy 0.000 abstract description 2
- 230000010287 polarization Effects 0.000 description 33
- 239000007789 gas Substances 0.000 description 10
- 238000005496 tempering Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- -1 platinum metals Chemical class 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- 150000003624 transition metals Chemical class 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Definitions
- the present invention relates to a method for producing a ferroelectric layer.
- the present invention relates in particular to a method for producing a ferroelectric layer for an integrated memory arrangement and to a method for producing a storage capacitor.
- Ferroelectric memory arrangements have the advantage over conventional memory arrangements, such as DRAMs and SRAMs, that the stored information is not lost, but remains stored even when the voltage or power supply is interrupted.
- storage capacitors for storing the information are generally also used in ferroelectric storage arrangements.
- a ferroelectric material is used between the electrodes of the capacitor (for example SrBi 2 Ta0 9 (SBT) or Pb (Zr, Ti) 0 3 (PZT)).
- SBT SrBi 2 Ta0 9
- Pb Zr, Ti 0 3
- the non-volatility of ferroelectric memory arrangements is based on the fact that, in ferroelectric materials, the polarization impressed by an external electric field is essentially retained even after the external electric field has been switched off.
- the signal that can be read from the storage capacitors is the higher the higher the polarization that can be impressed into the ferroelectric material. In order to be able to guarantee a sufficiently high signal when reading out a storage capacitor, a high remanent polarization between the electrodes of the capacitor is necessary.
- Ferroelectric materials are characterized in that they have microstructural domains that have an electrical polarization.
- the alignment this polarization is linked to the orientation of the respective crystal lattice.
- the polarization is oriented in the direction of the crystallographic [001] axis.
- the vector of the electrical polarization lies mainly parallel to the a-axis ([100] orientation) or the b-axis ([010] orientation).
- both axes are almost equivalent, since it is a pseudotetragonal grid.
- the domains and thus the vectors of the electrical polarization are also randomly oriented. If an electrical field is now applied from the outside, the polarization vectors of the individual domains are aligned so that they are as parallel as possible to the external field applied. For domains whose crystal is oriented so that the [100] axis is perpendicular to the plates of the capacitor, this means that the entire polarization vector of the domain runs parallel to the external field. For domains with a different orientation, only the component of the polarization vector parallel to the external field is relevant.
- the macroscopically measurable total polarization which is perpendicular to the electrodes of the capacitor, is the sum of the individual polarizations of the domains.
- a high remanent polarization is of crucial importance for the use of ferroelectric thin films in highly integrated components, such as in integrated memory arrays with structure sizes smaller than 0.25 ⁇ m, since not only the area of the capacitor is very small, but these structures are related their volume also have a very large surface area.
- ferroelectric materials always show damage that is caused by the structuring and that leads to a reduction in the remanent polarization.
- other processes that are indispensable in the production of integrated components e.g. forming gas tempering, TEOS oxide / Si0 2 deposition, etc.
- the orientation of the ferroelectric material i.e. for example, to produce as much [100] or [010] -oriented material as possible in the case of SBT or as much [001] -oriented material as possible in the case of PZT, the polarization vectors of which are oriented perpendicular to the electrodes of the storage capacitor.
- other orientations within the a, b plane e.g. [110]
- the polarization is still significantly higher than if there are many domains with an alignment along the c-axis.
- a method for producing a ferroelectric layer which has the following steps:
- a heat treatment is carried out in the presence of an electric field, which is aligned along a predetermined direction, so that the material is converted into a ferroelectric phase.
- the method according to the invention has the advantage that crystallization of the material in accordance with the predetermined direction is facilitated by the application of an external electric field. Without wishing to be limited, the inventors believe that this can be explained by the fact that the crystallization will always proceed in the direction in which a state with the lowest Gibb's free energy is achieved. In the normal case, this will be a material with randomly oriented crystals, since a state with very high entropy can be created in this way. However, if you put an electrical one from the outside Field arrives, so there is an additional energy term that describes the interaction between the external field and the ferroelectric polarization. This energy term usually becomes minimal when the polarization of the ferroelectric material that is produced runs parallel to the external field.
- a ferroelectric material can be produced in which the crystallization, for example in the case of SBT, is preferably oriented in the [100], [010] or [110] direction or in the case of PZT in the [001] direction ,
- a suitable choice of the alignment of the field applied during crystallization can produce ferroelectric layers, the domains of which are preferably aligned such that their polarization vectors are perpendicular to the electrodes of the storage capacitor in a storage cell. As a result, the entire
- Polarization vector of the domain runs essentially parallel to the field of the storage capacitor and a correspondingly high remanent polarization is generated.
- the ferroelectric layer is a strontium bismuth tantalate layer (SBT, SrBi 2 Ta 2 0 9 ) and the heat treatment is carried out at a temperature between 500 ° and 820 ° C., preferably between 700 ° and 800 ° C. In particular, it is preferred if the heat treatment is carried out at a temperature between 700 ° and 750 ° C.
- the ferroelectric layer is a lead zirconate titanate layer (PZT, Pb (Zr, Ti) 0 3 ) and the heat treatment is carried out at a temperature between 400 ° and 600 ° C.
- the heat treatment is preferably carried out over a period of 5 to 90 minutes, preferably 10 to 30 minutes. It is further preferred if the field strength of the electric field is between 1 to 100 kV / cm, preferably between 20 and 40 kV / cm.
- the substrate is used as an electrode to apply the electrical field. It is particularly preferred if a noble metal electrode, in particular a platinum electrode, is provided on the surface of the substrate.
- a conductive plate is used as the second electrode, which is arranged above the material of the subsequent ferroelectric layer.
- a plasma is used as the second electrode, which is generated above the material of the subsequent ferroelectric layer. The use of a plasma above the later ferroelectric layer has the advantage that the plasma reaches right up to the material, so that the applied electric field can be applied directly to the material. It is preferred if the plasma is generated by an alternating frequency or voltage pulses.
- the substrate is immersed in the plasma by means of voltage pulses. If an additional conductive plate is used, there will generally be a distance between the plate and the material in which an electrical field is also present, with the result that a higher voltage must be applied to build up the electrical field.
- the material of the ferroelectric layer is applied to the substrate by a CVD method. It is particularly preferred if the material of the subsequent ferroelectric layer is applied to the substrate as an essentially amorphous film.
- 1 - 8 a method for producing a ferroelectric layer according to a first embodiment of the invention in the context of producing a ferroelectric memory cell
- FIG. 9 shows a further method for producing a ferroelectric layer according to a second exemplary embodiment of the invention.
- FIG. 10 shows a further method for producing a ferroelectric layer according to a third exemplary embodiment of the invention.
- the transistor 1 shows a silicon substrate 1 with transistors 4 that have already been completed.
- the transistors 4 each have two diffusion regions 2, which are arranged on the surface of the silicon substrate 1.
- the channel zones are arranged between the diffusion regions 2 of the transistors 4 and are separated by the gate oxide from the gate electrodes 3 on the surface of the silicon substrate 1.
- the transistors 4 are produced by the methods known in the prior art, which are not explained in more detail here.
- An insulating layer 5, for example an SiO 2 layer, is applied to the silicon substrate 1 with the transistors 4. Depending on the method used for the production of the transistors 4, several insulating layers can also be applied. The resulting structure is shown in Fig. 1.
- the contact holes 6 are then produced by a photo technique. These contact holes 6 establish a connection between the transistors 4 and the storage capacitors still to be produced.
- the contact holes 6 are produced, for example, by anisotropic etching using fluorine-containing gases. The resulting structure is shown in Fig. 2.
- CMP step Chemical Mechanical Polishing
- depressions are formed in the insulating layer 5 overlapping with the contact holes 6. These depressions are now filled with barrier material 8, for example iridium oxide. This takes place in that the barrier material 8 is deposited over the entire area and a further CMP step is subsequently carried out. Suitable CMP processes are described, for example, in the application, to which reference is hereby made.
- the resulting structure is shown in Fig. 4. A nated the lower electrode of the storage capacitors is blanket deposited on the in Fig. Structure shown. 4 Because of their good
- the noble metal layer 9, for example platinum, is applied by a sputtering process with a sputtering temperature of approximately 550 ° C.
- the thickness of the noble metal layer 9 is approximately 100 nm.
- the resulting structure is shown in FIG. 5.
- a ferroelectric layer follows.
- An SBT film 10 is deposited on the substrate prepared in this way using a CVD process.
- the CVD process is carried out at a substrate temperature of 385 ° C and a chamber pressure of about 1200 Pa.
- the oxygen content in the gas mixture is 60%.
- the SBT film 10 is deposited as an amorphous film, which is the result of X-ray or
- Electron beams essentially show no crystal structures. Accordingly, the SBT film 10 has essentially no ferroelectric properties. The resulting structure is shown in Fig. 6.
- the deposited, amorphous SBT 10 is then annealed at a temperature between 700 to 750 ° C. for 10 to 30 minutes.
- An external electric field 11 is applied during the heat treatment (tempering). The order of magnitude of the externally created field 11 should preferably be
- an additional conductive plate 12 is placed directly over the SBT film 10 in this embodiment of the present invention.
- the distance between the conductive plate 12 and the SBT film 10 is about 1 mm.
- an electric field is now generated which is oriented perpendicular to the platinum layer 9 and the plate 12.
- the voltage applied between the conductive plate 12 and the platinum layer 9 is approximately 30 kV.
- the pressure of the N / O 2 atmosphere which is used for tempering in this exemplary embodiment, is reduced to approximately 0.1 to 10 Pa. If instead of a N 2/0 2 atmosphere, a He / 0 2 atmosphere used can be carried out at a much higher pressure. Depending on the application, the annealing can also be carried out in a pure He atmosphere.
- the domains of the SBT layer 10 that are formed are preferably aligned in the predetermined direction of the electric field 11. Accordingly, a ferroelectric SBT layer can be produced in which the domains are preferably oriented in the [100], [010] or [110] direction. The domains are aligned so that their
- Polarization vectors are perpendicular to the electrodes of the storage capacitor that is still to be produced, which results in a correspondingly high remanent polarization.
- the resulting structure is shown in Fig. 7.
- the upper electrode of the storage capacitors is then deposited over the entire area onto the structure shown in FIG. 7.
- electrically conductive oxides 4d and 5d transition metals in particular platinum metals (Ru, Rh, Pd, Os, Ir, Pt) and in particular platinum itself, are used as electrode material.
- the Precious metal layer 13, for example platinum, is also applied by a sputtering process with a sputtering temperature of approximately 550 ° C. After the upper electrode has been applied, annealing is carried out again in order to heal the boundary layer between the ferroelectric layer 10 and the upper electrode 13.
- the three layers, noble metal layer 13, ferroelectric layer 10 and the noble metal layer 9 are then structured with the aid of anisotropic etching processes, so that the structure shown in FIG. 8 is produced. This essentially completes the memory cells.
- the methods used are part of the prior art and are not explained in more detail here.
- a plasma is provided above layer 10 in the second embodiment of the present invention.
- the first step a) of the method according to the second embodiment of the present invention corresponds to what has been explained in connection with FIGS. 1 to 6, so that a repetition can be omitted.
- the amorphous SBT layer 10 is in turn annealed min at a temperature between 700 to 750 ° C for 1 0 to 30.
- An external electric field 11 is applied during the heat treatment (tempering).
- the size of the externally created field 11 should be preferably correspond to the coercive field strength of the later ferroelectric layer, ie 30 kV / cm for SBT, for example.
- the substrate is introduced into a parallel plate reactor 14 in this embodiment.
- the reactor 14 essentially comprises a vacuum chamber with an inlet for the He / O 2 gas mixture and two parallel electrodes 15 and 16.
- the substrate 1 is positioned on the lower electrode 15. By one on the electrodes 15,
- the He / 0 2 gas mixture between the electrodes 15, 16 is brought to glow discharge and a plasma 17 is created.
- the much lighter electrons in comparison can follow the high frequency field between the electrodes 15, 16 and reach the electrodes 15, 16 much faster.
- the plasma 17 charges positively with respect to the electrodes 15, 16 and with respect to the substrate 1, so that an electrical field is generated within the SBT layer, which serves to align the domains within the SBT layer.
- the electrical potential of the plasma can be determined by a suitable choice of the process parameters pressure, RF power, external bias, gas flow, gas composition
- Suitable parameters are, for example: cathode temperature 450 ° C, RF power: 1200 W, bias power: 450 W, He / 0 2 - flow: 80 - 150 sccm, pressure: 0.6 - 3.4 Pa.
- the upper electrode of the storage capacitors is deposited over the entire surface.
- annealing is carried out in order to heal the boundary layer between the ferroelectric layer 10 and the top electrode 13.
- the ferroelectric layer 10 and the noble metal layer 9 are then structured with the aid of anisotropic etching processes, so that the structure shown in FIG. 8 is again formed.
- the plasma is generated by a continuous supply of RF power.
- the plasma is generated by voltage pulses.
- the first step a) of the method according to the third embodiment of the present invention in turn corresponds to what was explained in connection with FIGS. 1 to 6, so that repetition can be dispensed with.
- the amorphous SBT layer 10 is annealed at a temperature between 700 to 750 ° C for 10 to 30 min.
- An external electric field 11 is applied during the heat treatment (tempering). To generate the external electric field 11, the substrate is introduced into a reactor 18 in this embodiment.
- the reactor 18 essentially comprises a vacuum chamber with an inlet 19 for the He / O 2 gas mixture and a carrier 20 for the substrate 1.
- the inlet 19 has a disk 21 on its side facing the carrier 20, to which a modulator 22 connects Positive voltage pulses are applied.
- the walls of the vacuum chamber, the carrier 20 and thus the substrate 1, however, are connected to ground.
- the pulses of positive voltage ionize the gas molecules and thus generate a plasma 17 in the space above the carrier 20.
- the positive ions within the plasma are accelerated in the direction of the substrate 1 and the plasma expands in the direction of the substrate. As a result, the substrate is immersed in the plasma.
- the plasma can only be generated by the voltage pulses or by an additional plasma source, for example a ECR or microwave source (not shown). If the plasma is generated by an additional plasma source, the voltage pulses mainly serve to immerse the substrate in the plasma. Further details on these so-called “plasma immersion implantation” methods are described, for example, in US Pat. No. 5,911,832 (Denholm et al.).
- a very dense oxygen plasma can be generated, which provides a sufficient number of low-energy oxygen ions for the tempering of the SBT layer.
- the potential of the plasma 17 can be set over a wide range, so that a sufficiently large electric field can be generated for aligning the domains of the SBT layer.
- Heating lamps 23 are also provided for heating the substrate 1 and are arranged above the carrier 20.
- the process parameters can be varied over a wide range: cathode temperature 50 - 700 ° C, HF power 30 - 500 watts, gas flow 100 - 700 sccm, plasma density 3 10 11 ions / cm 3 , ion flow> 10 16 ions / (cm 2 min), pressure 0.1-3 Torr.
- the upper electrode of the storage capacitors is again deposited over the entire surface.
- annealing is carried out in order to heal the boundary layer between the ferroelectric layer 10 and the top electrode 13.
- the three layers, noble metal layer 13, ferroelectric layer 10 and the noble metal layer 9 are then structured with the aid of anisotropic etching processes, so that the structure shown in FIG. 8 is again produced.
- the processes according to the invention have the advantage that ferroelectric layers can be produced by the electrical field applied during the crystallization, the domains of which are preferably aligned such that their Polarization vectors are perpendicular to the electrodes of the storage capacitor in a memory cell.
- the entire polarization vector of the domain runs essentially parallel to the field of the storage capacitor during the operation of the memory arrangement, and a correspondingly high remanent polarization is generated.
- the signal that can be read from the storage capacitors is correspondingly high.
- the lower electrode 9, the ferroelectric layer 1 and the upper electrode 13 have been structured substantially simultaneously by one or more anisotropic etching processes.
- the lower electrode 9 can be structured by an etching process and / or a CMP process even before the ferroelectric material is applied.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10008617A DE10008617A1 (de) | 2000-02-24 | 2000-02-24 | Verfahren zur Herstellung einer ferroelektrischen Schicht |
DE10008617 | 2000-02-24 | ||
PCT/EP2001/002035 WO2001063658A1 (de) | 2000-02-24 | 2001-02-22 | Verfahren zur herstellung einer ferroelektrischen schicht |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1258036A1 true EP1258036A1 (de) | 2002-11-20 |
Family
ID=7632216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01911688A Withdrawn EP1258036A1 (de) | 2000-02-24 | 2001-02-22 | Verfahren zur herstellung einer ferroelektrischen schicht |
Country Status (6)
Country | Link |
---|---|
US (1) | US6790676B2 (de) |
EP (1) | EP1258036A1 (de) |
KR (1) | KR100533698B1 (de) |
DE (1) | DE10008617A1 (de) |
TW (1) | TW525196B (de) |
WO (1) | WO2001063658A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100562499B1 (ko) * | 2003-02-21 | 2006-03-21 | 삼성전자주식회사 | 강유전체 기억 소자 및 그 제조 방법 |
US6967365B2 (en) * | 2003-07-15 | 2005-11-22 | Texas Instruments Incorporated | Ferroelectric memory cell with angled cell transistor active region and methods for fabricating the same |
KR100634548B1 (ko) * | 2005-07-13 | 2006-10-13 | 삼성전자주식회사 | 강유전막 상에서 귀금속막의 증착률을 높일 수 있는 물질막제조방법, 이 방법을 이용한 강유전막 커패시터 제조 방법및 이 방법으로 형성된 강유전막 커패시터, 이러한강유전막 커패시터를 포함하는 반도체 메모리 장치 및 그제조 방법 |
WO2008072827A1 (en) * | 2006-12-15 | 2008-06-19 | University Of Seoul Foundation Of Industry-Academic Cooperation | Ferroelectric material and method of forming ferroelectric layer using the same |
EP2717343B1 (de) * | 2012-10-08 | 2014-09-24 | Christian-Albrechts-Universität zu Kiel | Magnetoelektrischer Sensor und Verfahren zu seiner Herstellung |
US10505040B2 (en) * | 2017-09-25 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device having a gate with ferroelectric layer |
US20210408049A1 (en) * | 2020-06-29 | 2021-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor chip |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0409104B1 (de) * | 1989-05-18 | 1996-05-01 | Sony Corporation | Verfahren zur Kontrolle der ferroelektrischen Domänen eines nichtlinearen optischen Substrates |
JP3169599B2 (ja) * | 1990-08-03 | 2001-05-28 | 株式会社日立製作所 | 半導体装置、その駆動方法、その読み出し方法 |
JPH0685173A (ja) * | 1992-07-17 | 1994-03-25 | Toshiba Corp | 半導体集積回路用キャパシタ |
US5525528A (en) * | 1994-02-23 | 1996-06-11 | Ramtron International Corporation | Ferroelectric capacitor renewal method |
JP3152859B2 (ja) | 1994-09-16 | 2001-04-03 | 株式会社東芝 | 半導体装置の製造方法 |
US6194751B1 (en) * | 1994-11-15 | 2001-02-27 | Radiant Technologies, Inc | Ferroelectric based memory devices utilizing low Curie point ferroelectrics and encapsulation |
JPH09232532A (ja) * | 1996-02-22 | 1997-09-05 | Toshiba Corp | 強誘電体メモリの製造方法 |
JP3435966B2 (ja) * | 1996-03-13 | 2003-08-11 | 株式会社日立製作所 | 強誘電体素子とその製造方法 |
EP0957516A1 (de) * | 1996-08-20 | 1999-11-17 | Hitachi, Ltd. | Herstellungsverfahren eines oxiddielektrikumbauelement, sowie speicher und dieses bauelement verwendende halbleiterbauteil |
US5911832A (en) | 1996-10-10 | 1999-06-15 | Eaton Corporation | Plasma immersion implantation with pulsed anode |
US6096597A (en) * | 1997-01-31 | 2000-08-01 | Texas Instruments Incorporated | Method for fabricating an integrated circuit structure |
KR100269314B1 (ko) * | 1997-02-17 | 2000-10-16 | 윤종용 | 플라즈마처리를이용한반도체장치의커패시터제조방법 |
AUPO620197A0 (en) | 1997-04-14 | 1997-05-08 | Leung, Chi Keung | Extra byte propeller |
US6322849B2 (en) * | 1998-11-13 | 2001-11-27 | Symetrix Corporation | Recovery of electronic properties in hydrogen-damaged ferroelectrics by low-temperature annealing in an inert gas |
JP2000031151A (ja) * | 1999-07-05 | 2000-01-28 | Seiko Epson Corp | 半導体装置 |
-
2000
- 2000-02-24 DE DE10008617A patent/DE10008617A1/de not_active Withdrawn
-
2001
- 2001-02-22 EP EP01911688A patent/EP1258036A1/de not_active Withdrawn
- 2001-02-22 KR KR10-2002-7011031A patent/KR100533698B1/ko not_active IP Right Cessation
- 2001-02-22 US US10/204,830 patent/US6790676B2/en not_active Expired - Fee Related
- 2001-02-22 WO PCT/EP2001/002035 patent/WO2001063658A1/de active IP Right Grant
- 2001-02-23 TW TW090104171A patent/TW525196B/zh not_active IP Right Cessation
Non-Patent Citations (1)
Title |
---|
See references of WO0163658A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2001063658A1 (de) | 2001-08-30 |
KR20020086568A (ko) | 2002-11-18 |
TW525196B (en) | 2003-03-21 |
US6790676B2 (en) | 2004-09-14 |
US20030138977A1 (en) | 2003-07-24 |
DE10008617A1 (de) | 2001-09-06 |
KR100533698B1 (ko) | 2005-12-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69833168T2 (de) | Halbleiter-Speicherbauteil mit ferroelektrischem Dünnfilm | |
DE69736895T2 (de) | Verfahren zur herstellung eines halbleiterspeichers | |
EP1128428B1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
DE19649670C2 (de) | Verfahren zur Herstellung eines Kondensators einer Halbleitervorrichtung und auf diese Weise hergestellter Kondensator | |
DE19613669B4 (de) | Verfahren zur Herstellung eines Halbleiterelements mit einer Platinschicht | |
EP1258036A1 (de) | Verfahren zur herstellung einer ferroelektrischen schicht | |
DE19963500C2 (de) | Verfahren zum Herstellen einer strukturierten metalloxidhaltigen Schicht, insbesondere einer ferroelektrischen oder paraelektrischen Schicht | |
DE10053171C2 (de) | Verfahren zum Herstellen einer ferroelektrischen oder paraelektrischen metalloxidhaltigen Schicht und eines Speicherbauelements daraus | |
EP1307906B1 (de) | Strukturierung ferroelektrischer schichten | |
DE10125370C1 (de) | Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einem stark polarisierbaren Dielektrikum oder Ferroelektrikum | |
EP1111083B1 (de) | Verfahren zur Herstellung einer strukturierten Metallschicht | |
EP1114451A1 (de) | Mikroelektronische struktur, verfahren zu deren herstellung und deren verwendung in einer speicherzelle | |
DE10064068A1 (de) | Verfahren zur Herstellung von Kondensatoren von Halbleitereinrichtungen | |
EP1138065A1 (de) | Verfahren zum herstellen einer strukturierten metalloxidhaltigen schicht | |
EP0902461A2 (de) | Verfahren zur Erzeugung von Strukturen mit einem hohen Aspektverhältnis | |
EP1277230B1 (de) | Verfahren zur herstellung von kondensatorstrukturen | |
DE19851280A1 (de) | Verfahren zum Herstellen einer strukturierten metalloxidhaltigen Schicht | |
WO2001001461A1 (de) | Verfahren zur herstellung einer strukturierten schicht | |
DE102005008391B3 (de) | FeRAM-Speicherzelle zum Speichern von mehr als zwei Zuständen und Verfahren zum Herstellen einer solchen | |
DE19957122C2 (de) | Verfahren zur Herstellung eines ferroelektrischen Kondensators und ferroelektrischer Kondensator | |
DE19929723B4 (de) | Verfahren zur Herstellung einer Elektrode | |
DE10009146A1 (de) | Herstellungsverfahren sehr dünner ferroelektrischer Schichten | |
WO2000046843A1 (de) | Mikroelektronische struktur | |
DE10010284C2 (de) | Verfahren zur Herstellung eines Halbleiterbauelements mit einem Kondensator |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20020820 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: WINTERAUER, FRANZ Inventor name: HOEPFNER, JOACHIM Inventor name: SCHINDLER, GUENTHER Inventor name: HARTNER, WALTER Inventor name: CERVA, HANS Inventor name: HINTERMAIER, FRANK Inventor name: WEINRICH, VOLKER |
|
RBV | Designated contracting states (corrected) |
Designated state(s): AT BE CH DE GB IE LI |
|
17Q | First examination report despatched |
Effective date: 20061012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20090901 |