EP1234328A2 - Procede pour le traitement thermique rapide de substrats - Google Patents

Procede pour le traitement thermique rapide de substrats

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Publication number
EP1234328A2
EP1234328A2 EP00992125A EP00992125A EP1234328A2 EP 1234328 A2 EP1234328 A2 EP 1234328A2 EP 00992125 A EP00992125 A EP 00992125A EP 00992125 A EP00992125 A EP 00992125A EP 1234328 A2 EP1234328 A2 EP 1234328A2
Authority
EP
European Patent Office
Prior art keywords
substrate
hot gas
gas stream
temperature
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00992125A
Other languages
German (de)
English (en)
Inventor
Lynn David Bollinger
Iskander Tokmouline
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jetek Inc
Original Assignee
Jetek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/689,307 external-priority patent/US6467297B1/en
Application filed by Jetek Inc filed Critical Jetek Inc
Publication of EP1234328A2 publication Critical patent/EP1234328A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring

Definitions

  • This invention relates to semiconductor manufacturing generally and more specifically to thermal processing of substrates used to make semicon- ductor devices. Background Of The Invention
  • Device applications include diffusion and annealing of implanted semiconductors to form high conductivity structures in substrates; annealing of a number of different materials used in CMOS logic devices and DRAM memory devices as well as processing specialty compound semiconductor devices.
  • a general requirement for many such advanced devices is to very rapidly raise the temperature of the surface and then very rapidly cool-down the surface to enable a diffu- sion or anneal process without degrading other characteristics of the device materials.
  • the two methods of driving the doping material into the single crystal silicon so that the doped crystal becomes highly conductive are: (1 ) implantation of the doping material into the silicon by accelerating the doping atoms into the silicon surface with sufficient energy, followed by a high temperature anneal to repair the crystal damage by the implant process; and (2) diffusion of the doping atoms into the silicon by having a high concentration of doping material on the silicon surface and raising the silicon temperature so that the doping material diffuses into the silicon.
  • the seed doping material may be in a layer deposited on the silicon surface or may be in the gas at the surface of the wafer.
  • the diffusion rate of a doping material into silicon follows an exponential type dependence on temperature.
  • a high temperature requirement e.g., 1200°C
  • the doping atoms will rapidly diffuse into the silicon and in a short time a shallow highly conductive area can be obtained.
  • very shallow doping requires a short time duration high temperature pulse.
  • the pulse would be a spike that rapidly rises to, and falls from, a high temperature.
  • a short high temperature pulse is required to maintain a sharply defined, shallow conductive area having a steep concentration gradient at the conductive area boundary.
  • a means is needed for a well controlled, very rapid, high heat input to the wafer.
  • High electrical conductivity structures in silicon semiconductor devices are in a non-equilibrium concentration regime. The concentration of doping atoms in the silicon structure is greater than the solubility of the doping material at ambient, operating temperature.
  • the doping concentration is set by the solubility of the doping atoms in silicon at the peak process temperature.
  • a higher concentration of doping atoms in a single crystal structure gives a higher electrical conductiv- ity.
  • Ion implantation and anneal A high current, low energy ion implanter implants doping atoms to the required depth and concentration followed by a rapid thermal anneal of the damage.
  • Two rapid anneal methods now used are radiant Rapid Thermal Processing (RTP) and fast furnace anneal RTP.
  • RTP radiant Rapid Thermal Processing
  • RTP fast furnace anneal
  • Radiant RTP Heat lamps rapidly heat the silicon wafer. Cooling is by contact with a cooled wafer holding plate. Radiant energy output from the lamps is largely in the Infra-Red (IR) range so that heating results from coupling mechanisms for IR energy to silicon. The primary coupling mechanism for heating silicon wafers is to free electrons that occur at temperatures above 700°C. Issues with Radiant RTP for future generations of semiconductor devices are:
  • Plasma immersion and anneal Instead of the scan implantation method used by ion implanters, the wafer is placed in a plasma that contains the doping material. A voltage pulse is applied to the wafer with respect to the plasma potential that drives doping ions into the wafer. A rapid thermal anneal removes the crystal damage from the plasma implant.
  • the advantage of this approach is that it could provide ion implantation at a lower cost. Issues with this approach are the same as those set forth above for the ion implant technique as well as those above for the RTP anneal. In addition, problems include:
  • PILD Projection Gas Immersion on Laser Doping
  • Rapid thermal pas doping The wafer is placed in a furnace containing the doping material as a gas. A rapid temperature rise diffuses the doping material into the silicon. The fundamental issue with this approach for future device generations requiring shallow implants and diffusion is that temperature rise time and cool down is limited. Maximum rise times of 100°C using forced air oven convection have been reported.
  • CMOS gate dielectric applications include oxide materials such as tantalum oxide.
  • the tantalum oxide can be annealed at a temperature less than 800°C. However, if the temperature rise and cool-down time are not sufficiently rapid, then a silicon oxide layer will form at the silicon / tantalum oxide interface partially negating the effect of the high-k tantalum oxide dielectric.
  • a substrate is exposed to a hot gas stream that is operated in a regime that yields a large thermal gradient through the substrate thickness during processing and is operated for a time period that is sufficiently short to enable a very rapid cool down of the areas treated by the hot gas stream.
  • This processing regime is obtained by a combination of high heat flux delivered to the substrate and low exposure time of any location on the sub- strate to the hot gas heat flux.
  • heating power delivered to the substrate would be in a range of greater than about 5x10 7 Watts/m 2 up to about 10 9 W/m 2 .
  • the exposure time to the hot gas stream is chosen according to the peak temperature needed and the heating flux used and would be generally less than about 8ms.
  • the uniqueness of our invention is not just the parameter range of heat flux and exposure time but that in the properly chosen combination, thermal processing can be done in a regime that preserves a large temperature differential through the substrate thickness. This will give very high heating and cooling, of the order of about -10 5 °C/sec, with no substrate damage or deformation. It is not only critical that exposure times be in the range to give a large temperature gradient through the substrate thickness but also that in a given RTP process the exposure times are stable and have very small variations.
  • RTP Processing
  • Heating of the substrate with uniform thermal processing can be achieved in a manner that is insensitive to the surface characteristics of the substrate such as patterning and material layers.
  • a heating method for low temperature applications can be employed using a very rapid RTP.
  • This enables one to anneal and activate thin layers (e.g. ⁇ 1 micron) in temperature ranges less than 1000° C/sec.
  • thin layers e.g. ⁇ 1 micron
  • a particularly high degree of temperature control and uniformity better than 1% with a corresponding high process throughput, is achievable, both within a wafer and from wafer-to-wafer.
  • substrate heating can be done in two different regimes characterized by a nearly constant tempera- ture through the substrate thickness during heating and cooling; and by a large temperature differential through the substrate thickness.
  • heating of a substrate is done by gas conduction wherein the gas heating power density is sufficiently high, preferably above about 5x10 7 W/m 2 and with the dwell time of the substrate being treated within the hot gas stream being sufficiently low to create a high temperature gradient within the substrate.
  • gas heating power density is sufficiently high, preferably above about 5x10 7 W/m 2 and with the dwell time of the substrate being treated within the hot gas stream being sufficiently low to create a high temperature gradient within the substrate.
  • Sharply defined, shallow, high conductivity structures in silicon can be formed by rapidly bringing the silicon temperature to temperatures greater than 1100°C followed by very rapid cooling.
  • RTP Thermal Process
  • a very high conductivity could be obtained by an extremely fast spike-like temperature rise and cooling profile that instantaneously raises the surface of the substrate, for silicon about 1410°C, to obtain a solubility concentration for liquid silicon. Heating by gas conduction avoids the surface optical emissivity dependence issue of the laser and radiant RTP methods. Heat transfer to the substrate is then independent of patterning used in manufacturing microelectronic devices.
  • a preferable approach to obtain the high heat flux is to use a gas stream that is smaller than standard substrate sizes, such as 200mm to 300mm diameter silicon wafers. Uniform thermal treatment is then obtained with a programmed movement of the substrate relative to the hot gas stream. To avoid hydrodynamic stabilization is- sues arising when one moves a hot gas stream, it is preferable, though not absolutely required, to move the substrate through a stationary hot gas stream.
  • Thermal treatment includes annealing or activation of the substrate surface and deposited layers, and doping of the substrate to give electrically con- ductive structures.
  • Single crystal doped structures may be obtained using hot gas RTP by:
  • a hard mask such a silicon nitride of oxide, which would be stripped in a later step, would provide the patterning for the diffusion of the doping atoms into the substrate.
  • Thermal treatment of this invention differs fundamentally from hot ov- ens approaches that use forced, convective gas flow to heat the substrate.
  • the gas temperature does not greatly exceed the peak temperature reached by the substrate during processing.
  • the temperature of the gas stream at the boundary layer over the substrate will be in the range of 2 to 30 times the peak temperature reached by the substrate during processing. It is this large temperature gradient established by the invention near the substrate surface that enables a very rapid heat transfer of this invention.
  • an object of the invention to provide a process for a rapid thermal treatment involving fast heating and fast cooling of the gas treated areas of a substrate used to make semiconductor devices while using a very high temperature hot gas stream whereby excellent doping and annealing processes can be carried out to manufacture shallow substrate structures having sharp doping boundaries.
  • Figure 1 is a schematic view of the concept of processing a substrate using an intense hot gas stream to obtain very rapid heating and cool-down of the substrate surface exposed to the hot gas treatment area in accordance with the invention.
  • Figure 2 is a schematic side plan view of an atmospheric plasma proc- essing system that can be used to generate the hot gas stream needed for very rapid heating and cooling in accordance with the invention.
  • Figure 3A is a schematic side cross-section view of a non-contact vortex type substrate holder with which a rapid thermal processing technique in accordance with the invention can be practiced.
  • Figure 3B is a bottom view of the substrate holder of Figure 3A.
  • Figure 4 is a plot of modeled heating and cooling rates for two different velocities of a substrate as it passes through a hot gas stream and shows the method for controlling the peak temperature in accordance with the invention.
  • Figure 5 is schematic view of a simple model for heat transfer to a sub- strate from a hot gas stream.
  • Figure 6 is a plot of modeled heating and cooling rates for a silicon wafer in the regime of a low temperature differential through the wafer thickness of Figure 5 in comparison with heating and cooling rates obtained by a conventional radiant RTP process.
  • Figure 7 is a diagram of modeled plots of temperature differential through the thickness of a silicon wafer for different input heating powers and gas stream traversals or velocities of the substrate with the same front surface peak temperature of the silicon.
  • Figure 8 is a modeled plot of heating and cooling rates for the front sur- face of a silicon wafer in the regime of a large temperature differential through the wafer thickness and with heating and cooling rates of 10 5 o C/sec.
  • Figure 9 is a diagram of modeled plots for cooling rates of a silicon wafer in two operating regimes of respectively low and high temperature differentials through the wafer thickness. Front and back wafer surfaces vs. time are shown.
  • Figure 10 is a diagram of modeled plots for cooling rates at three different input heating powers and velocities that yield the same front surface temperature.
  • Figure 11 is a diagram of a modeled plot showing very rapid heating and cooling rates for a silicon wafer with a relatively low peak temperature for a low temperature very fast RTP anneal process.
  • Figure 12 is a schematic representation of a single linear pass of a hot gas treatment area across a circular substrate.
  • Figure 13 is a diagram view of a thermal treatment profile, perpendicular to the scan direction, as would be obtained from a single linear pass of the substrate through a hot gas treatment area in accordance with the invention.
  • Figure 14 is a diagram view of overlapped multiple linear scans where the overlap distance is comparable to the width of a single scan treatment profile.
  • Figure 15 is a diagram view of overlapped multiple linear scans where the overlap distance is small compared to the width of a single scan treatment profile.
  • Figure 16 is a schematic view of a step and scan motion configuration of the substrate through the hot gas stream to provide the overlapped multiple scans of Figures 14 and 15.
  • Figures 17A through 17C are schematic side views of a substrate holder and substrate.
  • a plot 74 is shown of the rise 78 and fall 80 in temperature as a function of time using a hot gas treatment in accordance with the invention.
  • the plot 74 shows that the hot gas stream is sufficiently high in temperature and power, at least about 5x10 7 Watts/m 2 , to raise the front surface of a silicon wafer substrate to 1300 degrees C in a short time.
  • the time is sufficiently short so that the time to cool the substrate to below the critical temperature of about 800 degrees is substantially shorter than that for a conventional, radiant RTP, thermal processing technique having a maximum temperature rise rate of 300 degrees/sec and cooling rate of 90 de- grees/sec.
  • the fall 80 of plot 74 during cooling to below 800 degrees C is also substantially faster than the cooling rate obtained using a conventional as shown with curve 22 in Figure 6. (Below 800 degrees C further doping or annealing activities tend to cease in silicon.)
  • the hot gas heating time occurs very fast as shown with the curve 78, about 10 5 degrees C/sec, while the cool- ing occurs very fast as shown with curve 80 of plot 74, about 10 5 degrees C/sec.
  • a semiconductor substrate 32 is held upside down by a substrate holder 34 of the vortex type although other holding meth- ods may be used.
  • a suitable atmospheric hot gas stream 14 can be generated by an atmospheric plasma system as shown in figure 2.
  • a hot gas stream is formed by an arc type plasma 38, sometimes referred to as a plasma jet, generated between an anode 40 and cathode 42 powered by a power supply 44.
  • the hot gas stream 14 is directed onto the substrate or wa- fer surface 46.
  • the non-contact vortex type substrate holder 34 which has advantages for this application is shown in Figures 3A and 3B.
  • the holder 34 includes vortex chucks 35 and may be as described in a copending U.S. Patent Application filed on October 12, 2000 and previously identified on the first page of this specification and filed by the same Assignee as of this invention and the same inventors. Alternatively one may include such prior art features as described in the International patent WO 97/45862 , "Non-contact holder for wafer-like articles," inventors Siniaguine and Steinberg, published December 4, 1997.
  • the substrate holder 34 for this application meets a requirement of not rigidly holding the substrate 32 so as to avoid the introduction of stress into the substrate caused by temporary thermal warping due to the high and localized heat input.
  • the holder 34 further should enable a rapid cool-down of the substrate by rapidly removing heat from it and bring the substrate 32 to a fixed and controlled ambient temperature when it is outside the processing region defined by the gas stream 36.
  • FIGs 3A and 3B show six vortex chucks 35 each consisting of an annular channel 35a.
  • a stream of gas such as nitrogen, is injected tangen- tially into the upper section of each annular gas channel 35a of outside diameter D.
  • D may be in the range of 0.5mm to 5mm.
  • the vortex chuck 35 may consist of an open hole rather than an annular ring, with the gas then introduced tangentially at the top of the open hole.
  • the vortex chucks create an outward spiral- ing stream of gas 35c from the diameter D in the gap between the holder, shown for two vortex locations in figure 3.
  • This outward spiraling gas flow generates a low pressure area inside the diameter D at each vortex chuck.
  • the low pressure areas over each vortex chuck create the non-contact holding force for the substrate.
  • the substrate 32 is prevented from sliding away from the holder surface by a set of limiters 35d.
  • the substrate holder is moved through the hot gas treatment area by means of an actuator attached to the holder, not shown.
  • the size of the hot gas stream 36 treatment area is where the stream 36 is incident upon the substrate surface 46.
  • the area A is approximately 2 cm in diameter, normally less than the size of the substrate 32 to be processed (e.g., a 200 mm or 300mm diameter silicon wafer). Consequently, the entire substrate surface 46 is treated by multiple passes of the wafer 32 through the treatment area using a motion configuration that pro- vides for treatment over the full substrate area. Relative motion of the substrate with respect to the treatment area is programmed so that uniform treatment can be obtained. Motion configurations can be by way of step and scan or by way of rotation with translation of wafer 32. The means to obtain uniform thermal processing is shown in Figures 12 to 16.
  • the atmospheric hot gas stream 36 is generated with apparatus 38 within a sealed chamber 48.
  • the atmospheric plasma generating system 38 often referred to as a plasma jet, has previously been described; see US patent 6,040,548, by Siniaguine, entitled "Ap- paratus for generating and deflecting a plasma jet".
  • the apparatus 38 uses a high temperature, arc type plasma generated in an inert gas such as argon between two electrode subassembiies 40, 42 that serve as an anode and cathode for the arc discharge 48.
  • the arc 48 formed by the electrode configuration creates the stream 36 of hot gas to the substrate surface 46.
  • the substrate or wafer 32 to be processed is moved through the treatment area formed by the hot gas stream 36 using a suitable actuator that is not shown.
  • Other suitable ambient gases may be employed inside the sealed chamber 48.
  • a gas injector 50 may be used to inject a gas. Without a flow of gas from the gas injector 50, the hot gas stream 36 is composed primarily of the inert gas from the two electrode assemblies and from the process chamber 48 ambient gas that is entrained into the hot gas stream. For this reason, it is important to have a sealed process chamber to control the process chamber, ambient gas. If air were to be present during a high temperature RTP process oxygen could be diffused into the substrate and cause oxygen to precipitate into crystal defects.
  • a gas containing the doping atoms to be diffused into the substrate may be injected into the hot has stream by the gas injector 50.
  • the hot gas will dissociate the injected material, gas or powder, into its elemental form so that the doping atoms, such as for diffusing boron into silicon, are delivered directly to the substrate surface 46.
  • the temperature of the hot gas stream, at the boundary layer over the substrate, may be controlled by controlling the distance d of the electrode assemblies 40,42 from the substrate 32 as well as the electrical power into the arc type plasma 36.
  • Typical power parameters for driving the arc plasma for RTP applications may be in the ranges of 125 to 250V and 60 to 150Amps and such power is set with the power supply 44.
  • the size of the treatment area generally denoted as A, where the stream 36 is incident upon the substrate surface 46, is approximately 2 cm diameter, normally less than the size of the substrate 32 to be processed (e.g., a 200 mm or 300mm diameter silicon wafer).
  • A may be in the range of 0.5cm to 5cm.
  • A need not be circular but can be elliptically shaped by choice of the plasma generation parameters and gas injected into the hot gas stream, such as by the gas injector 50.
  • the entire substrate surface 46 is treated by multiple passes of the wafer 32 through the treatment area using a motion configuration that provides for such treatment.
  • the relative motion of the substrate with respect to the treatment area is programmed so that uniform treatment can be obtained.
  • Motion configurations can be by way of step and scan or by way of rotation with translation of the substrate 32.
  • the flow of the hot gas stream 36 onto the substrate surface 46 forms a thin hydrodynamic boundary over the surface of the substrate that is approximately 100 microns thick.
  • the gas temperature drops from the temperature in the hot gas stream to the substrate temperature across this boundary layer.
  • the gas temperature on the hot gas stream 36 side of the boundary layer may be in the range of 5,000- 12,000°C with a preferable range being about 9,000 to about 12,000°C.
  • the wafer temperature depends on the process parameters and the velocity of the substrate through the hot gas stream treatment area A, as described below.
  • Heat flux from the hot gas stream through the boundary layer to the substrate surface should be in the range of about 5x10 7 to about 10 9 W/m 2 . It is usually preferable to use an inert gas for the hot gas stream 36 to avoid diffusing unwanted impurities into the substrate 32.
  • a doping gas may be introduced into the hot gas stream to provide doping atoms for diffusion into the substrate.
  • Control of the peak temperature of the substrate 32 reached during exposure of local area A of the substrate to the hot gas treatment area is obtained by control of the substrate velocity through the hot gas treatment area.
  • the heat flux delivered by the hot gas stream 36 is constant.
  • the velocity of the substrate 32 through the gas stream 36 varies the heating time of local area A of the substrate 32.
  • the temperature of the substrate surface increases until that local area exits the treatment area A.
  • Increasing the substrate velocity decreases the exposure time of that local area of the substrate, and consequently, reduces the maximum temperature reached by that area of the sub- strate.
  • Figure 4 illustrates the concept of controlling maximum temperature by the velocity.
  • the programmed motion may used to correct for small systematic variations in the thermal treatment of the substrate such as may occur near the edge of the substrate 32.
  • Control of the peak temperature reached during exposure of a local area of the substrate 32 to the hot gas treatment area A is obtained by motion control.
  • the heat flux delivered by the hot gas stream is constant.
  • Figure 4 illustrates the process of controlling maximum temperature by the velocity of the substrate 32.
  • the hot gas stream treatment area A of the substrate 32 moves over the position on the substrate for which the temperature profile is plotted in Figure 4.
  • the temperature rap- idly rises until that portion of the substrate 32 moves out of the hot gas stream treatment area A.
  • this temperature is 1 ,000°C.
  • a velocity v 2 that is less, the local area on the substrate is exposed to the hot gas stream 36 for a longer period and, therefore, result in a higher peak temperature of 1100 °C for the plot 62.
  • the example shown in Figure 4 is for a silicon wafer.
  • a very rapid cool-down rate is essential to very fast RTP. Rapid cool- down of the substrate surface is obtained by 2 mechanisms.
  • Conductive heat transfer may be by gas conduction or conduction to a solid plate in contact with the wafer. It may be argued that conduction to a solid plate too is gas conduction since heat transfer to the plate is primarily across a very narrow gap by the gas in that gap. Heat from the substrate area exposed to the hot gas treatment area will conduct from the higher temperature substrate surface to the surrounding gas orto a cooled contact plate. For this invention there are advantages to using a non-contact wafer holder so that only the thermal mass of the substrate itself contributes to the heating and cool-down rates.
  • the major heat transfer out of the substrate is from the backside of the substrate to the gas flowing in the gap between the vortex chucks 35 and the substrate 32.
  • the gas transfers heat across the gas gap, typically less than 1mm, to the temperature controlled substrate holder.
  • Conductive heat transfer in the bulk material of the substrate 32 will occur in two directions namely: 1) lateral heat conduction, parallel to the substrate surface 46; and 2) heat transfer through the wafer thickness, perpendicular to the substrate surface 46.
  • Semiconductor substrates are generally very thin (e.g., 0.75 mm for a 200mm standard silicon wafer) compared to the heating area, typi- cally about 20mm in diameter for the atmospheric plasma system of
  • Two heating regimes may be characterized by the dominant cooling mechanism of the surface after immediate exposure to the hot gas stream.
  • W 10 8 W/m 2
  • the heating and cooling characteristics are very different such that we refer to them as different regimes: a high heating power using a high velocity and a low heating power regime using a lower speed.
  • T T(x,y,z) is the temperature of the body
  • p the density
  • c p the heat capacity
  • k the thermal conductivity
  • Q Q(x,y,z) is the net heat input /output.
  • a simple physical model can provide the substrate heating and cooling and the differential equation (1) does not need to be explicitly solved.
  • the time that a given area of the substrate 32 is exposed to the hot gas stream is long compared to the time it takes for the heat to conduct through the substrate from the heated side to the back side.
  • the heating area is much larger than the substrate thickness, as is the case for silicon wafers, thickness of a 200mm wafer ⁇ 0.75mm compared to a heating area ⁇ 20mm in diameter, the heat flow out of the heated area is low compared to the heat input.
  • the heating of the local volume of the substrate can closely approximate the temperature rise of a local area of the substrate.
  • the local substrate volume element ⁇ V undergoing heating is:
  • the total input power H (i.e., Watts) expressed in terms of the heat per unit area W (i.e., Watts/m 2 ) is:
  • the time t, during which the volume element ⁇ V is exposed to the heating flux H is:
  • Temperature rise is related to the total heat input into a volume with density p and heat capacity c p by the well-known equation:
  • Equations (2), (3), (5) and (6) then give the simple expression for calculating the temperature rise:
  • cooling time is relatively long compared to the heating time: yielding a heating rate ⁇ 10 4 °C/sec and a cooling rate ⁇ 1sec.
  • the cooling can then be considered independent of the heating and starting at the time heating from the hot has stream treatment area moves off a given location.
  • the primary cooling mechanism with the non-contact vortex type wafer holder is by forced gas convective heat transfer by the gas flowing from the vortex chucks.
  • the heat removal rate from the backside of the substrate W out can be expressed as:
  • T C00 ⁇ gas, and T wa f e r are the gas temperatures for the cooling gas flowing to the substrate from the substrate holder and the substrate respectively;
  • Ci is the convective gas film coefficient, calculated from the known gas flow and composition conditions.
  • equations (7) and (8) describe the heating and cooling occurring at a given position with motion of a substrate 32 through the hot gas stream 36.
  • the same dependence can be arrived at by applying the proper boundary conditions to the general time dependent heat equation (1 ) as will be evident from the following discussion of the high power heating regime.
  • Figure 6 shows a low heating power regime with curve 20 with the heating and cooling plotted with curve 20 for a silicon wafer with an input power of 10 7 W/m 2 and a velocity of 0.12 m/sec giving a peak temperature z 1 ,100 °C.
  • the hot gas stream starts crossing the first point on the surface 46 of the wafer 32 for which the temperature is plot- ted.
  • the temperature rises at a rate of about ⁇ 10 4 °C/sec until the hot gas stream 36 has moved off of that point; cooling at a rate of seconds then begins.
  • Cooling rate While much faster than Radiant RTP, it is evident that in the low heating power regime that the thermal budget impact is limited by the cooling rate. 2. For high temperatures, such as those approaching the melting point of silicon, the front and back surface temperatures are nearly equal. Hence, the substrate 32 is subject to permanent distortion and associated crystal defects.
  • the stream 36 of hot gas onto the wafer surface 46 sets up a hydrodynamic boundary layer with a temperature dropping from that of the hot gas stream Thot gas (e.g., -10,000 °C) to the substrate temperature T wa fer across the boundary.
  • Thot gas e.g., -10,000 °C
  • C 2 is the convective gas film coefficient calculated from the known gas flow and composition conditions.
  • Figures 7 to 11 are plots that present results from numerical solution, for silicon wafer substrates, to the governing equation (9) subject to the front and back surface boundary conditions, equations (11) and (12). These plots illustrate the non-linear effect that arises when a very high heat gas stream 36 is applied to the wafer 32 and it is moved at a very high speed through the gas stream 36 in comparison to the case where a relatively low power hot gas stream is used.
  • Figure 7 shows how a large temperature differential can be developed through the substrate thickness for the high heating power regime.
  • This figure shows modeling results, plots 66, 68 and 70 for three different heat flux powers to a silicon wafer substrate respectively, 10 7 , 10 8 , and 10 9 W/m 2 .
  • the plots give the temperature profile through the wafer thickness at the time when exposure to the hot gas heating area has just ended.
  • the exposure time of the localized wafer area to the hot gas determined by the velocity of the wafer through the hot gas treatment area, is set to give the same surface temperature of the wafer, 1400°C, close to the melting point of silicon, 1410 °C.
  • a large temperature differential is developed across the wafer.
  • Very high front surface temperatures may be obtained, such as the melting point of silicon, while the bulk of the wafer remains at a low temperature to provide structural rigidity to prevent permanent thermal distortion.
  • the high heating power regime for a large temperature differential through the substrate thickness applies to low and intermediate peak temperatures as well (e.g., ⁇ 900°C).
  • a large temperature differential is set up during the heating time by a sufficiently high velocity (i.e., short exposure time).
  • thermal conductivity for many materials thermal conductivity varies significantly with temperature; for silicon thermal conductivity decreases by a factor of approximately 8 between room temperature and 1400°C).
  • Temperature rise is a direct function of the input heating power. A more rapid temperature rise may be obtained by increasing the heating power. However, in RTP the integrated time spent at a higher temperature uses a significant portion of the allowable thermal budget. As is the case for the low heating power regime, a relatively slow cool-down time will then drive the thermal budget impact. A "spike-like" temperature vs. time thermal profile having both very rapid temperature rise and cool-down rates provides a high thermal processing temperature with a very low impact on the thermal budget.
  • curve 74 shows the front surface temperature rising from the ambient temperature level 76 of 200°C to 1300°C in 6 ms along curve portion 78 when the exposure to the heat flux ends. This illustrates a heating rate of greater than 10 5 o C/sec.
  • curve portion 80 shows a rapidly cooling of the wafer front surface 46, from 1300°C to less than 700°C in the next 6ms, at a cooling rate of about - 10 5 o C/sec.
  • FIG. 9 shows the two cooling mechanisms that are obtained with hot gas RTP in accordance with the invention.
  • This figure shows the front surface and back surface cool-down rates of a silicon wafer substrate 32 immediately after exposure to the hot gas stream for two heating flux powers. At time “0" ms exposure to the hot gas heating area A has just ended.
  • the low heating power regime with the lower heat input flux of 10 7 W/m 2 (upper two plots 82, 84), there is a low temperature differential through the wafer thickness. Consequently, the front surface temperature rapidly comes to the same temperature as the back surface and the cool-down rate is determined by the rate of heat removal by gas conduction from the wafer surfaces, primarily from the back surface.
  • Gas heat conduction from the wafer 32 may be increased above that shown in Figure 9 such as by a lower gas temperature and increased gas flow from the vortex chucks 35.
  • the most rapid cool-down of the front surface is obtained by the mechanism of heat conduction into the silicon en- abled by retaining or establishing a temperature differential through the wafer thickness
  • Figure 10 shows the cool-down rates of the front surface 46 for three input heat flux powers, for curves 90, 92, 94 with the heating exposure time (i.e., velocity) set to give the same peak temperature. At time “0" ms for each of these plots coincides with the peak temperature and occurs when exposure to the hot gas heating area has just ended.
  • rapid cool-down to a temperature below 800°C is needed to allow abrupt doping concentration boundaries and to prevent unwanted diffusion into the silicon.
  • a wafer velocity through the hot gas stream of about - 2 m/sec is needed. Precision control of velocity at 2 m/sec is in the range of standard, commercially available motion control systems.
  • Figure 11 shows a low temperature RTP cooling example with curves 96, for the front surface 46, and 98, for the back wafer surface.
  • a peak temperature of 850°C, from a base temperature of 100°C, is reached in about 6ms after which a rapid cool down of the front surface 46 from ⁇ 850°C to ⁇ 500°C occurs in about 4ms.
  • the peak temperature and the temperature at which the front and back surfaces come to near the same temperature, corresponding to a slower cooling rate, may be adjusted by the input heating power and the substrate velocity.
  • Equations (9), (11) and (12) must be numerically solved to accurately calculate the exposure time of an area of the substrate surface to the hot gas heat flux that will give a large temperature differential through the substrate thickness and consequent high cooling rate. It is instructive, however, to de- velop an approximating physical model that gives the driving variable dependencies and provides an estimate for an exposure time that divides the low and high input heating power regimes.
  • the basis for this approximate physical model is that, to develop a large temperature differential through the wafer thickness, the heat input to the substrate surface must be much greater than the rate of heat transfer through the wafer to the back surface of the wafer.
  • To model this we use the simple, well-known static equations for heat transfer. For temperature rise equation (6) and for heat transfer the equation:
  • Equation (13) then gives:
  • High surface temperature without permanent deformation or crystal defects can be obtained by a hot gas RTP in the high heating power regime in accordance with the invention by establishing a large temperature difference across the wafer thickness, see Figure7.
  • Figure 12 shows at 100 a single pass of the substrate 32 through the hot gas stream treatment area.
  • the substrate 32 moves through the hot gas treatment area A at a velocity V to thermally treat the substrate in a linear path 100 having a characteristic width w.
  • Figure 13 shows plot 104 of a cross-section of the thermal treatment intensity (e.g., depth of diffusion of doping material; temperature) vs. distance for a cross-sectional area that is perpendicular to the scan direction 106 shown in Figure 12.
  • the thermal treatment intensity e.g., depth of diffusion of doping material; temperature
  • Figure 14 shows treatment of the full wafer 32 with multiple scans 104 across the wafer 32 where the step distance si between subsequent scans 104 is relatively large.
  • the treatment intensity cross-section of the wafer 32 for each individual, overlapped scan with separation s-i is shown at 108.
  • the total treatment of the wafer 32 for a cross-sectional area perpendicular to the scan direction is shown at 110. At any point the total treatment resulting from the overlapped scans 104 is the superposition, or summation at that point, of the treatment intensities from each individual scan.
  • Figure 15 shows treatment of the full wafer by multiple scans across the substrate where the step distance s 2 between subsequent scans is small with respect to the width w of the treatment area A.
  • the treatment intensity cross-section of the substrate for each individual, overlapped scan 104 with separation s 2 is shown.
  • the cross-sectional area is perpendicular to the scan direction.
  • the total treatment of the substrate 32 is plotted, for a cross-sectional area perpendicular to the scan direction, with much lower, ripple-like treatment variation as illustrated at 112 for a ratio of w/s 2 of about 3 to 1.
  • the step between scans may be reduced to make the uniformity variation less than any required value.
  • the ratio of w/s 2 can be as shown in Figure 14 equal to 1 , but preferably is in range from about 8 to 1 to about 3 to 1 , with a ratio of about 6 to 1 being acceptable. Increasing the ratio increases the number of scans and may in the aggregate increase the effective impact of the process on the thermal budget to a higher level for the wafer as well increase the scanning time for the entire wafer 32. Too low a ratio w/s 2 results in too high a uniformity variation over the surface of the wafer 32.
  • a method to provide increased cool-down time between overlapped scans is shown at 120 in Figure 16.
  • the time between overlapped scans is increased by scanning with large steps 122 between subsequent scans Y interlaced with small steps s.
  • the hot gas treatment area starts centered at the Start position 124 and scans across the substrate 32 at the programmed velocity that will give the required treatment temperature, see the top solid line 126.1.
  • the edge of the hot gas treatment area A would cross the edge 128 of the substrate 32.
  • the substrate 32 is stepped a distance Y to the second scan position 126.2.
  • the cool-down time be- tween overlapped scans is increased by approximately a factor of four over a straight step and scan pattern.
  • the number of scans per set may be increased or decreased as needed to give full cool-down between overlapped scans.
  • a necessary condition for the large step Y in a scan set is that Y be greater than the characteristic width of the hot gas treatment area w of Figure 13.
  • Figure 16 shows the substrate scans moving over a box area before stepping to the next scan position.
  • the substrate 32 would only need to move fully out of the hot gas treatment area A before stepping to the next scan position.
  • this step and scan concept could also be implemented by having the substrate 32 scan through the hot gas treatment area by moving in an arcuate path instead of the linear paths shown in Figure 16.
  • the arcuate paths for each step would have a constant radius and be offset from each other in the manner as shown for the linear scans.
  • the substrate holder 34 diameter is only slightly larger than the substrate diameter (e.g., -1 mm).
  • the hot gas treatment area A is not sharply defined, but rather, is smoothly spread out by the hydrodynamic gas flow over the wafer surface 46, see Figure 17A. Consequently, as the hot gas treatment area A moves off the substrate 32, in the prior art design there is no processing of the wafer 32 from the outward flow from the hot gas treatment area. Consequently, there is relatively less treatment of the area close to the substrate edge relative to the area close to the substrate center. This effect may be partially compensated for in the programmed, motion of the substrate through the hot gas treatment area by slowing down the motion near the substrate edge.
  • annular substrate holder extension 140 can be added to the perimeter of the substrate holder 34 to effectively extend the plane of the substrate 32 so that the peripheral area of the substrate will be exposed to the same secondary treatment area B as the main treatment area A moves off of the substrate 32.
  • the flow of the process gas as the treatment area moves off the wafer edge will be similar to the flow pattern over the central area of the wafer.
  • a key advantage is that the velocity of the substrate as it moves out of the treatment area can be maintained at a higher relative velocity with uniform treatment.
  • the substrate holder extension 140 should be at least half the width of the main treatment area A and preferably greater than the width of A.
  • a typical dimension for A is 2cm.
  • A may be in the range of 0.5cm to 5cm. and need not be circular.
  • Small systematic effects could arise to introduce small variations in the treatment across the substrate 32. Such variations can arise from a small variation in temperature across the wafer holder resulting in a corresponding small variation in the thermal processing. Such repeatable systematic effects may be measured and subsequently compensated for by programming the position dependent velocity of the substrate 32 through the hot gas stream. For example, a small measured thermal treatment deviation across the substrate ⁇ T(x,y) from the required treatment T 0 can be corrected by a compen- sating velocity map V(x,y) for scanning the substrate through the hot gas stream.
  • This velocity map may be corrected in an iterative procedure by measuring any thermal treatment variation and using this to re-calculate the velocity map.
  • the iterated, compensation velocity map V n+ ⁇ (x,y) is determined from the previous velocity map V n (x,y) for which a treatment variation ⁇ T(x,y) was measured by:
  • V n+ ⁇ (x,y) V n (x,y) / [1 + ⁇ T(x,y) T 0 ]
  • the velocity compensation may be applied from direct feedback from an in-situ, in- process wafer temperature measurement; or, from post-process measurement of the wafer characteristics such as a resistivity mapping of the substrate after RTP for diffusion or anneal.

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Abstract

L'invention se rapporte à une technique de mise en oeuvre très rapide du traitement thermique d'un substrat utilisé pour la fabrication de dispositifs semi-conducteurs. Ledit substrat est exposé à un courant de gaz très chaud tel que celui pouvant être produit par un générateur de plasma de type à arc. Le substrat est ensuite déplacé dans le courant de gaz chaud à une vitesse sélectionnée de manière à chauffer suffisamment la surface du substrat jusqu'à une température élevée à laquelle les processus de dopage et de diffusion peuvent être effectués de manière satisfaisante, tandis qu'un gradient thermique est maintenu sur toute l'épaisseur du substrat. De cette manière, lorsque le substrat se déplace dans le courant de gaz chaud, on parvient à un réchauffement rapide de la surface et à mesure que la partie chauffée se déplace vers l'extérieur du courant gazeux, la majeure partie du substrat peut faciliter le refroidissement de la partie chauffée. Des régions de dopage définies de manière très précise peuvent ainsi être formées dans le substrat. Ce procédé permet d'obtenir des vitesses de réchauffement et de refroidissement de l'ordre de 105°C/s ainsi que des températures de pointe atteignant le point de fusion d'un substrat tel qu'un substrat en silicium sans provoquer de distorsion permanente ni introduire de défauts dans le substrat, et il permet d'effectuer un recuit très rapide à basse température et une activation avec des températures de pointe comprises entre 300 °C et 1000 °C, ce qui assure l'uniformité des processus et le respect des exigences de rendement pour la fabrication de dispositifs en silicium.
EP00992125A 1999-11-01 2000-10-23 Procede pour le traitement thermique rapide de substrats Withdrawn EP1234328A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US16276299P 1999-11-01 1999-11-01
US162762P 1999-11-01
US09/689,307 US6467297B1 (en) 2000-10-12 2000-10-12 Wafer holder for rotating and translating wafers
US689307 2000-10-12
PCT/US2000/041492 WO2001035041A2 (fr) 1999-11-01 2000-10-23 Procede pour le traitement thermique rapide de substrats

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JP3501768B2 (ja) * 2001-04-18 2004-03-02 株式会社ガソニックス 基板熱処理装置およびフラットパネルデバイスの製造方法
JP5105620B2 (ja) * 2008-12-05 2012-12-26 株式会社フィルテック 膜形成方法および膜形成装置
JP5403247B2 (ja) * 2009-09-07 2014-01-29 村田機械株式会社 基板移載装置

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AU4134401A (en) 2001-06-06

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