EP1215719A3 - Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung Download PDF

Info

Publication number
EP1215719A3
EP1215719A3 EP01304902A EP01304902A EP1215719A3 EP 1215719 A3 EP1215719 A3 EP 1215719A3 EP 01304902 A EP01304902 A EP 01304902A EP 01304902 A EP01304902 A EP 01304902A EP 1215719 A3 EP1215719 A3 EP 1215719A3
Authority
EP
European Patent Office
Prior art keywords
electrode pad
substrate
applying
semiconductor device
mounting terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01304902A
Other languages
English (en)
French (fr)
Other versions
EP1215719A2 (de
Inventor
Yoshitaka Aiba
Mitsutaka Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to EP10180097A priority Critical patent/EP2261970A3/de
Publication of EP1215719A2 publication Critical patent/EP1215719A2/de
Publication of EP1215719A3 publication Critical patent/EP1215719A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02319—Manufacturing methods of the redistribution layers by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1067—Oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
EP01304902A 2000-12-12 2001-06-05 Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung Withdrawn EP1215719A3 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10180097A EP2261970A3 (de) 2000-12-12 2001-06-05 Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000377684 2000-12-12
JP2000377684A JP3842548B2 (ja) 2000-12-12 2000-12-12 半導体装置の製造方法及び半導体装置

Publications (2)

Publication Number Publication Date
EP1215719A2 EP1215719A2 (de) 2002-06-19
EP1215719A3 true EP1215719A3 (de) 2004-02-25

Family

ID=18846370

Family Applications (2)

Application Number Title Priority Date Filing Date
EP01304902A Withdrawn EP1215719A3 (de) 2000-12-12 2001-06-05 Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung
EP10180097A Withdrawn EP2261970A3 (de) 2000-12-12 2001-06-05 Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP10180097A Withdrawn EP2261970A3 (de) 2000-12-12 2001-06-05 Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung

Country Status (4)

Country Link
US (2) US6586273B2 (de)
EP (2) EP1215719A3 (de)
JP (1) JP3842548B2 (de)
KR (1) KR100702018B1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020170897A1 (en) * 2001-05-21 2002-11-21 Hall Frank L. Methods for preparing ball grid array substrates via use of a laser
US6784544B1 (en) * 2002-06-25 2004-08-31 Micron Technology, Inc. Semiconductor component having conductors with wire bondable metalization layers
US6845901B2 (en) * 2002-08-22 2005-01-25 Micron Technology, Inc. Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece
US6891248B2 (en) * 2002-08-23 2005-05-10 Micron Technology, Inc. Semiconductor component with on board capacitor
JP2004146526A (ja) * 2002-10-23 2004-05-20 Tomoegawa Paper Co Ltd 電子部材及びその製造方法、並びに半導体装置
JP2004289802A (ja) * 2003-03-06 2004-10-14 Denso Corp ローパスフィルタ及びそれを使用した半導体圧力センサ装置
JP3565835B1 (ja) 2003-04-28 2004-09-15 松下電器産業株式会社 配線基板およびその製造方法ならびに半導体装置およびその製造方法
JP3678239B2 (ja) * 2003-06-30 2005-08-03 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
KR100546346B1 (ko) * 2003-07-23 2006-01-26 삼성전자주식회사 재배선 범프 형성방법 및 이를 이용한 반도체 칩과 실장구조
JP4072141B2 (ja) * 2003-07-31 2008-04-09 沖電気工業株式会社 半導体装置の製造方法
JP4360873B2 (ja) * 2003-09-18 2009-11-11 ミナミ株式会社 ウエハレベルｃｓｐの製造方法
JP4777644B2 (ja) * 2004-12-24 2011-09-21 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
JP2006310530A (ja) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP5165190B2 (ja) * 2005-06-15 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4061506B2 (ja) * 2005-06-21 2008-03-19 セイコーエプソン株式会社 半導体装置の製造方法
KR100699891B1 (ko) * 2006-01-14 2007-03-28 삼성전자주식회사 재배선을 갖는 웨이퍼 레벨 칩 사이즈 패키지 및 그제조방법
US8575018B2 (en) * 2006-02-07 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump structure with multi-layer UBM around bump formation area
US7541251B2 (en) * 2006-02-10 2009-06-02 California Micro Devices Wire bond and redistribution layer process
JP4750586B2 (ja) 2006-02-28 2011-08-17 住友電工デバイス・イノベーション株式会社 半導体装置および電子装置並びにその製造方法
KR100817079B1 (ko) * 2006-12-05 2008-03-26 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그 제조 방법, 및 웨이퍼레벨 칩 스케일 패키지를 포함하는 반도체 칩 모듈
KR101517598B1 (ko) 2008-07-21 2015-05-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP2010010689A (ja) * 2009-06-30 2010-01-14 Sanyo Electric Co Ltd 回路装置およびその製造方法
CN102484101A (zh) 2009-08-13 2012-05-30 SKLink株式会社 电路基板及其制造方法
US8551814B2 (en) * 2010-03-11 2013-10-08 Freescale Semiconductor, Inc. Method of fabricating a semiconductor device that limits damage to elements of the semiconductor device that are exposed during processing
US8952418B2 (en) 2011-03-01 2015-02-10 Micron Technology, Inc. Gated bipolar junction transistors
US9379075B2 (en) * 2014-01-28 2016-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump stop structure
US10074625B2 (en) * 2015-09-20 2018-09-11 Qualcomm Incorporated Wafer level package (WLP) ball support using cavity structure
GB2566029B (en) * 2017-08-30 2022-11-02 Pragmatic Printing Ltd Methods and apparatus for manufacturing a plurality of electronic circuits
US11145612B2 (en) * 2017-12-28 2021-10-12 Texas Instruments Incorporated Methods for bump planarity control

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0734065A2 (de) * 1995-03-24 1996-09-25 Shinko Electric Industries Co. Ltd. Halbleiteranordnung in Chipgrösse
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
US5960308A (en) * 1995-03-24 1999-09-28 Shinko Electric Industries Co. Ltd. Process for making a chip sized semiconductor device
JPH11340369A (ja) * 1998-03-23 1999-12-10 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
EP1030357A1 (de) * 1997-10-30 2000-08-23 Hitachi, Ltd. Halbleiteranordnung und verfahren zur herstellung
JP2001135663A (ja) * 1999-11-04 2001-05-18 Nec Corp 半導体装置及びその製造方法
US6448108B1 (en) * 2000-10-02 2002-09-10 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
GB2385465A (en) * 1999-11-04 2003-08-20 Nec Corp Flip-chip stress aborbing layers and connections

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3316714B2 (ja) * 1994-05-31 2002-08-19 三菱電機株式会社 半導体装置
JP3142723B2 (ja) * 1994-09-21 2001-03-07 シャープ株式会社 半導体装置及びその製造方法
JP3400877B2 (ja) * 1994-12-14 2003-04-28 三菱電機株式会社 半導体装置及びその製造方法
JP3301894B2 (ja) 1995-04-10 2002-07-15 新光電気工業株式会社 半導体装置の製造方法
TW340967B (en) * 1996-02-19 1998-09-21 Toray Industries An adhesive sheet for a semiconductor to connect with a substrate, and adhesive sticking tape for tab, an adhesive sticking tape for wire bonding connection, a substrate for connecting with a semiconductor and a semiconductor device
JP2891665B2 (ja) * 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
WO1998003047A1 (en) * 1996-07-15 1998-01-22 Hitachi Chemical Company, Ltd. Film-like adhesive for connecting circuit and circuit board
JP3305211B2 (ja) * 1996-09-10 2002-07-22 松下電器産業株式会社 半導体装置及びその製造方法
US6130110A (en) * 1996-10-22 2000-10-10 Seiko Epson Corporation Film carrier tape, tape carrier semiconductor device assembly, semiconductor device, and method of making the same, mounted board, and electronic device
US5933752A (en) * 1996-11-28 1999-08-03 Sony Corporation Method and apparatus for forming solder bumps for a semiconductor device
US5969424A (en) * 1997-03-19 1999-10-19 Fujitsu Limited Semiconductor device with pad structure
JP3968788B2 (ja) * 1997-03-21 2007-08-29 セイコーエプソン株式会社 半導体装置及びフィルムキャリアテープの製造方法
JP3796016B2 (ja) * 1997-03-28 2006-07-12 三洋電機株式会社 半導体装置
JPH10294423A (ja) * 1997-04-17 1998-11-04 Nec Corp 半導体装置
US6069406A (en) * 1997-05-20 2000-05-30 Shinko Electric Industries Co., Ltd. Wiring patterned film and production thereof
TW434646B (en) * 1997-11-21 2001-05-16 Rohm Co Ltd Semiconductor device and method for making the same
SG75841A1 (en) * 1998-05-02 2000-10-24 Eriston Invest Pte Ltd Flip chip assembly with via interconnection
JPH11354563A (ja) * 1998-06-11 1999-12-24 Citizen Watch Co Ltd 半導体配線の構造
JP2000022039A (ja) * 1998-07-06 2000-01-21 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP3420703B2 (ja) * 1998-07-16 2003-06-30 株式会社東芝 半導体装置の製造方法
DE19906737A1 (de) * 1999-02-18 2000-09-14 Schott Glas Glaskeramikplatte als Kochfläche mit mindestens einer Kochzone und Verfahren zur Darstellung einer Kochzonenanzeige
JP2001085361A (ja) * 1999-09-10 2001-03-30 Oki Electric Ind Co Ltd 半導体装置およびその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0734065A2 (de) * 1995-03-24 1996-09-25 Shinko Electric Industries Co. Ltd. Halbleiteranordnung in Chipgrösse
US5960308A (en) * 1995-03-24 1999-09-28 Shinko Electric Industries Co. Ltd. Process for making a chip sized semiconductor device
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
EP1030357A1 (de) * 1997-10-30 2000-08-23 Hitachi, Ltd. Halbleiteranordnung und verfahren zur herstellung
JPH11340369A (ja) * 1998-03-23 1999-12-10 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6333565B1 (en) * 1998-03-23 2001-12-25 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP2001135663A (ja) * 1999-11-04 2001-05-18 Nec Corp 半導体装置及びその製造方法
GB2385465A (en) * 1999-11-04 2003-08-20 Nec Corp Flip-chip stress aborbing layers and connections
US6448108B1 (en) * 2000-10-02 2002-09-10 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 03 30 March 2000 (2000-03-30) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 22 9 March 2001 (2001-03-09) *

Also Published As

Publication number Publication date
KR20020046134A (ko) 2002-06-20
US20030207574A1 (en) 2003-11-06
US6967399B2 (en) 2005-11-22
EP2261970A2 (de) 2010-12-15
EP2261970A3 (de) 2012-05-02
EP1215719A2 (de) 2002-06-19
KR100702018B1 (ko) 2007-03-30
JP3842548B2 (ja) 2006-11-08
US20020070440A1 (en) 2002-06-13
JP2002184904A (ja) 2002-06-28
US6586273B2 (en) 2003-07-01

Similar Documents

Publication Publication Date Title
EP1215719A3 (de) Verfahren zur Herstellung einer Halbleitervorrichtung mit einem Schritt zur Anbringung einer Kupferfolie auf einem Substrat, als Teil einer eine Elektrodenfläche mit einem Anschlusselement verbindenden Verdrahtung
WO2003028098A3 (en) Programmable chip-to-substrate interconnect structure and device and method of forming same
EP1335422A3 (de) Halbleitervorrichtung mit Chipabmessungen und Herstellungsverfahren
EP1202348A3 (de) Halbleiteranordnung und Verfahren zu deren Herstellung
WO2005064641A3 (en) Semiconductor device and method of fabricating the same
EP0824301A3 (de) Gedruckte Schaltungsplatte, Chipkarte, und Verfahren zu deren Herstellung
EP1329956A3 (de) Halbleiter-Bauelement und Herstellungsverfahren
EP1418617A3 (de) Halbleiterbauelement und Verfahren zu dessen Herstellung
EP1251558A8 (de) Halbleiteranordnung
WO2005104211A3 (en) Land grid array packaged device and method of forming same
EP1447850A3 (de) Elektronikteil-Gehäusungsstruktur und ihre Herstellungsmethode
EP1343109A3 (de) System zur Versorgung einer niedrigen, mit offener Höhlung versehenen Halbleiterpackung
EP1111676A3 (de) Unterteil-Verbindungssubstrat für Elektronikteil
JP2004179232A5 (de)
EP1174921A3 (de) Halbleiterbauelement
WO2000004584A3 (de) Halbleiterbauelement im chip-format und verfahren zu seiner herstellung
EP1076360A3 (de) Halbleitermontagemethode und Montageapparat
EP1187523A3 (de) Hochfrequenzbaugruppe und zugehöriges Herstellungsverfahren
EP0917191A3 (de) Elektronische Bauelementeinheit, elektronischer Zusammenbau welcher diese Einheit anwendet, und Herstellungsverfahren für diese elektronische Bauelementeinheit
EP0814510A3 (de) Filmträger und in einer Halbleiteranordnung verwendete Filmträger
US20010040239A1 (en) Chip-type semiconductor light-emitting device
EP1143515A3 (de) Verdrahtungssubstrat, seine Herstellung und Halbleiterbauteil
EP1193750A3 (de) Microlötverfahren und -vorrichtung
EP1028388A3 (de) Identifizierungselement und Verfahren zur Herstellung eines Identifizierungselements
EP1030444A3 (de) Akustische Oberflächenwellenanordnung und Verfahren zur Herstellung derselben

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17P Request for examination filed

Effective date: 20040823

AKX Designation fees paid

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 20070502

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: FUJITSU MICROELECTRONICS LIMITED

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: FUJITSU SEMICONDUCTOR LIMITED

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SOCIONEXT INC.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20170103