EP1190448A1 - Boitier de microcircuit a comblement moule - Google Patents

Boitier de microcircuit a comblement moule

Info

Publication number
EP1190448A1
EP1190448A1 EP99923109A EP99923109A EP1190448A1 EP 1190448 A1 EP1190448 A1 EP 1190448A1 EP 99923109 A EP99923109 A EP 99923109A EP 99923109 A EP99923109 A EP 99923109A EP 1190448 A1 EP1190448 A1 EP 1190448A1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
substrate
circuit chip
underfilling
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99923109A
Other languages
German (de)
English (en)
Other versions
EP1190448A4 (fr
Inventor
Patrick O. Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hestia Technologies Inc
Original Assignee
Hestia Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hestia Technologies Inc filed Critical Hestia Technologies Inc
Priority claimed from PCT/US1999/010771 external-priority patent/WO2000070678A1/fr
Publication of EP1190448A1 publication Critical patent/EP1190448A1/fr
Publication of EP1190448A4 publication Critical patent/EP1190448A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • FIG. 3 is a side view of an integrated circuit chip mounted on a substrate and underfilled according to a prior art method
  • FIG. 5 is a cross-sectional side view of an alternative embodiment of an integrated circuit chip package according to the present invention
  • FIG. 6 is a cross-sectional side view of an integrated circuit chip and substrate placed within a mold cavity according to the present invention
  • the integrated circuit chip package 10 is illustrated by way of example in FIG. 4 and includes an integrated circuit chip 12, a substrate 14, and a mold compound 16 encapsulating the chip and underfilling between the chip and the substrate.
  • the integrated circuit chip package 10 is formed by transfer molding the package in a mold tool by a process which is described below with reference to FIGS. 6 - 8.
  • the integrated circuit chip 12 has an active upper surface 18 having metal circuits thereon.
  • a plurality of solder bumps 20 are formed on the active surface 18 of the integrated circuit chip 12 for electrical interconnection of the chip to the substrate 14.
  • the patterns of the solder bumps 20 on the integrated circuit chip 12 will vary widely between chips and may have spaces between the solder bumps which are as small as approximately 0.002 inches (0.051 mm).
  • the solder bumps 20 themselves have a height which is approximately 0.005 inches (0.127 mm).
  • the solder bumps 20 are melted by a reflow furnace to connect the integrated circuit chip to the substrate.
  • the reflowed chip and substrate are separated by a distance D which is 0.002 inches (0.051 mm) to 0.006 inches (0.152 mm), preferably approximately 0.003 inches (0.076 mm) to 0.005 inches (0.127 mm).
  • the method of underfilling according to the present invention employs a mold 30 having a top half 32 and bottom half 34.
  • the bottom half 34 of the mold is provided with cavities 36 for receiving the substrate solder bumps 24 on the lower side of the substrate.
  • the mold cavities 36 may be eliminated and the substrate solder bumps 24 or pins may be attached after underfilling.
  • the bottom half 34 of the mold also includes a mold material overflow channel 38 which is positioned to receive mold material which passes through the central vent hole 26 in the substrate. Mold material which collects in the overflow channel 38 forms an overflow bead 48 of mold material on an underside of the substrate 14 as shown in FIGS. 4, 7, and 8.
  • the mold compound fills the mold cavity surrounding the integrated circuit chip 12 and the sides of the substrate 14.
  • the mold compound is also forced between the chip 12 and the substrate 14 into the air gaps which are present between the solder joints formed by the solder bumps 20.
  • a pressure within the mold cavity 40 must be carefully controlled while the underfilling process is performed to prevent the pressure within the mold cavity from exceeding a predetermined pressure threshold and pressing the chip 12 down onto the substrate with a force causing crushing of the solder bumps 20 before the underfilling process is complete.
  • the mold cavity pressure is controlled by the mold vent 46 which allows some of the mold compound to escape from the mold cavity 40 into the overflow cavity 42.
  • the volume of mold compound which can be held in both the vent hole 26 and the overflow channel 38 are designed to allow mold material to continue to pass into the vent hole of the substrate 14 until all the air spaces between the integrated circuit chip 12 and substrate have been completely filled.
  • the total transfer time for the mold cavity 40 to be filled and for underfilling to be completed is preferably between approximately 15 and 20 seconds.
  • the cure time for the thermoset mold material to cure is then between about 60 and 200 seconds. After this cure time, the mold is opened and the integrated circuit chip package 10 is removed from the mold.
  • the total cycle time for underfilling and encapsulation of the integrated circuit chip 12 in the present invention is significantly better than the time for underfilling alone with the known underfilling methods employing capillary action.
  • the integrated chip package 50 is formed in a mold cavity having an upper mold half which engages a surface 58 of the integrated circuit chip 52.
  • the mold compound 56 surrounds the edges of the integrated circuit chip 52 and the edge of the substrate 54, but does not enclose the chip within the mold compound 56.
  • the transfer molding process according to the present invention may be used for a wide variety of integrated circuit chip shapes, sizes, and types.
  • the transfer molding composition may be modified as known to those in the art to achieve different transfer times, cure times, flow characteristics, and post cure properties.
  • the mold compound 16 for use in the present invention includes a combination of one or more adhesive and one or more filler material.
  • the filler material is between about 70 and 90 percent of the mold compound, preferably between 75 and 85 percent.
  • the filler material may be silica, quartz, or any other known filler material having particle diameters which are preferably 0.35 - 2 mils (0.01 - 0.05 mm).
  • the filler material particles may be formed in different shapes such as spherical, elongated, or irregularly shaped to achieve different flow characteristics.
  • the adhesive material may be any known adhesive material, such as a novolac epoxy.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Le boîtier de microcircuit (10) pour circuit intégré de la présente invention comporte un microcircuit de circuit intégré (12) monté sur un substrat (14) via une pluralité de bossages de soudure (20). On utilise un mélange de moulage (16) pour combler les vides entre le microcircuit (12) et le substrat (14). Pour réaliser le boîtier de microcircuit (10) pour circuit intégré, on prend le microcircuit (12) et le substrat (14), on les place à l'intérieur d'une cavité de moulage (36), et on y comprime un mélange de moulage par transfert (16). Les vides de matière entre le microcircuit de circuit intégré (12) et le substrat (14) se comblent de mélange de moulage dès qu'on l'injecte sous pression entre le microcircuit de circuit intégré (12) et le substrat (14). Un évent (26) traversant le substrat (14) permet à l'air retenu entre le microcircuit (12) et le substrat (14) de s'échapper pendant le comblement. La matière de comblement (16) convient également à l'encapsulation du microcircuit (12) pendant l'opération de comblement.
EP99923109A 1999-05-14 1999-05-14 Boitier de microcircuit a comblement moule Withdrawn EP1190448A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1999/010771 WO2000070678A1 (fr) 1997-10-29 1999-05-14 Boitier de microcircuit a comblement moule

Publications (2)

Publication Number Publication Date
EP1190448A1 true EP1190448A1 (fr) 2002-03-27
EP1190448A4 EP1190448A4 (fr) 2004-11-24

Family

ID=22272770

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99923109A Withdrawn EP1190448A4 (fr) 1999-05-14 1999-05-14 Boitier de microcircuit a comblement moule

Country Status (3)

Country Link
EP (1) EP1190448A4 (fr)
JP (1) JP2003500833A (fr)
KR (1) KR20020035477A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7029342B2 (ja) * 2018-04-16 2022-03-03 アピックヤマダ株式会社 モールド金型、樹脂モールド装置及び樹脂モールド方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557150A (en) * 1992-02-07 1996-09-17 Lsi Logic Corporation Overmolded semiconductor package
US5578261A (en) * 1993-05-17 1996-11-26 Lucent Technologies Inc. Method of encapsulating large substrate devices using reservoir cavities for balanced mold filling
WO1999000834A2 (fr) * 1997-06-27 1999-01-07 International Business Machines Corporation Procede et appareil d'encapsulation d'une puce a protuberances moulee par injection

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226414A (ja) * 1994-02-10 1995-08-22 Toshiba Corp 半導体素子の樹脂封止方法および樹脂封止型半導体装置
JP3683996B2 (ja) * 1996-07-30 2005-08-17 株式会社東芝 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557150A (en) * 1992-02-07 1996-09-17 Lsi Logic Corporation Overmolded semiconductor package
US5578261A (en) * 1993-05-17 1996-11-26 Lucent Technologies Inc. Method of encapsulating large substrate devices using reservoir cavities for balanced mold filling
WO1999000834A2 (fr) * 1997-06-27 1999-01-07 International Business Machines Corporation Procede et appareil d'encapsulation d'une puce a protuberances moulee par injection

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
HAN AND K K WANG S: "Study on the pressurized underfill encapsulation of flip chips" IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY. PART B: ADVANCED PACKAGING, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 4, no. 20, 1 November 1997 (1997-11-01), pages 434-442, XP002075500 ISSN: 1070-9894 *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 11, 26 December 1995 (1995-12-26) -& JP 07 226414 A (TOSHIBA CORP), 22 August 1995 (1995-08-22) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 06, 30 April 1998 (1998-04-30) -& JP 10 050878 A (TOSHIBA CORP), 20 February 1998 (1998-02-20) -& US 6 107 689 A (KOZONO HIROYUKI) 22 August 2000 (2000-08-22) *
See also references of WO0070678A1 *

Also Published As

Publication number Publication date
JP2003500833A (ja) 2003-01-07
KR20020035477A (ko) 2002-05-11
EP1190448A4 (fr) 2004-11-24

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