Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

• the invention relates to a semiconductor device with a semiconductor body which is provided at a surface with a programmable and electrically erasable non-volatile memory comprising a matrix of memory cells which each comprise a field effect transistor with floating gate.
• a major embodiment of such a device is a CMOS circuit manufactured in a standard CMOS process and provided with an embedded memory.
• Such semiconductor devices are generally known.
• Flash memories in which the cells are arranged in a NOR architecture and in which writing and erasing take place by means of CHEI (channel hot electron injection) and FN tunneling (Fowler-Nordheim tunneling mechanism) often suffer from the problem of overerasure.
• CHEI channel hot electron injection
• FN tunneling Fluler-Nordheim tunneling mechanism
• writing programming in general requires much current.
• Memories with a N AND architecture, in which both writing and erasing take place by means of Fowler-Nordheim tunneling require high voltages for erasing and writing, which in its turn may have important consequences for the technology.
• each memory cell also comprises a select transistor which is connected in series with the floating-gate transistor, in that the memory cells form a matrix of the NOR type, and in that the select transistor is connected to the source of the floating-gate transistor, while both writing and erasing of the memory cells can be carried out on the basis of the Fowler-Nordheim tunneling mechanism.
• the problem of overerasure can be solved by the select transistor.
• the FN tunneling mechanism as a result has a high efficiency, so that lower voltages can suffice.
• a preferred embodiment is characterized in that the transistors of each cell are of the n-channel type, while the semiconductor body comprises a p-type surface region adjoining the surface, and the transistors are provided in a p-type well which adjoins the surface and which is insulated from the p-type surface region by an interposed n-type well.
• Fig. 1 is an equivalent circuit diagram of a non-volatile memory according to the invention.
• Fig. 2 is a cross-sectional view of a memory cell of the device of Fig. 1.
• Fig. 1 represents a diagram of a non- volatile, programmable, electrically erasable memory according to the invention.
• the device comprises a matrix of memory cells, arranged in m rows and n columns.
• the cells in a row are identified with Mil, Mi2, ..., Min, i being the number of the row.
• the cells in a column j are identified with Mlj, M2j, ..., Mnj.
• Each memory cell comprises a floating gate transistor Tl in which data can be stored on a floating gate, as is generally known.
• Each memory cell further comprises a second transistor T2 which is connected in series with Tl and which forms a select transistor connected to the source of the floating gate transistor Tl .
• the sources of the select transistors T2 are connected to a common junction point 1.
• the drains of the transistors Tl in one column are connected to a bit line BLi, i being the number of the column.
• the bit lines BL are connected to means 2 for applying the desired voltages to the selected bit lines.
• Each floating gate transistor Tl is provided with a control gate which is connected to word line Cgi, i being the number of the row.
• the gate- of the select transistors ⁇ -! are connected to a word line Sgi.
• the lines Sg and Cg are connected to means 3 by which the suitable voltage can be applied to the selected lines.
• the arrangement of the memory cells described here is referred to in the literature as the NOR architecture. Since the read current between the bit line BL and the junction point 1 runs through the selected cell only, comparatively low voltages on the word lines can suffice, in contrast to circuits of, for example, the NAND type, in which the cells of a column are connected in series.
• Fig. 2 shows a cross-section of a single memory cell.
• the device comprises peripheral electronics, which are not shown, apart from the memory cell shown here.
• the device may also comprise a logic portion manufactured in a standard CMOS process, also not shown, in embedded applications.
• the silicon semiconductor body comprises a surface region 5 of the p-type which adjoins the surface 4. The surface region may cover the entire semiconductor body, but this is not necessarily the case.
• a deep n-type well 6 is provided in the surface region 5 and is provided with a less deep p-type well in which the n- channel transistors Tl and T2 are provided.
• the n-well 6 insulates the p-type well 7 from the p-type substrate 5, so that different voltages, for example positive voltages, can be applied to the p-type well 7 compared with the voltages applied to the substrate 5, and/or negative voltages may be applied to the bit line.
• the transistor T2 comprises an n-type source 8, an n- type drain 9, and a gate 10 which is separated from the channel between the source and the drain by gate oxide.
• the source is connected to the junction point 1 , as is indicated diagrammatically, and the gate to a word line Sg.
• the transistor Tl comprises a source formed by the zone 9 and an n-type drain 11 connected to a bit line BL.
• the floating gate 12 is provided above the channel, electrically insulated from the latter.
• the control gate 13 is provided above the floating gate, electrically insulated therefrom, and is connected to a select line Cg. In the embodiment of Fig. 2, the control gate 13 is provided so as to overlap the floating gate 12, whereby a large capacitive coupling between the gates is obtained.
• the gates may alternatively be arranged as a stack, so that the capacitance between the gates is somewhat smaller, but the cell can also be made smaller then. Reference is made to Table 1 below for the operation of the memory.
• a low (negative) voltage Vnn (for example -5 V) is applied to all word lines Sg, so that the select transistors are not conducting.
• the low voltage Vnn is also applied to the selected bit line, so that the relevant drain can temporarily act as a source.
• a positive voltage Vpp (for example 5 V) is applied to the selected word line Cg, so that an inversion channel is formed in the transistor Tl. Since the select transistor is not conducting, no current flows through the cell, so that no or substantially no power is dissipated.
• the maximum voltage is present between the channel and the control gate, which voltage is chosen (depending on, for example, oxide thicknesses and other process parameters) such that electrons are stored on the floating owing to Fowler-Nordheim tunneling.
• the charge transport takes place over the entire channel, a high efficiency is obtained, so that the voltages used may be comparatively low.
• the field strength across the tunnel oxide is also comparatively small, so that damage to the oxide can remain limited, which is important inter alia for the number of write/erase cycles which can be carried out.
• 0 V is applied to the non-selected bit lines, so that the voltage across the oxide becomes so small that no Fowler-Nordheim tunneling occurs in the non-selected cells.
• the low voltage Vnn is applied to the p-type well 7 during programming so as to prevent the pn junctions belonging to the selected bit line from becoming forward biased.
• the positive voltage Vpp is applied to the p-type well 7 and also to the n-type well 6 so as to prevent the pn junction between the n-type well and the p-type well from becoming forward biased.
• the low voltage Vnn is applied to the selected word line Cg, and 0 V to the other word lines.
• the voltage across the gate oxide of the selected cell is sufficiently high again now for Fowler-Nordheim tunneling, so that electrons will tunnel from the floating gate to the substrate 5.
• the potential of the floating gate rises and the threshold voltage of the transistor becomes low. As during writing, tunneling takes place during erasing over the entire channel surface, so that comparatively low voltages can be used also during erasing.
• each cell comprises a select transistor, moreover, there are absolutely no objections against erasing to the point where the threshold voltage becomes very low, even lower than 0 V, which has important advantages inter alia for reading. Reading
• a voltage is applied to the selected word line Cg which lies between the threshold voltage of a programmed cell (high threshold voltage) and the threshold voltage of a non-programmed cell (low threshold voltage of an erased cell), and it is ascertained whether the floating gate transistor is or is not conducting.
• the highest available voltage Vdd is applied to the word line Sg of the cell, so that the select transistor is conducting.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Non-Volatile Memory (AREA)
• Semiconductor Memories (AREA)

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• 2000
  • 2000-05-24 KR KR1020017001409A patent/KR20010072189A/ko not_active Application Discontinuation
  • 2000-05-24 EP EP00940280A patent/EP1119875A1/de not_active Withdrawn
  • 2000-05-24 JP JP2001502170A patent/JP2003501838A/ja not_active Withdrawn
  • 2000-05-24 WO PCT/EP2000/004891 patent/WO2000075994A1/en not_active Application Discontinuation

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