EP1116256A1 - Dispositif a effet de champ a vide et procede de fabrication - Google Patents

Dispositif a effet de champ a vide et procede de fabrication

Info

Publication number
EP1116256A1
EP1116256A1 EP00948950A EP00948950A EP1116256A1 EP 1116256 A1 EP1116256 A1 EP 1116256A1 EP 00948950 A EP00948950 A EP 00948950A EP 00948950 A EP00948950 A EP 00948950A EP 1116256 A1 EP1116256 A1 EP 1116256A1
Authority
EP
European Patent Office
Prior art keywords
vacuum
source
oxide
insulating
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00948950A
Other languages
German (de)
English (en)
Inventor
Michael D. Potter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Vision Technologies Inc
Original Assignee
Advanced Vision Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Vision Technologies Inc filed Critical Advanced Vision Technologies Inc
Publication of EP1116256A1 publication Critical patent/EP1116256A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/05—Preparation or purification of carbon not covered by groups C01B32/15, C01B32/20, C01B32/25, C01B32/30
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J21/00—Vacuum tubes
    • H01J21/02—Tubes with a single discharge path
    • H01J21/06—Tubes with a single discharge path having electrostatic control means only
    • H01J21/10—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode
    • H01J21/105—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode with microengineered cathode and control electrodes, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

Definitions

  • This invention relates to microelectronic devices and more particularly to a vacuum-channel field-effect microelectronic device having a lateral field-emission source and preferably having insulated gate(s).
  • lateral emitter or “lateral field-emission source” are used interchangeably to refer to a field- emission source disposed parallel to a substrate.
  • horizontal and vertical are used herein to mean parallel and perpendicular to a substrate respectively, without implying any preferred orientation in space or any preferred orientation with respect to the earth's surface or with respect to the direction of a gravitational force.
  • insulating as in “insulating substrate” or “insulating layer,” is used in its common meaning and particularly for substances characterized by a resistivity greater than 10 s ⁇ - cm.
  • conductive refers to substances characterized by a resistivity less than or equal to 10 8 ⁇ - cm., i.e., including the resistivity range of both conductive and semiconductive substances.
  • An ultra-high-frequency vacuum-channel field-effect microelectronic device has a lateral field-emission source, a drain, and one or more insulated gates.
  • the insulated gate(s) is preferably disposed to extend in overlapping alignment with the emitting edge of the lateral field-emission source and with a portion of the vacuum channel region. If the gate(s) is omitted, the device performs as an ultra-high-speed diode.
  • a preferred fabrication process for the device uses a sacrificial material temporarily deposited in a trench for the vacuum channel region, which is covered with an insulating layer cover. An access hole in the cover allows removal of the sacrificial material.
  • the drain preferably acts also as a sealing plug, plugging the access hole and sealing the vacuum-channel region after the vacuum-channel region is evacuated.
  • FIG. 1 is a partially cut-away perspective view of an insulated-gate vacuum field-effect device made in accordance with the invention.
  • FIGS. 2a - 2 j are side-elevation cross-sectional views of the device in various stages of a preferred fabrication process.
  • FIG. 3 is a flowchart illustrating the steps of a preferred fabrication process performed in accordance with the invention.
  • VFED ultra-high-switching-speed vacuum field-effect device
  • the charge carrier source for the VFED is an electron emitter source operable via Fowler-Nordheim emission.
  • the channel region is a vacuum. Since there is no material in the channel region to scatter the electrons and the channel length is short, the electron transit time is very short. There is no vacuum path between the source and gate or between the drain and gate. Therefore, a relatively high drain potential can be maintained without causing electron emission from the gate.
  • the high drain potential together with the short vacuum channel leads to an electron transit time on the order of sub-picoseconds.
  • the electric permittivity preferably has a value greater than two.
  • the gain parameter, ( ⁇ I SVd/dVg
  • @ Id constant), can be large due to the strong influence of the gate on the channel current with a vacuum channel length in the range of about equal to or greater than 0.5 micrometer.
  • FIG. 1 (not to scale) is a partially cut-away perspective view of an insulated- gate vacuum-channel field-effect device 10 made in accordance with the invention.
  • Device 10 is made on an insulating substrate 20.
  • Source layer 60 (a lateral field- emission cold cathode with emitting tip 85) is parallel to substrate 20.
  • FIG. 1 and the cross-section drawings 2f — 2 j show emitting tip 85 schematically as having a rectangular shape, the actual shape of the emitting tip 85 can be a very sharp edge , i.e., an extremely small radius, as is known in the art of field-emission cathodes.
  • a drain 150 collects electrons emitted from emitting tip 85 of source 60 when a suitable bias voltage is applied to source 60 and drain 150.
  • Drain 150 is spaced apart laterally from emitting tip 85 of the source 60 by a spacing preferably between about one nanometer and about one millimeter.
  • Gates preferably bottom gate 40 and top gate 160, are disposed in at least partial alignment with emitting edge 85 of source 60 and extend to overlap a portion of a vacuum-channel region 120.
  • a conductive bottom- gate contact 155 extends down and makes ohmic electrical contact with bottom gate 40.
  • Contact 155 is also connected to top gate 160 in the embodiment shown in FIG. 1.
  • the use of a recess in substrate 20 for bottom gate 40 allows for planarization of gate 40 and therefore provides for precise control and uniformity of the thickness of insulating layer 50 deposited over gate 40 in a preferred fabrication process, described in detail below.
  • gate 40 may be disposed on the top surface of substrate 20, without a recess.
  • each gate and the vacuum channel region prevents any electrons emitted by the source from reaching either gate, each gate being completely separated from the vacuum channel region by its respective insulating layer (50 or combination of 70 with 100).
  • Each of these insulating layers also prevents any vacuum path between its corresponding gate and the drain 150, so there is no possibility of electron current flowing through the vacuum between either gate and the drain (for example, secondary electron current). It will be understood that this is also true for an IGVFED having only one gate instead of the two-gate preferred embodiment described and illustrated herein.
  • the conductive contact 155 that interconnects them is also fully insulated from vacuum-channel region 120 by the insulators 50, 70, and 100.
  • the dimensions of vacuum-channel region 120 are designed to prevent vacuum- channel region 120 from extending back to the region of conductive contact 155.
  • a conventional passivation layer (not shown) may be deposited over device 10 to protect the device and to prevent surface leakage currents.
  • Conventional via- openings may be formed and conventional terminal metallurgy (not shown) may be deposited to contact the conductive elements shown in FIG. 1.
  • one aspect of the invention is a vacuum field-effect device 10 having a source 60 comprising a lateral field-emitter with an emitting tip 85 for emitting electrons, having a conductive drain 150 spaced apart laterally from the emitting tip, having a vacuum channel region 120 extending at least between the emitting tip 85 of the source and the drain 150, having at least one gate 40 or 160, completely separated from the vacuum channel region by an insulating layer 50, 70, or 100 disposed between the gate and the vacuum channel region 120 to prevent any electrons emitted by the source from reaching the gate, and having terminals (e.g., 140) for applying a bias voltage between the drain and source and for applying a control signal to the gate.
  • terminals e.g. 140
  • the terminals may be integral with their respective electrodes, such as 150 and 160 in FIG. 1.
  • the device preferably has two electrically common gates 40 and 160, which may be connected by an integrated conductive gate contact 155.
  • the device is constructed on an insulating substrate 20, which may consist of an insulating film on a conductive or semiconductive substrate.
  • the new terahertz vacuum field-effect device is much simpler to fabricate than compound semiconductor or heteroj unction semiconductor devices. No semiconductor materials are used in the preferred embodiment.
  • the structure fabrication is, however, compatible with standard IC metallization, passivation, and interconnecting processing. Furthermore, the new device can be integrated with either variations of the preferred embodiment fabrication process or with other integrated- circuit fabrication processes.
  • An overall process for fabricating the vacuum field-effect device includes the steps of providing a suitably flat insulating substrate, forming a source by disposing a lateral field emitter parallel to the substrate, forming an emitting tip on the lateral field emitter of the source, providing a conductive drain spaced apart laterally from the emitting tip for receiving electrons, forming a first opening for a vacuum channel region at least between the emitting tip and the drain, disposing at least one gate in at least partial alignment with respect to the emitting tip and in at least partially overlapping alignment with the first opening, substantially covering the first opening to form a closed vacuum channel chamber, removing any gases from the first opening to provide a vacuum, and sealing the vacuum channel chamber.
  • the overall process may also include the step of disposing an insulating layer between the gate and the vacuum channel region to prevent any of the electrons emitted by the source from reaching the gate, the gate being completely separated from the vacuum channel region by the insulating layer. Terminals are added for applying a bias voltage between the source and drain and for applying a control signal to the gate.
  • the step of providing an insulating substrate may be accomplished by first providing a base substrate, where the base substrate may have any degree of conductivity or semiconductivity, and then depositing an insulating surface layer on the base substrate.
  • the base substrate may be a conductor, a semiconductor, or any substance characterized by a resistivity of less than about 10 8 ⁇ -cm., or an insulator differing in composition from the insulating layer deposited on it.
  • the base substrate may be a metal, silicon, germanium, III-V compounds (GaAs, AlGaAs, InP, GaN, etc.), conducting oxides (e.g., indium tin oxide, indium oxide, tin oxide, copper oxide, or zinc oxide), transition metal nitrides, or transition metal carbides.
  • FIGS. 2a - 2 j and 3 gives details of a particularly preferred fabrication process.
  • FIGS. 2a - 2 j are not drawn to scale. This description includes steps for providing two gates, but it will be recognized that a VFED device may be made with one or more gates and that the gates may be omitted to make a high-speed diode.
  • FIGS. 2a - 2j show a series of side-elevation cross-sectional views showing the results of specific steps of the preferred process.
  • FIG. 3 shows a flow chart representing the preferred fabrication process, in which steps are designated by reference numerals SI, ..., S21. For each of these steps, the act performed is listed in Table I (following page). 51 Provide substrate
  • a suitably flat insulating substrate 20 is provided.
  • Insulating substrate 20 may comprise any suitable insulating material such as glass, ceramic, glass ceramic, diamond, quartz, aluminum oxide, sapphire, silicon oxide, silicon nitride, aluminum nitride, nickel oxide, plastic, polymer, polyimide, parylene, polyethylene terephthalate, and mixtures and combinations thereof.
  • the flat insulating substrate 20 provided in step SI may be made by first providing a conductive base substrate, such as a silicon semiconductor wafer, and depositing a surface layer of a suitable insulating material on the conductive base substrate to form an insulating surface.
  • the insulating layer may be any of the insulating materials listed above, for example.
  • step S2 a trench 30 is formed in the surface of the insulating substrate (FIG. 2a).
  • step S3 trench 30 is filled with a conducting layer 40 and planarized (FIG. 2b) to form a first gate.
  • the planarization may be done by chemical-mechanical polishing (CMP).
  • conducting layer 40 Some suitable materials for conducting layer 40 are aluminum, copper, silver, gold, platinum, palladium, bismuth, conducting oxides, conducting nitrides, the refractory transition metals (titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, and tungsten), the refractory transition metal carbides, the refractory transition metal nitrides, boron carbide, doped boron nitride, transition metal suicides, carbon in any of its conductive forms (e.g., doped diamond, graphite, amorphous carbon, fullerenes, nanotubes, or nanocoralline), silicon (N - type or P - type, polycrystalline, amorphous, or single-crystal), germanium, and mixtures, alloys, and combinations thereof.
  • the refractory transition metals titanium, vanadium, chromium, zirconium, niobi
  • Step S4 consists of depositing a first insulating layer 50 over the planarized surface (FIG. 2c).
  • First insulating layer 50 may comprise any suitable insulator, such as glass, glass ceramic, quartz, aluminum oxide, sapphire, silicon oxide, silicon nitride, barium strontium titanate, titanium oxide, samarium oxide, yttrium oxide, tantalum oxide, barium titanium oxide, barium tantalum oxide, lead titanium oxide, strontium titanium oxide, strontium (zirconium, titanium) oxide, aluminum nitride, polyimide, parylene, or mixtures and combinations thereof.
  • the electric permittivity ⁇ of first insulating layer 50 preferably has a value greater than two.
  • Second insulating layer 70 may comprise any suitable insulator, such as any of the materials used for first insulating layer 50 (glass, glass ceramic, quartz, aluminum oxide, sapphire, silicon oxide, silicon nitride, barium strontium titanate, titanium oxide, samarium oxide, yttrium oxide, tantalum oxide, barium titanium oxide, barium tantalum oxide, lead titanium oxide, strontium titanium oxide, strontium (zirconium, titanium) oxide, aluminum nitride, polyimide, parylene, or mixtures and combinations thereof).
  • insulating layers 50 and 70 consist of the same insulating material.
  • the electric permittivity ⁇ of second insulating layer 70 preferably has a value greater than two.
  • a second trench 80 for a vacuum channel region is formed (step S7, FIG. 2f) by etching at least through second insulating layer 70 and source layer 60, but not down as far as first gate layer 40.
  • Trench 80 may be formed by directional reactive ion etching. Forming this trench also etches source layer 60 to form emitting tip 85. If necessary, further etching, such as an isotropic wet etch or plasma etch may be used to further etch emitting tip 85. As is known in the art of field-emission cathodes, it is desirable to form emitting edge 85 with an extremely small radius, to have a very sharp knife-edge shape.
  • Suitable conductive materials for source layer 60 are aluminum, copper, silver, gold, platinum, palladium, bismuth, conducting oxides, conducting nitrides, the refractory transition metals (titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, and tungsten), the refractory transition metal carbides, the refractory transition metal nitrides, boron carbide, doped boron nitride, transition metal suicides, carbon in any of its conductive forms (e.g., doped diamond, graphite, amorphous carbon, fullerenes, nanotubes, or nanocoralline), silicon (N - type or P - type, polycrystalhne, amorphous, or single-crystal), germanium, and mixtures, alloys
  • second trench 80 is filled with a sacrificial material 90 and planarized (FIG. 2g).
  • Sacrificial material 90 may be an inorganic material or an organic material such as parylene.
  • a third insulating layer 100 is deposited (step S9, FIG. 2h).
  • Third insulating layer 100 may comprise any suitable insulator, such as any of the materials used for first insulating layer 50 and second insulating layer 70.
  • Insulating layer 100 preferably consists of the same insulating material as insulating layers 50 and 70 and preferably has an electric permittivity ⁇ of greater than two.
  • an access hole 110 is opened through third insulating layer 100 down at least into sacrificial material 90 (FIG. 2i).
  • Access hole 110 is preferably made at or near the edge of trench 80 that is spaced farthest from emitting tip 85.
  • step Sll source via-opening 130 and a via-opening (not shown) for bottom gate 40 are formed.
  • the bottom gate contact 155 (shown in FIG. 1) uses this bottom gate via- opening, which is out of the plane of the cross-sections of FIGS. 2a - 2j.
  • steps S10 and Sll may be combined and performed simultaneously, as indicated in FIG. 3 by a bracket joining these two steps.
  • sacrificial material 90 is removed through access hole 110, e.g., by dissolving sacrificial material 90 with a suitable solvent and removing the solution through access hole 110.
  • the solvent may be acetone.
  • the sacrificial material 90 is silicon dioxide, it may be removed by wet chemical etching, e.g., with HF. For many sacrificial materials, the removal process may be done by oxygen plasma etching. Removing the sacrificial material leaves an empty vacuum channel region 120. The next few steps may be performed in a vacuum environment, with a vacuum pressure preferably less than or equal to about one torr, provided in step S13.
  • step S14 a conductive source contact 140 is deposited and patterned.
  • step S15 a conductive top gate 160 is deposited and patterned.
  • step S16 a conductive bottom gate contact 155 (shown in FIG. 1) is deposited and patterned.
  • step SI 7 a conductive drain 150 is deposited and patterned.
  • Suitable conductive materials for conductive top gate 160, conductive bottom gate contact 155, and conductive drain 150 are aluminum, copper, silver, gold, platinum, palladium, bismuth, conducting oxides, conducting nitrides, the refractory transition metals (titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, and tungsten), the refractory transition metal carbides, the refractory transition metal nitrides, boron carbide, doped boron nitride, transition metal suicides, carbon in any of its conductive forms (e.g., doped diamond, graphite, amorphous carbon, fullerenes, nanotubes, or nanocoralline), silicon (N - type or P - type, polycrystalhne, amorphous, or single-crystal), germanium, and mixtures, alloys, and combinations thereof.
  • the refractory transition metals titanium,
  • step S18 access hole 110 is filled to seal the vacuum channel region 120.
  • This step SI 8 is preferably performed at a vacuum pressure of less than or equal to about one torr. When the vacuum channel region 120 is sealed, the channel region will be at vacuum.
  • Steps S14 - S18 are preferably all performed together simultaneously as a step SI 9, as indicated in Fig. 3 by a bracket.
  • access hole 110 also defines the pattern for the lower part of drain 150 (inside vacuum chamber channel region 120). The resultant device after performing steps S14 - S18 or the combined step S19 is shown in the cross-sectional view of FIG. 2j and in the partially cut-away perspective view of FIG. 1.
  • forming conductive drain 150 and sealing vacuum channel region 120 may be accomplished by the methods of U.S. Pat. No. 5,700,176 to Potter, the entire disclosure of which is incorporated herein by reference.
  • a passivation layer may be deposited (step S20) and via-openings formed and terminal metallurgy deposited (step S21).
  • the vacuum field-effect device of this invention may be made with very wide ranges of dimensions and of material characteristics such as electric permittivity of insulators.
  • the vacuum channel length may be made between about one nanometer and about one millimeter.
  • electric permittivities ⁇ , drain voltage values, tradeoffs with coupling capacitance, and enhancement vs. retardation mode of operation are wide ranges of electric permittivities ⁇ , drain voltage values, tradeoffs with coupling capacitance, and enhancement vs. retardation mode of operation.
  • the thicknesses of the insulating layers 50 and combination of 70 and 100 is preferably chosen to be between about one nanometer and about 1000 nanometers when the electric permittivity of the insulating layer is less than or equal to 20, and the spacing is preferably chosen to be between about 10 nanometers and about 5000 nanometers when the electric permittivity of the insulating layer is greater than 20.
  • the device disclosed herein is particularly useful for high bandwidth communication requirements. Such uses of the device include transmitting and receiving data at the chip level, and thus, the device is suitable for short-range intra- LAN communication, wired or wireless.
  • the device also inherently has high thermal tolerance and radiation resistance. It is therefore desirable for applications in harsh environments. These applications include sensor applications for fission or fusion reactors, borehole sensors, accelerator sensors and instrumentation, applications in satellites, deep space and extrate ⁇ estrial exploration vehicles, and many other similar applications.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Composite Materials (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)

Abstract

La présente invention concerne un dispositif micro-électronique à effet de champ à canal de vide à fréquence ultra-haute (VFED ou IGVFED) comportant une source d'émission de champ latéral (60), un collecteur (150) et au moins une grille isolée (40, 160). Ces grilles isolées sont disposées de préférence de façon à se déployer en alignement de chevauchement avec le bord émetteur (85) de la source d'émission de champ latérale et avec une partie de la région du canal à vide (120). Si les grilles n'existent pas, le dispositif fonctionne comme une diode à très grande vitesse. Pour l'un des procédés de fabrication préférés du dispositif, on utilise un matériau sacrificiel déposé temporairement dans une tranchée pour la région du canal à vide qui est couverte d'une couverture isolante. Un trou d'accès dans la couverture permet l'élimination du matériau sacrificiel. Un aspect d'un procédé de fabrication préféré est de voir le drain agir de préférence également comme obturateur étanche, fermant le trou d'accès et obstruant de façon étanche la région du canal à vide une fois que la région du canal à vide a été évacuée.
EP00948950A 1999-07-26 2000-07-25 Dispositif a effet de champ a vide et procede de fabrication Withdrawn EP1116256A1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US477788 1990-02-09
US14557099P 1999-07-26 1999-07-26
US145570P 1999-07-26
US47778899A 1999-12-31 1999-12-31
US47698499A 1999-12-31 1999-12-31
US476984 1999-12-31
PCT/US2000/020230 WO2001008193A1 (fr) 1999-07-26 2000-07-25 Dispositif a effet de champ a vide et procede de fabrication

Publications (1)

Publication Number Publication Date
EP1116256A1 true EP1116256A1 (fr) 2001-07-18

Family

ID=27386281

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00948950A Withdrawn EP1116256A1 (fr) 1999-07-26 2000-07-25 Dispositif a effet de champ a vide et procede de fabrication

Country Status (6)

Country Link
EP (1) EP1116256A1 (fr)
JP (1) JP2003505844A (fr)
KR (1) KR20010075312A (fr)
CN (1) CN1327610A (fr)
CA (1) CA2345629A1 (fr)
WO (1) WO2001008193A1 (fr)

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Publication number Priority date Publication date Assignee Title
US9136794B2 (en) 2011-06-22 2015-09-15 Research Triangle Institute, International Bipolar microelectronic device

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JP2003308798A (ja) 2002-04-17 2003-10-31 Toshiba Corp 画像表示装置および画像表示装置の製造方法
CN101086940B (zh) * 2006-06-09 2011-06-22 清华大学 场发射阴极装置的制造方法
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WO2016182080A1 (fr) * 2015-05-14 2016-11-17 国立大学法人山口大学 Transistor à canal à vide et procédé de fabrication correspondant
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WO2017190511A1 (fr) * 2016-05-04 2017-11-09 中国科学院苏州纳米技术与纳米仿生研究所 Dispositif à émission de champ et son procédé de fabrication
CN108242466B (zh) * 2016-12-26 2020-09-01 中国科学院苏州纳米技术与纳米仿生研究所 场发射器件及其制作方法
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CN111613662B (zh) * 2020-05-27 2021-06-11 东北大学 偏压诱导共线反铁磁材料产生自旋极化电流的调控方法
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KR20010075312A (ko) 2001-08-09

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