EP1070340A1 - Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby - Google Patents
Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated therebyInfo
- Publication number
- EP1070340A1 EP1070340A1 EP99908553A EP99908553A EP1070340A1 EP 1070340 A1 EP1070340 A1 EP 1070340A1 EP 99908553 A EP99908553 A EP 99908553A EP 99908553 A EP99908553 A EP 99908553A EP 1070340 A1 EP1070340 A1 EP 1070340A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- gallium nitride
- nitride layer
- layer
- underlying
- growing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 402
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 401
- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims description 41
- 208000012868 Overgrowth Diseases 0.000 title description 12
- 238000004377 microelectronic Methods 0.000 claims abstract description 30
- 230000000873 masking effect Effects 0.000 claims abstract description 11
- 230000007547 defect Effects 0.000 claims description 70
- 239000000758 substrate Substances 0.000 claims description 39
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 claims description 19
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 17
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 229910021529 ammonia Inorganic materials 0.000 claims description 7
- 238000003491 array Methods 0.000 claims description 3
- 230000001902 propagating effect Effects 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000003085 diluting agent Substances 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 125000002524 organometallic group Chemical group 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000004581 coalescence Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000000877 morphologic effect Effects 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910000807 Ga alloy Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
Definitions
- This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
- gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
- a major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable. It is also known to fabricate gallium nitride structures through openings in a mask.
- a gallium nitride semiconductor layer by laterally growing an underlying gallium nitride layer to thereby form a laterally grown gallium nitride semiconductor layer, and forming microelectronic devices in the laterally grown gallium nitride semiconductor layer.
- a gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the overgrown gallium nitride semiconductor layer.
- the overgrown gallium nitride layer is relatively defect-free. Accordingly, high performance microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.
- the overgrown gallium nitride semiconductor layer is overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer.
- the overgrown layer can thus have overgrown regions of relatively low defect in the area of coalescence and regions of relatively high defects over the mask openings.
- a gallium nitride semiconductor layer is fabricated by laterally growing an underlying gallium nitride layer to thereby form a first laterally grown gallium nitride semiconductor layer, and laterally growing the first laterally grown gallium nitride layer to thereby form a second laterally grown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second laterally grown gallium nitride semiconductor layer.
- a gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a first mask that includes a first array of openings therein and growing the underlying gallium nitride layer through the first array of openings and onto the first mask, to thereby form a first overgrown gallium nitride semiconductor layer.
- the first overgrown layer is then masked with the second mask that includes a second array of openings therein.
- the second array of openings is laterally offset from the first array of openings.
- the first overgrown gallium nitride layer is then grown through the second array of openings and onto the second mask, to thereby form a second overgrown gallium nitride semiconductor layer.
- Microelectronic devices may then be formed in the second overgrown gallium nitride semiconductor layer.
- the first overgrown gallium nitride layer is relatively defect-free.
- the second array of mask openings is laterally offset from the first array of mask openings, the relatively defect-free overgrown first gallium nitride layer propagates through the second array of openings and onto the second mask. Accordingly, high performance microelectronic devices may be formed in the second overgrown gallium nitride semiconductor layer.
- the second overgrown gallium nitride semiconductor layer is overgrown until the second overgrown gallium nitride layer coalesces on the second mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer.
- the entire continuous overgrown layer can thus be relatively defect-free compared to the underlying gallium nitride layer.
- the first and second gallium nitride semiconductor layers may be grown using metalorganic vapor phase epitaxy (MONPE).
- the openings in the masks are stripes that are oriented along the ⁇ 1 1 00 > direction ofthe underlying gallium nitride layer.
- the overgrown gallium nitride layers may be grown using triethylgallium (TEG) and ammonia ( ⁇ H 3 ) precursors at 1000- 1100°C and 45 Torr.
- TEG triethylgallium
- ⁇ H 3 ammonia
- TEG at 13-39 ⁇ mol/min and NH 3 at 1500 seem are used in combination with 3000 seem H 2 diluent.
- TEG at 26 ⁇ mol/min, NH 3 at 1500 seem and H 2 at 3000 seem at a temperature of 1100°C and 45 Torr are used.
- the underlying gallium nitride layer preferably is formed on a substrate, which itself includes a buffer layer such as aluminum nitride, on a substrate such as 6H- SiC(0001).
- Gallium nitride semiconductor structures according to the present invention include an underlying gallium nitride layer, a lateral gallium nitride layer that extends from the underlying gallium nitride layer, and a plurality of microelectronic devices in the lateral gallium nitride layer.
- gallium nitride semiconductor structures according to the present invention include an underlying gallium nitride layer and a patterned layer (such as a mask) that includes an array of openings therein, on the underlying gallium nitride layer.
- a vertical gallium nitride layer extends from the underlying gallium nitride layer through the array of openings.
- a lateral gallium nitride layer extends from the vertical gallium nitride layer onto the patterned layer, opposite the underlying gallium nitride layer.
- a plurality of microelectronic devices including but not limited to optoelectronic devices and field emitters, are formed in the lateral gallium nitride layer.
- the lateral gallium nitride layer is a continuous monocrystalline gallium nitride semiconductor layer.
- the underlying gallium nitride layer and the vertical gallium nitride layer both include a predetermined defect density, and the lateral gallium nitride semiconductor layer is of lower defect density than the predetermined defect density. Accordingly, low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high- performance microelectronic devices.
- gallium nitride semiconductor structures include an underlying gallium nitride layer, a first lateral gallium nitride layer that extends from the underlying gallium nitride layer and a second lateral gallium nitride layer that extends from the first lateral gallium nitride layer.
- a plurality of microelectronic devices are provided in the second lateral gallium nitride layer.
- gallium nitride semiconductor structures include an underlying gallium nitride layer and a first mask that includes a first array of openings therein, on the underlying gallium nitride layer.
- a first vertical gallium nitride layer extends from the underlying gallium nitride layer through the first array of openings.
- a first lateral gallium nitride layer extends from the vertical gallium nitride layer onto the mask, opposite the underlying gallium nitride layer.
- a second mask on the first lateral gallium nitride layer includes a second array of openings therein that are laterally offset from the first array of openings.
- a second vertical gallium nitride layer extends from the first lateral gallium nitride layer and through the second array of openings.
- a second lateral gallium nitride layer extends from the second vertical gallium nitride layer onto the second mask, opposite the first lateral gallium nitride layer.
- a plurality of microelectronic devices including but not limited to optoelectronic devices and field emitters, are formed in the second vertical gallium nitride layer and in the second lateral gallium nitride layer.
- the second lateral gallium nitride layer is a continuous monocrystalline gallium nitride semiconductor layer.
- the underlying gallium nitride layer includes a predetermined defect density, and the second vertical and lateral gallium nitride semiconductor layers are of lower defect density than the predetermined defect density. Accordingly, continuous low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high-performance microelectronic devices, using laterally offset masks.
- Figure 1 is a cross-sectional view of first embodiments of gallium nitride semiconductor structures according to the present invention.
- Figures 2-5 are cross-sectional views of structures of Figure 1 during intermediate fabrication steps, according to the present invention.
- Figure 6 is a cross-sectional view of second embodiments of gallium nitride semiconductor structures according to the present invention.
- Figure 7-14 are cross-sectional views of structures of Figure 6 during intermediate fabrication steps, according to the present invention.
- the gallium nitride structures 100 include a substrate 102.
- the substrate may be sapphire or gallium nitride.
- the substrate includes a 6H-SiC(0001) substrate 102a and an aluminum nitride buffer layer 102b on the silicon carbide substrate 102 a
- the aluminum nitride buffer layer 102b may 0.01 ⁇ m thick.
- the fabrication of substrate 102 is well known to those having skill in the art and need not be described further. Fabrication of silicon carbide substrates are described, for example, in U.S.
- An underlying gallium nitride layer 104 is also included on buffer layer 102b opposite substrate 102a.
- the underlying gallium nitride layer 104 may be between O 99/44224 .
- the underlying gallium nitride layer generally has an undesired relatively high defect density, for example dislocation densities of between about 10 and 10 10 cm "2 . These high defect densities may result from mismatches in lattice parameters between the buffer layer 102b and the underlying gallium nitride layer 104. These high defect densities may impact performance of microelectronic devices formed in the underlying gallium nitride layer 104.
- a mask such as a silicon dioxide mask 106 is included on the underlying gallium nitride layer 104.
- the mask 106 includes an array of openings therein. Preferably, the openings are stripes that extend along the ⁇ 1 1 00 > direction ofthe underlying gallium nitride layer 104.
- the mask 106 may have a thickness of about 1000 A and may be formed on the underlying gallium nitride layer 104 using low pressure chemical vapor deposition (CVD) at 410°C.
- the mask 106 may be patterned using standard photolithography techniques and etched in a buffered hydrofluoric acid (HF) solution.
- HF buffered hydrofluoric acid
- a vertical gallium nitride layer 108a extends from the underlying gallium nitride layer 104 and through the array of openings in the mask 106.
- the term "vertical" means a direction that is orthogonal to the faces ofthe substrate 102.
- the vertical gallium nitride layer 108a may be formed using metalorganic vapor phase epitaxy at about 1000-1100°C and 45 Torr. Precursors of triethygallium (TEG) at 13-39 ⁇ mol/min and ammonia ( ⁇ H 3 ) at 1500 seem may be used in combination with a 3000 seem H 2 diluent, to form the vertical gallium nitride layer 108a.
- TAG triethygallium
- ⁇ H 3 ammonia
- the gallium nitride semiconductor structure 100 also includes a lateral gallium nitride layer 108b that extends laterally from the vertical gallium nitride layer 108a onto the mask 106 opposite the underlying gallium nitride layer 104.
- the lateral gallium nitride layer 108b may be formed using metalorganic vapor phase epitaxy as described above.
- the term "lateral" denotes a direction parallel to the faces of substrate 102.
- lateral gallium nitride layer 108b coalesces at interfaces 108c to form a continuous monocrystalline gallium nitride semiconductor layer 108. It has been found that the dislocation densities in the underlying gallium nitride layer 104 generally do not propagate laterally with the same intensity as vertically. Thus, lateral gallium nitride layer 108b can have a relatively low defect density, for example less that 10 4 cm "2 . Accordingly, lateral gallium nitride layer 108b may form device quality gallium nitride semiconductor material. Thus, as shown in Figure 1 , microelectronic devices 110 may be formed in the lateral gallium nitride layer 108b.
- an underlying gallium nitride layer 104 is grown on a substrate 102.
- the substrate 102 may include a 6H-SiC(0001) substrate 102a and an aluminum nitride buffer layer 102b.
- the gallium nitride layer 104 may be between 1.0 and
- the underlying gallium nitride layer 104 is masked with a mask 106 that includes an array of openings 107 therein.
- the mask may comprise silicon dioxide at thickness of lOOOA and may be deposited using low pressure chemical vapor deposition at 410°C. Other masking materials may be used.
- the mask may be patterned using standard photolithography techniques and etching in a buffered HF solution.
- the openings 107 are 3 ⁇ m-wide openings that extend in parallel at distances of between 3 and 40 ⁇ m and that are oriented along the ⁇ 1 1 00 > direction on the underlying gallium nitride layer 104.
- the structure Prior to further processing, the structure may be dipped in a 50% buffered hydrochloric acid (HC1) solution to remove surface oxides from the underlying gallium nitride layer 104.
- HC1 50% buffered hydrochloric acid
- the underlying gallium nitride layer 104 is grown through the array of openings 107 to form vertical gallium nitride layer 108a in the openings.
- Growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr.
- the precursors TEG at 13-39 ⁇ mol/min and NH 3 at 1500 seem may be used in combination with a 3000 seem H diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used.
- the gallium nitride layer 108a grows vertically to the top ofthe mask 106.
- underlying gallium nitride layer 104 may also be grown laterally without using a mask 106, by appropriately controlling growth parameters and/or by appropriately patterning the underlying gallium nitride layer 104.
- a patterned layer may be formed on the underlying gallium nitride layer after vertical growth or lateral growth, and need not function as a mask.
- lateral growth in two dimensions may be used to form an overgrown gallium nitride semiconductor layer.
- mask 106 may be patterned to include an array of openings 107 that extend along two orthogonal directions such as ⁇ 1100 > and ⁇ 1120 > .
- the openings can form a rectangle of orthogonal striped patterns.
- the ratio ofthe edges ofthe rectangle is preferably proportional to the ratio ofthe growth rates ofthe ⁇ 1120 ⁇ and ⁇ 1101 ⁇ facets, for example, in a ratio of 1.4: 1.
- lateral overgrowth is allowed to continue until the lateral growth fronts coalesce at interfaces 108c, to form a continuous gallium nitride layer 108.
- the total growth time may be approximately 60 minutes.
- microelectronic devices may then be formed in regions 108b. Devices may also be formed in regions 108a if desired.
- gallium nitride semiconductor structures according to second embodiments ofthe present invention are illustrated.
- the gallium nitride structures 200 include a substrate 102 as described above.
- An underlying gallium nitride layer 104 is also included on buffer layer 102b opposite substrate 102a as described above.
- a first mask such as a first silicon dioxide mask 106 is included on O 99/44224 _ J Q - PCT/US99/04346
- the first mask 106 includes a first array of openings therein.
- the first openings are first stripes that extend along the ⁇ 1 1 00 > direction ofthe underlying gallium nitride layer 104 as described above.
- a first vertical gallium nitride layer 108a extends from the underlying gallium nitride layer 104 and through the first array of openings in the first mask 106 as described above.
- the gallium nitride semiconductor structure 200 also includes a first lateral gallium nitride layer 108b that extends laterally from the first vertical gallium nitride layer 108a onto the first mask 106 opposite the underlying gallium nitride layer 104 as described above.
- a second mask such as a second silicon dioxide mask 206 is included on the first vertical gallium nitride layer 108a. As shown, second mask 206 is laterally offset from first mask 106. It will also be understood that second mask 206 may also extend onto first vertical gallium nitride layer 108b. Preferably, second mask 206 covers all of first vertical gallium nitride layer 108b such that defects in this layer do not propagate further. It will also be understood that the second mask 206 need not be symmetrically offset with respect to first mask 106.
- the second mask 206 includes a second array of openings therein. The second openings are preferably oriented as described in connection with the first mask 106.
- the second mask 206 also may be fabricated similar to first mask 106. Still continuing with the description of Figure 6, a second vertical gallium nitride layer 208a extends from the first lateral gallium nitride layer 108a and through the second array of openings in the second mask 206. The second vertical gallium nitride layer 208a may be formed similar to first vertical gallium nitride layer 108a.
- the gallium nitride semiconductor structure 200 also includes a second lateral gallium nitride layer 208b that extends laterally from the second vertical gallium nitride layer 208a onto the second mask 206 opposite the first gallium nitride layer 108.
- the second lateral gallium nitride layer 208b may be formed using metalorganic vapor phase epitaxy as was described above.
- the second lateral gallium nitride layer 208b coalesces at second interfaces 208c, to form a second continuous monocrystalline gallium nitride semiconductor layer 208. It has been found that since the first lateral gallium nitride layer 108b is used to grow second gallium nitride layer 208, the second gallium nitride layer 208 including second vertical gallium nitride layer 208a and O 99/44224 _ j j _ PCT/US99/04346
- second lateral gallium nitride layer 208b can have a relatively low defect density, for example less than 10 4 cm "2 . Accordingly, the entire gallium nitride layer 208 can form device quality gallium nitride semiconductor material.
- microelectronic devices 210 may be formed in both the second vertical gallium nitride layer 208a and the second lateral gallium nitride layer 208b, and may bridge these layers as well. By offsetting masks 106 and 206, a continuous device quality gallium nitride layer may be obtained.
- an underlying gallium nitride layer 104 is grown on a substrate 102 as was described in detail in connection with Figure 2. Still referring to Figure 7, the underlying gallium nitride layer 104 is masked with a first mask 106 that includes a first array of openings 107 therein as was described in connection with Figure 2. Referring to Figure 8, the underlying gallium nitride layer 104 is grown through the first array of openings 107 to form first vertical gallium nitride layer 108a in the first openings as was described in connection with Figure 3.
- first gallium nitride layer 108a causes lateral overgrowth onto the first mask 106, to form first lateral gallium nitride layer 108b, as was described in connection with Figure 4.
- lateral overgrowth is optionally allowed to continue until the lateral growth fronts coalesce at first interfaces 108c, to form a first continuous gallium nitride layer 108, as was described in connection with Figure 5.
- the first vertical gallium nitride layer 108a is masked with a second mask 206 that includes a second array of openings 207 therein.
- the second mask may be fabricated as was described in connection with the first mask.
- the second mask may also be eliminated, as was described in connection with the first mask of Figure 3.
- the second mask may also be eliminated, as was described in connection with Figure 3.
- the second mask 206 preferably covers the entire first vertical gallium nitride layer 108a, so as to prevent defects therein from propagating vertically or laterally. In order to provide defect-free propagation, mask 206 may extend onto first lateral gallium nitride layer 108b as well.
- the first lateral gallium nitride layer 108c is grown vertically through the second array of openings 207, to form second vertical gallium nitride layer 208a in the second openings. Growth may be obtained as was described in connection with Figure 3.
- continued growth ofthe second gallium nitride layer 208a causes lateral overgrowth onto the second mask 206, to form second lateral gallium nitride layer 208b. Lateral growth may be obtained as was described in connection with Figure 3.
- lateral overgrowth preferably continues until the lateral growth fronts coalesce at second interfaces 208c to form a second continuous gallium nitride layer 208.
- Total growth time may be approximately 60 minutes.
- Microelectronic devices may then be formed in regions 208a and in regions 208b as shown in Figure 6, because both of these regions are of relatively low defect density. Devices may bridge these regions as well, as shown. Accordingly, a continuous device quality gallium nitride layer 208 may be formed.
- the openings 107 and 207 in the masks are preferably rectangular stripes that preferably extend along the ⁇ 1120 > and/or ⁇ 1 1 00 > directions relative to the underlying gallium nitride layer 104.
- Truncated triangular stripes having (1 1 01) slant facets and a narrow (0001) top facet may be obtained for mask openings 107 and 207 along the ⁇ 1120 > direction.
- Rectangular stripes having a (0001) top facet, (1120) vertical side faces and (1 1 01) slant facets may be grown along the ⁇ 1 1 00 > direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop into different shapes if the growth is continued.
- the amount of lateral growth generally exhibits a strong dependence on stripe orientation.
- the lateral growth rate ofthe ⁇ 1 1 00 > oriented stripes is generally much faster than those along ⁇ 1120 > . Accordingly, it is most preferred to orient the openings 107 and 207 so that they extend along the ⁇ 1 1 00 > direction ofthe underlying gallium nitride layer 104.
- Stripes oriented along ⁇ 1120 > may have wide (1 1 00) slant facets and either a very narrow or no (0001) top facet depending on the growth conditions. This may be because (1 1 01) is the most stable plane in the gallium nitride wurtzite crystal structure, and the growth rate of this plane is lower than that of others.
- the ⁇ 1 1 01 ⁇ planes ofthe ⁇ 1 1 00 > oriented stripes may be wavy, which implies the existence of more than one Miller index.
- the morphologies ofthe gallium nitride layers selectively grown on openings oriented along ⁇ 1 1 00 > are also generally a strong function ofthe growth temperatures. Layers grown at 1000°C may possess a truncated triangular shape. This morphology may gradually change to a rectangular cross-section as the growth temperature is increased. This shape change may occur as a result ofthe increase in the diffusion coefficient and therefore the flux ofthe gallium species along the (0001) top plane onto the ⁇ 1 1 01 ⁇ planes with an increase in growth temperature.
- the morphological development ofthe gallium nitride regions also appears to depend on the flow rate ofthe TEG.
- An increase in the supply of TEG generally increases the growth rate ofthe stripes in both the lateral and the vertical directions.
- the lateral/vertical growth rate ratio decrease from 1.7 at the TEG flow rate of 13 ⁇ mol/min to 0.86 at 39 ⁇ mol.min.
- This increased influence on growth rate along ⁇ 0001> relative to that of ⁇ 1120 > with TEG flow rate may be related to the type of reactor employed, wherein the reactant gases flow vertically and perpendicular to the substrate.
- the considerable increase in the concentration ofthe gallium species on the surface may sufficiently impede their diffusion to the ⁇ 1 1 01 ⁇ planes such that chemiso ⁇ tion and gallium nitride growth occur more readily on the (0001) plane.
- Continuous 2 ⁇ m thick gallium nitride layers 108 and 208 may be obtained using 3 ⁇ m wide stripe openings 107 and 207 spaced 7 ⁇ m apart and oriented along ⁇ 1 1 00 > , at 1100°C and a TEG flow rate of 26 ⁇ mol/min.
- the overgrown gallium nitride layers 108b and 208b may include subsurface voids that form when two growth fronts coalesce.
- the coalesced gallium nitride layers 108 and 208 may have a microscopically flat and pit-free surface.
- the surfaces ofthe laterally grown gallium nitride layers may include a terrace structure having an average step height of 0.32nm. This terrace structure may be related to the laterally grown gallium nitride, because it is generally not included in much larger area films grown only on aluminum nitride buffer layers.
- the average RMS roughness values may be similar to the values obtained for the underlying gallium nitride layers 104.
- Threading dislocations originating from the interface between the gallium nitride underlayer 104 and the buffer layer 102b, appear to propagate to the top surface ofthe first vertical gallium nitride layer 108a within the first openings 107 of the first mask 106.
- the dislocation density within these regions is approximately 10 9 cm "2 .
- threading dislocations do not appear to readily propagate into the first overgrown regions 108b. Rather, the first overgrown gallium nitride regions 108b contain only a few dislocations. These few dislocations may be formed parallel to the (0001) plane via the extension ofthe vertical threading dislocations after a 90° bend in the regrown region.
- both the second vertical gallium nitride layer 208a and the second lateral gallium nitride layer 208b propagate from the low defect first overgrown gallium nitride layer 108b, the entire layer 208 can have low defect density.
- the formation mechanism ofthe selectively grown gallium nitride layer is lateral epitaxy.
- the two main stages of this mechanism are vertical growth and lateral growth.
- Ga or N atoms should not readily bond to the mask surface in numbers and for a time sufficient to cause gallium nitride nuclei to form. They would either evaporate or diffuse along the mask surface to the openings 107 or 207 in the masks or to the vertical gallium nitride surfaces 108a or 208a which have emerged. During lateral growth, the gallium nitride grows simultaneously both vertically and laterally over the mask from the material which emerges over the openings.
- lateral cracking within the SiO may take place due to thermal stresses generated on cooling.
- the viscosity (p) ofthe SiO 2 at 1050°C is about 10 15 ' 5 poise which is one order of magnitude greater than the strain point (about 10 145 poise) where stress relief in a bulk amorphous material occurs within approximately six hours.
- the SiO 2 mask may provide limited compliance on cooling.
- chemical bonding may occur only when appropriate pairs of atoms are in close proximity. Extremely small relaxations ofthe silicon and oxygen and gallium and nitrogen atoms on the respective surfaces and/or within the bulk ofthe SiO may accommodate the gallium nitride and cause it to bond to the oxide.
- regions of lateral epitaxial overgrowth through mask openings from an underlying gallium nitride layer may be achieved via MOVPE.
- the growth may depend strongly on the opening orientation, growth temperature and TEG flow rate.
- Coalescence of overgrown gallium nitride regions to form regions with both extremely low densities of dislocations and smooth and pit-free surfaces may be achieved through 3 ⁇ m wide mask openings spaced 7 ⁇ m apart and extending along the ⁇ 1 TOO > direction, at 1100°C and a TEG flow rate of 26 ⁇ mol/min.
- the lateral overgrowth of gallium nitride via MOVPE may be used to obtain low defect density continuous gallium nitride layers for microelectronic devices.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US32190 | 1979-04-23 | ||
US09/032,190 US6051849A (en) | 1998-02-27 | 1998-02-27 | Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer |
US09/031,843 US6608327B1 (en) | 1998-02-27 | 1998-02-27 | Gallium nitride semiconductor structure including laterally offset patterned layers |
US31843 | 1998-02-27 | ||
PCT/US1999/004346 WO1999044224A1 (en) | 1998-02-27 | 1999-02-26 | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1070340A1 true EP1070340A1 (en) | 2001-01-24 |
Family
ID=26707683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99908553A Ceased EP1070340A1 (en) | 1998-02-27 | 1999-02-26 | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1070340A1 (ja) |
JP (1) | JP2002505519A (ja) |
KR (1) | KR100610396B1 (ja) |
CN (1) | CN1143363C (ja) |
AU (1) | AU2795699A (ja) |
CA (1) | CA2321118C (ja) |
WO (1) | WO1999044224A1 (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998047170A1 (en) | 1997-04-11 | 1998-10-22 | Nichia Chemical Industries, Ltd. | Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device |
US6265289B1 (en) | 1998-06-10 | 2001-07-24 | North Carolina State University | Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby |
JP4529215B2 (ja) * | 1999-10-29 | 2010-08-25 | 日亜化学工業株式会社 | 窒化物半導体の成長方法 |
US6380108B1 (en) | 1999-12-21 | 2002-04-30 | North Carolina State University | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby |
US6403451B1 (en) * | 2000-02-09 | 2002-06-11 | Noerh Carolina State University | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts |
WO2001059819A1 (en) * | 2000-02-09 | 2001-08-16 | North Carolina State University | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby |
US6261929B1 (en) | 2000-02-24 | 2001-07-17 | North Carolina State University | Methods of forming a plurality of semiconductor layers using spaced trench arrays |
TW518767B (en) * | 2000-03-31 | 2003-01-21 | Toyoda Gosei Kk | Production method of III nitride compound semiconductor and III nitride compound semiconductor element |
JP4291527B2 (ja) | 2000-10-13 | 2009-07-08 | 日本碍子株式会社 | Iii族窒化物エピタキシャル基板の使用方法 |
JP4920152B2 (ja) * | 2001-10-12 | 2012-04-18 | 住友電気工業株式会社 | 構造基板の製造方法および半導体素子の製造方法 |
KR101167590B1 (ko) * | 2002-04-15 | 2012-07-27 | 더 리전츠 오브 더 유니버시티 오브 캘리포니아 | 유기금속 화학기상 증착법에 의해 성장된 무극성 α면 질화갈륨 박막 |
US6876009B2 (en) * | 2002-12-09 | 2005-04-05 | Nichia Corporation | Nitride semiconductor device and a process of manufacturing the same |
US7453129B2 (en) | 2002-12-18 | 2008-11-18 | Noble Peak Vision Corp. | Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry |
US7012314B2 (en) | 2002-12-18 | 2006-03-14 | Agere Systems Inc. | Semiconductor devices with reduced active region defects and unique contacting schemes |
KR100960764B1 (ko) * | 2003-01-28 | 2010-06-01 | 엘지전자 주식회사 | 레이저 발광 다이오드 및 그 제조 방법 |
FR2855650B1 (fr) * | 2003-05-30 | 2006-03-03 | Soitec Silicon On Insulator | Substrats pour systemes contraints et procede de croissance cristalline sur un tel substrat |
US7622318B2 (en) | 2004-03-30 | 2009-11-24 | Sony Corporation | Method for producing structured substrate, structured substrate, method for producing semiconductor light emitting device, semiconductor light emitting device, method for producing semiconductor device, semiconductor device, method for producing device, and device |
KR100735488B1 (ko) * | 2006-02-03 | 2007-07-04 | 삼성전기주식회사 | 질화갈륨계 발광다이오드 소자의 제조방법 |
KR100773555B1 (ko) * | 2006-07-21 | 2007-11-06 | 삼성전자주식회사 | 저결함 반도체 기판 및 그 제조방법 |
US7825432B2 (en) * | 2007-03-09 | 2010-11-02 | Cree, Inc. | Nitride semiconductor structures with interlayer structures |
US8362503B2 (en) | 2007-03-09 | 2013-01-29 | Cree, Inc. | Thick nitride semiconductor structures with interlayer structures |
JP4638958B1 (ja) * | 2009-08-20 | 2011-02-23 | 株式会社パウデック | 半導体素子の製造方法 |
CN102427101B (zh) * | 2011-11-30 | 2014-05-07 | 李园 | 半导体结构及其形成方法 |
CN104221129A (zh) * | 2012-04-13 | 2014-12-17 | 坦德姆太阳能股份公司 | 基于外延生长来制造半导体设备的方法 |
WO2016184523A1 (de) * | 2015-05-21 | 2016-11-24 | Ev Group E. Thallner Gmbh | Verfahren zur aufbringung einer überwuchsschicht auf eine keimschicht |
CN106469648B (zh) * | 2015-08-31 | 2019-12-13 | 中国科学院微电子研究所 | 一种外延结构及方法 |
WO2021237528A1 (zh) * | 2020-05-27 | 2021-12-02 | 苏州晶湛半导体有限公司 | Ⅲ族氮化物结构及其制作方法 |
WO2021261494A1 (ja) * | 2020-06-22 | 2021-12-30 | 京セラ株式会社 | 半導体デバイスの製造方法、半導体デバイス、電子機器、半導体エピタキシャル基板の製造方法および半導体エピタキシャル基板 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04127521A (ja) * | 1990-09-19 | 1992-04-28 | Fujitsu Ltd | 半導体基板の製造方法 |
JPH04303920A (ja) * | 1991-03-29 | 1992-10-27 | Nec Corp | Iv族基板上の絶縁膜/iii −v族化合物半導体積層構造 |
JP3830051B2 (ja) * | 1995-09-18 | 2006-10-04 | 株式会社 日立製作所 | 窒化物半導体基板の製造方法、窒化物半導体基板、光半導体装置の製造方法および光半導体装置 |
JP3757339B2 (ja) * | 1995-12-26 | 2006-03-22 | 富士通株式会社 | 化合物半導体装置の製造方法 |
JPH09219540A (ja) * | 1996-02-07 | 1997-08-19 | Rikagaku Kenkyusho | GaN薄膜の形成方法 |
JP3139445B2 (ja) * | 1997-03-13 | 2001-02-26 | 日本電気株式会社 | GaN系半導体の成長方法およびGaN系半導体膜 |
JPH10326912A (ja) * | 1997-03-25 | 1998-12-08 | Mitsubishi Cable Ind Ltd | 無転位GaN基板の製造方法及びGaN基材 |
JPH11191657A (ja) * | 1997-04-11 | 1999-07-13 | Nichia Chem Ind Ltd | 窒化物半導体の成長方法及び窒化物半導体素子 |
JPH10321529A (ja) * | 1997-05-22 | 1998-12-04 | Nippon Telegr & Teleph Corp <Ntt> | 2層選択成長法 |
JPH11135770A (ja) * | 1997-09-01 | 1999-05-21 | Sumitomo Chem Co Ltd | 3−5族化合物半導体とその製造方法および半導体素子 |
JP3925753B2 (ja) * | 1997-10-24 | 2007-06-06 | ソニー株式会社 | 半導体素子およびその製造方法ならびに半導体発光素子 |
-
1999
- 1999-02-26 EP EP99908553A patent/EP1070340A1/en not_active Ceased
- 1999-02-26 JP JP2000533892A patent/JP2002505519A/ja active Pending
- 1999-02-26 KR KR1020007009261A patent/KR100610396B1/ko not_active IP Right Cessation
- 1999-02-26 CN CNB998034002A patent/CN1143363C/zh not_active Expired - Lifetime
- 1999-02-26 WO PCT/US1999/004346 patent/WO1999044224A1/en not_active Application Discontinuation
- 1999-02-26 CA CA002321118A patent/CA2321118C/en not_active Expired - Lifetime
- 1999-02-26 AU AU27956/99A patent/AU2795699A/en not_active Abandoned
Non-Patent Citations (1)
Title |
---|
See references of WO9944224A1 * |
Also Published As
Publication number | Publication date |
---|---|
KR20010041192A (ko) | 2001-05-15 |
WO1999044224A1 (en) | 1999-09-02 |
CA2321118A1 (en) | 1999-09-02 |
AU2795699A (en) | 1999-09-15 |
KR100610396B1 (ko) | 2006-08-09 |
CN1143363C (zh) | 2004-03-24 |
CA2321118C (en) | 2008-06-03 |
CN1292149A (zh) | 2001-04-18 |
JP2002505519A (ja) | 2002-02-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6608327B1 (en) | Gallium nitride semiconductor structure including laterally offset patterned layers | |
US6051849A (en) | Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer | |
CA2331893C (en) | Fabrication of gallium nitride semiconductor layers by lateral growth from trench sidewalls | |
CA2321118C (en) | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby | |
US6462355B1 (en) | Pendeoepitaxial gallium nitride semiconductor layers on silicon carbide substrates | |
US6602764B2 (en) | Methods of fabricating gallium nitride microelectronic layers on silicon layers | |
US6955977B2 (en) | Single step pendeo-and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures | |
US20040029365A1 (en) | Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby | |
JP4947867B2 (ja) | 窒化ガリウム系半導体構造及び該半導体構造を製造する方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20000926 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R003 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
|
18R | Application refused |
Effective date: 20151016 |