Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3002—Conversion to or from differential modulation
  • H03M7/3004—Digital delta-sigma modulation
  • H03M7/3015—Structural details of digital delta-sigma modulators
  • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
  • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
  • H03M7/3028—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
  • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • H03M7/3002—Conversion to or from differential modulation
  • H03M7/3004—Digital delta-sigma modulation
  • H03M7/3015—Structural details of digital delta-sigma modulators
  • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
  • H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
  • H03M7/304—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Definitions

• the invention relates to digital signal processing and specifically to controlling the level of a pulse density modulation (PDM) signal generated by a sigma-delta modulator.
• PDM pulse density modulation
• the basic operations of signal processing, multiplication and addition can be implemented in a known manner by analog signal processing blocks, or an analog signal can be converted into a digital one by using an A/D converter and the desired signal processing operations can be performed digitally.
• the results can be reconverted into analog signals by using a D/A converter.
• the A/D and D/A conversions are performed at predetermined sample frequency and at a predetermined resolution.
• A/D and D/A convertors based on sigma-delta modulators have become very common recently.
• a sigma- delta A/D convertor a conversion of an analog signal into a baseband digital signal occurs at two stages. At the first stage, an input signal is converted by a sigma- delta modulator into an oversampled single-bit or multibit signal. At the second stage, this oversampled single-bit or multibit signal is decimated to the baseband by using digital filtering.
• Sigma-delta technique and converters are described for instance in the following articles:
• An oversampled output signal of a sigma-delta modulator is a pulse density modulated (PDM) representation of an input signal.
• PDM pulse density modulated
• the modulator converts an analog signal into a pulse density modulated (PDM) format.
• the PDM signal consists of an oversampled single-bit or multibit (e.g.
• the relative pulse density of the PDM signal determine represents the amplitude of the input signal.
• the baseband part of the spectrum of the PDM signal is the useful signal band, and at higher frequencies of the spectrum, there is quantization noise produced by a noise processing function of the sigma-delta modulator. It has thus been possible to change the resolution at signal frequencies for over-sampling rate.
• the noise processing performance of the sigma-delta modulator depends on the order of the modulator, and higher-order modulators remove quantization noise more efficiently from the signal band. By increasing the oversa ple ratio, the signal band can also be made narrower, in proportion, and the amount of the noise falling on the signal band smaller.
• the amount of noise in the signal band in a sigma-delta modulator can be controlled by the transfer function of the modulator, e.g. by inserting zeroes at suitable frequencies in the transfer function of the modulator.
• FIG. 1 of the above article [4] shows a sigma-delta attenuator, in which an oversampled 1-bit signal (PDM) is multiplied by a multibit coefficient al and the resulting multibit signal is applied to a digital sigma-delta modulator outputting a 1-bit PDM signal.
• PDM oversampled 1-bit signal
• the multiplier of the 1- bit PDM signal is implemented as a 2 -input multiplexor
• the article also describes a digital sigma-delta filter suitable for this purpose.
• the attenuator is possible to implement when said multibit coefficient is lower than one.
• the feedback value of the sigma-delta modulator being b and said coefficient being a, an attenuation ratio a/b is obtained.
• a problem with this known solution is that only an attenuation of a PDM signal has been possible, and therefore, it has been necessary to perform all multiplications by coefficients lower than one.
• the sigma-delta modulator is a conditionally stable structure and the output signals of integrators escape upon the input exceeding a predetermined value.
• the input value is allowed to be normally, depending on the order and the structure of the modulator, approximately 0.3 to 0.7 times the feedback value, cf . article [3] .
• An amplification of the PDM signal in such a circuit would require an ingoing signal to be multiplied by a number higher than the feedback value.
• An object of the invention is a signal process- ing method and device, enabling also a relative amplification of a PDM signal, without the noise level increasing remarkably .
• the method is according to the invention characterized in that the M-bit signal is converted into the N-bit pulse density modulated signal by the digital sigma-delta modulator having a better signal-to-noise ratio performance than said first sigma- delta modulator.
• means for controlling the level of the pulse density modulated signal comprising a) a multibit multiplier, the input of which is the N-bit pulse density modulated signal and the output an M-bit signal, where M>N, b) a digital sigma-delta modulator converting the M-bit signal into the N-bit pulse density modulated signal .
• the system is according to the inven- tion characterized in that said digital sigma-delta modulator has a better signal-to-noise ratio performance than said first sigma-delta modulator.
• a single-bit pulse density modulated PDM signal is generated by the first sigma-delta modulator being an analog modulator, for instance.
• the level control is performed by multiplying the single-bit PDM signal by a multibit coefficient, so that a multibit stream of numbers is obtained.
• the number stream is reconverted into a single-bit PDM signal by a second sigma-delta modulator, preferably being a digital modulator.
• the signal-to-noise ratio performance of said second sigma-delta modulator is better than that of said first sigma-delta modulator. Accordingly, the most significant factor of the total signal-to-noise ratio (SNR) is the noise level of the first sigma-delta modulator, by which the PDM signal originally was generated.
• the PDM signal can be attenuated within a range which is equal to the difference between the SNR performances of the modulators, without any decrease in the total signal-to-noise ratio.
• the PDM signal can be attenuated in the second modulator by nearly 20 dB without any decrease in the signal-to-noise ratio. This is possible, because, in the latter modulator, besides the signal, naturally also the noise of the first modulator on the signal band is attenuated and approaches the noise floor set by the second modulator structure.
• the PDM signal has thus been scaled to a slightly lower level without any decrease in the performance.
• the attenuation may be less than said difference between the performances (20 dB in the above example) , whereby a relative amplification is achieved.
• the PDM signal is attenuated less than said difference between the SNR performances of the two modulators, the same total signal-to-noise ratio is obtained as by the preceding analog modulator.
• the nominal level of the signal can be fixed to a point where the first modulator gives an unattenuated signal and the second modulator attenuates the signal by 20 dB .
• the second-order attenuation may be C.
• the total signal-to-noise ratio will then be 90 dB, the signal being between +20 - 0 dB and 90 + 20 - (c) , c being between 20 and 110 dB, and the attenuation of the system thus between 0 and 90 dB .
• FIG. 1 is a block diagram illustrating a PDM level controller according to the invention, connected after an analog sigma-delta A/D modulator;
• Figure 2 is a graph showing noise and signal levels of an analog sigma-delta modulator and a digital sigma-delta modulator and a controlling area at disposal as a function of frequency;
• Figure 3 is a block diagram showing a multichannel PDM level controller.
• an analog sigma- delta modulator 2 performs an A/D conversion of an analog input signal at an input 1 into a 1-bit pulse density modulated (PDM) format.
• the modulator 2 may be, for instance, any sigma-delta A/D modulator structure described in the article [1] . Let us assume that the modulator 2 is a third-order sigma-delta modulator having a signal-to-noise ratio of about lOOdB. A single-bit PDM signal, which may obtain the values +1 and -1, is applied to a PDM level controller 3.
• the PDM level controller 3 comprises a digital modulator 4 and a preceding multiplier 300.
• Level control is performed by multiplying the single-bit pulse density modulated (PDM) signal by a multibit coefficient a in the multiplier 300 in order to obtain a multibit number stream, which is reconverted into a single-bit PDM signal by means of a digital sigma-delta modulator 4.
• the multiplier 300 can be implemented by a simple multiplexor or selector, generating an output +a or -a depending on whether the input value is +1 or -1.
• the output of the multiplier 300 is thus a multibit number stream consist- ing of the numbers +a and -a.
• the multiplier 300 may have a structure similar to the one disclosed in the article [4] .
• the multiplier may have one fixed coefficient or the value of the coefficient may be adjustable.
• a selection signal SELECT may choose one of several coefficients al...an, and accordingly, a desired attenuation or amplification can be set.
• the coefficients may be in accordance with Table 1, for instance.
• the Table indicates 32 values of the coefficient a, giving a level control range of +12 dB ...-34,5 dB by 1.5 dB steps .
• the digital modulator 4 is a fourth-order modulator, comprising summers 400 to 403, integrators 404 to 407, a quantizer 408 and feedbacks 409 to 412, having the feedback coefficients rl to r4 , respectively. It is to be noted that a detailed implementation and structure of the modulator 4 is of no significance for the invention. Only the fact that the performance of the modulator 4 is better than that of the modulator 2 is of significance for the invention, as will be described below.
• the input of the modulator 4 is said number stream consisting of the numbers +a and -a.
• the output 5 of the modulator 4 is a 1-bit oversampled PDM signal. The level of the PDM signal is controlled in the level controller 3 at the ratio a/rl .
• the input value of the modulator 4 cannot approach the internal reference voltage value of the modulator, which means that the coefficient a shall be lower than the feedback coefficient rl . Therefore, the PDM signal can only be attenuated in the multiplier 300.
• the noise processing performance of the modulator 4 may be higher thanks to higher order, multibit quantization and feedback or higher oversampling ratio, or some combination of these, for instance.
• the modulator 4 is a fourth- order modulator, while the modulator 2 is a third-order modulator.
• the noise level of the lower-level modulator is most decisive for the total signal-to-noise ratio (SNR) of the system.
• SNR signal-to-noise ratio
• the signal-to-noise ratio at the output 5 is thus primarily determined on the basis of the signal-to-noise ratio of the modulator 2.
• the performance of the modulator 4 shall be at least a desired need of amplification and preferably also a suitable stability margin better than the signal-to-noise ratio of the modulator 2 and the incoming PDM signal.
• the level controller may lower the level of the whole PDM signal without practically any decrease in the signal-to- noise ratio at all. This is possible, because in addition to the noise of a payload signal, also the noise of the PDM signal is attenuated. The signal has thus been scaled to a slightly lower level without any decrease in the performance. Though the PDM signal is attenuated also in the modulator 4, it is possible to attenuate the signal in the level controller 3 less than said difference between the performances of the modulators 2 and 4 and to achieve a relative amplification. Let us examine the operation of the level controller according to the invention by way of example with reference to the graph of Figure 3.
• the analog modulator 2 is a third-order modulator, the signal-to-noise ratio of which is about 100 dB .
• the modulator 4 is a fourth-order digital modulator, the signal-to-noise ratio of which is about 120 dB, i.e. about 20 dB better than that of the modulator 2.
• the desired control range is +12 dB...-34,5 dB by 1.5 dB steps.
• the ratio a/rl is 0.5, i.e. -6 dB.
• the value of the reference rl can be calculated as a function of the maximum attenuation (-34.5 dB) and the required accuracy ( ⁇ 0.3 dB) . Accordingly, the reference value is assumed to be
• the signal-to-noise ratio remains approximately the same in the range +12... -1.5 dB as it is after the modulator 2.
• the noise of the very input signal is attenuated below a noise floor 22 of the modulator 4, the attenuated payload signal 25 and the noise floor 22 determining the signal-to-noise ratio at the output 5.
• the invention is described above in conjunction with a 1-bit PDM signal.
• the invention can, however, be applied directly to a multibit, e.g. 2 -bit to 4 -bit, PDM signal as well .
• FIG. 1 shows the analog modulator 2, the multiplier 300 and the digital modulator 4 sequentially connected. In practice, these units may be located apart from each other in the signal processing system in such a way that there are other signal processing stages between them. An example of such a signal processing system is shown in Figure 3.
• Figure 3 shows three analog input signals 31,
• the modulators 34, 35 and 36 generate PDM signals 37, 38 and 39, respectively, which are applied to multipliers 40, 41 and 42, respectively.
• the multipliers 40, 41 and 42 generate multibit number streams 43, 44 and 45, respectively, which are summed in a summer 46 to a multibit number stream 47.
• the signal 47 is converted into a PDM signal 49 by a digital sigma-delta modulator.
• the modulators 34 to 36 may have a structure similar to that of the modulator 2 in Figure 1.
• the structure of the multipliers 40 to 42 may be similar to that of the multiplier 300 in Figure 1.
• the modulator 48 may have a structure similar to that of the modulator 4 in Figure 1.
• An application of the signal processing apparatus of the type shown in Figure 3 is an audio mixing board.
• the invention can be applied to the level control of a PDM signal in all sigma-delta structures.
• Typical objects of application are, besides audio applications, also IIR and FIR filter structures.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)
• Analogue/Digital Conversion (AREA)

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• 1997
  • 1997-10-09 FI FI973919A patent/FI103745B1/fi active
• 1998
  • 1998-08-26 CN CN98804731A patent/CN1112777C/zh not_active Expired - Fee Related
  • 1998-08-26 CA CA002274637A patent/CA2274637A1/en not_active Abandoned
  • 1998-08-26 JP JP52178599A patent/JP2002510455A/ja not_active Ceased
  • 1998-08-26 EP EP98942269A patent/EP1021876A4/en not_active Ceased
  • 1998-08-26 KR KR1019997010300A patent/KR20010012348A/ko active IP Right Grant
  • 1998-08-26 WO PCT/US1998/017743 patent/WO1999020004A1/en active IP Right Grant
  • 1998-10-01 MY MYPI98004505A patent/MY133001A/en unknown
  • 1998-12-11 TW TW087120605A patent/TW408531B/zh not_active IP Right Cessation
• 1999
  • 1999-06-08 NO NO992777A patent/NO992777L/no not_active Application Discontinuation
• 2000
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