EP0976156A1 - Circuit integre a plusieurs composants et son procede de production - Google Patents

Circuit integre a plusieurs composants et son procede de production

Info

Publication number
EP0976156A1
EP0976156A1 EP98925394A EP98925394A EP0976156A1 EP 0976156 A1 EP0976156 A1 EP 0976156A1 EP 98925394 A EP98925394 A EP 98925394A EP 98925394 A EP98925394 A EP 98925394A EP 0976156 A1 EP0976156 A1 EP 0976156A1
Authority
EP
European Patent Office
Prior art keywords
substrate
metal
component
components
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98925394A
Other languages
German (de)
English (en)
Inventor
Anton Anthofer
Holger HÜBNER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0976156A1 publication Critical patent/EP0976156A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

Definitions

  • the control logic has been galvanically isolated from the power semiconductors (see A. Nakagawa et al. ISPS 1990, pp. 97 to 101).
  • the modules were integrated on silicon wafers, which have a thin Si0 2 layer below the active Si region.
  • the galvanic isolation was achieved by etching trenches around the circuits that extend as far as the insulating SiO 2 layer.
  • the resulting shielding of the control logic against coupling is deficient against high-frequency interference pulses. Fast switching operations can trigger an uncontrolled response of the logic.
  • US Pat. No. 5,306,942 discloses an integrated circuit arrangement with at least one component which is arranged in a first substrate and which is shielded by a shielding structure from electrical fluctuations in the first substrate which are caused by a further component of the circuit arrangement.
  • a shielding structure is created which laterally surrounds a lower half of the component and which comprises a lower horizontal shielding element.
  • a method is described in which an annular depression is produced in a surface of a substrate. Then An insulating layer and a layer of polysilicon are deposited. A thick layer of Si0 2 is deposited over it and planarized. A second substrate is applied as a carrier to the planarized surface of the layer of SiO 2 .
  • the back of the first substrate is then sanded thinly until the insulating layer is exposed.
  • Parts of the conductive layer serve as a shielding structure.
  • source / drain regions are produced by implantation.
  • a gate electrode and contacts are created above it. Since high temperatures are required for the application of the carrier and for the generation of the source / drain regions, doped polysilicon, which has a high melting temperature, is used for the shielding structure.
  • JP 61/290 753 shows an integrated circuit arrangement in which a side metallic structure is arranged next to a component. For this purpose, depressions are arranged in a surface of a substrate, which is adjacent to the component, which are lined with an insulating layer and filled with conductive material.
  • EP 0 567 694 AI describes an integrated circuit arrangement with at least two blocks which are separated from one another by an insulating layer. A metallic plate is placed between them to limit capacitive coupling between the first and second blocks.
  • US 5 122 856 describes a circuit arrangement integrated in a substrate which can transmit electrical signals from a surface of the substrate to a rear side of the substrate. This is done in the back of the substrate a recess is made, which is lined with an insulating layer. A contact element runs along a flank of the depression. Stacks comprising components can be arranged one above the other by connecting electrodes of the components to one another by heating.
  • US 5 266 511 describes a three-dimensional integrated circuit arrangement in which substrates comprising components are stacked one above the other. The components are arranged in monocrystalline layers. The connection of the substrates is effected by heating two adjacent SiO 2 layers of the substrates to approximately 90020 ° C. Contacts connect components stacked one above the other electrically.
  • the invention is based on the problem of an integrated circuit arrangement in which components are shielded against the coupling in of high-frequency interference pulses, and of specifying a method for their production.
  • component is used here both for individual elements, such as diodes and transistors, and for circuit structures that comprise several elements.
  • Protecting components with a metallic shielding structure has the advantage of avoiding the high costs associated with the use of disks containing SiO 2 described above.
  • the metallic shielding structure protects the components from interference pulses not only from neighboring power semiconductors, but from every source. The need for additional shielding against interference from the environment is eliminated. This keeps the volume of the chips particularly small.
  • the components can be integrated into a three-dimensional circuit arrangement.
  • Substrates comprising components are stacked together in a stack.
  • the three-dimensional arrangement increases the possible combinations in terms of material and manufacturing process of the various components.
  • sensor elements or fast GaAs RF transistors can be combined with silicon CMOS logic.
  • the surfaces of the components are provided with a metal layer and then their electrical contacts are electrically insulated from the metal layer by etching away the metal layer around the contacts.
  • the metal layers of two components that will adjoin one another in the stack to use two different metals whose alloy has a melting temperature above the melting temperature of at least one metal. If the components are brought together and their metal layers are heated to a temperature below the melting temperature of the alloy, at which one metal is solid and the other is liquid, the metals mix, which, due to the higher melting temperature of the alloy, hardens has the consequence. As a result, the metals of the shielding structure serve at the same time for the firm connection of two components adjacent in the stack. It is advantageous to use tin as the one metal because it has a low melting temperature. Copper can be chosen as the other metal.
  • auxiliary layer of, for example, Ti or TiN to the surfaces of the components before attaching the metals, which improves the adhesion of the metal layer and which forms a barrier against diffusion of the metals into metallic parts of the surface of the components.
  • Figure 1 shows a section of a cross section through a first substrate, in the upper layer of a component with an upper and a lower
  • FIG. 2 shows the first substrate, on the upper surface of which an auxiliary layer and an upper horizontal shielding element are applied.
  • FIG. 3 shows a second substrate, in the upper layer of which there is a component with an upper and a lower contact and an electrical connection, which is surrounded by a depression in the upper layer, which is interrupted for the implementation of the electrical connection.
  • FIG. 4 shows the second substrate, on the upper surface of which an auxiliary layer is applied and an upper horizontal shielding element and a first lateral shielding element are produced.
  • FIG. 5 shows a third substrate, in the upper layer of which there is a component with an upper and a lower contact and an electrical connection, which is surrounded by a depression provided with an insulation layer.
  • FIG. 6 shows the first substrate, which is ground thinly from below and in which depressions are produced on its lower surface, on the one hand on the first lateral shielding element in the upper
  • the side walls of the depressions and the lower surface of the substrate are provided with an insulation layer.
  • FIG. 7 shows the first substrate after an auxiliary layer and a lower shielding element have been applied to the lower surface.
  • FIG. 8 shows two substrates arranged one above the other, which are connected.
  • a first substrate 1 is, for example, an undiluted semiconductor wafer made of single-crystal silicon or an III-V semiconductor, which comprises one or more components.
  • a component of the first substrate 1 contains, for example, a transistor or a circuit structure consisting of a plurality of metal and / or semiconductor layers which are embedded in an insulating environment which may contain intermetallic oxides, for example what is not shown in detail.
  • the area of the circuit structure is marked with S.
  • the construction ment has electrical contacts and connections.
  • An upper contact K1, a lower contact K2 and an electrical connection E are shown in FIG. 1, for example.
  • a first side shielding element Ala made of metal surrounds the area of the
  • Circuit structure S It is interrupted at the location of the electrical connection E such that electrical contact from the first lateral shielding element Ala to the electrical connection E is avoided.
  • the first side shielding element Ala is produced simultaneously with the circuit structure and thus consists of the same metal as the metal parts of the circuit structure.
  • An upper auxiliary is layer Hl and above an existing metal top horizontal shielding member A2a applied (see Fig. "2) on the surface of the substrate 1.
  • A2a applied (see Fig. "2) on the surface of the substrate 1.
  • the first layer consists of a material , for example Ti or TiN, which facilitates the wetting of the surface with metal and is, for example, 100 nm thick.
  • a second layer of metal is then applied, for example by sputtering or vaporization with an electron beam, over the first layer. Tin, gallium, nickel or tungsten and is, for example, 1 to 2 ⁇ m thick.
  • auxiliary layer Hl Layer that wets the surface well without the upper auxiliary layer Hl can be dispensed with the upper auxiliary layer Hl. If tin is used, an additional auxiliary layer located above the upper auxiliary layer H1, which is formed like the upper auxiliary layer H1, can be applied and which contains, for example, copper and is, for example, 20 nm thick.
  • a substrate 1 ' which comprises at least one component, an upper contact K 1', a lower contact K 2 'and an electrical connection E' are provided in a manner analogous to that in the first exemplary embodiment (see FIG. 3).
  • a photoresist mask (not shown) is applied to the substrate 1 '.
  • the photoresist mask is used as an etching mask to produce a depression V.
  • the depression V surrounds the component laterally.
  • the recess V has an interruption U above the electrical connection E '(see FIG. 3).
  • An upper auxiliary layer H1 ' is applied to the surface of the substrate 1', an upper horizontal shielding element A2a 'made of metal and first lateral shielding element Ala' are applied over it (see FIG. 4).
  • a first layer and a second layer are generated analogously to the first exemplary embodiment.
  • Anisotropic etching, with the aid of a photoresist mask (not shown), removes parts of the first and second layers which do not cover the component and electrically isolates the contact Kl '. This creates the upper auxiliary layer Hl ', the upper horizontal shielding element A2a' and the first lateral shielding element Ala '.
  • a substrate 1 ′′ which comprises at least one component, an upper contact K 1 ′′, a lower contact K 2 ′′ and an electrical connection E ′′ are provided in a manner analogous to that in the first and second exemplary embodiments (see FIG. 5 ).
  • a photoresist mask (not shown) is applied to the substrate 1 ′′.
  • anisotropic etching for example plasma etching
  • the photoresist mask is used to generation of a depression V 'used as an etching mask.
  • an insulation layer is deposited on the surface and structured using an photoresist mask (not shown) by anisotropic etching. This creates an insulation 2, which covers the side walls of the depression V 'and surfaces of the electrical connection E''.
  • the substrate 1 it is within the scope of the invention after the production of the upper horizontal shielding element A2a on the upper surface to glue the substrate 1 to a carrier and then to thinly grind the lower side of the substrate 1. It is applied, for example, by sputtering to a resulting lower surface of the substrate 1 insulating material, for example SiO 2 , so that the lower surface is completely covered.
  • a photoresist mask (not shown) is then applied to the lower surface.
  • anisotropic etching for example plasma etching
  • the photoresist mask is used as an etching mask to produce a depression VI or V2 (see FIG. 6).
  • the recess VI is made so that it meets the first side shielding element Ala from below.
  • the recess V2 extends to the lower contact K2. It is applied, for example, by sputtering over the entire surface of the insulating material, for example Si0 2 , as a result of which the lower surface is covered thicker by insulating material than the side surfaces and bottoms of the depressions VI and V2. Anisotropic etching removes the insulating material from the bottoms of the depression VI and the depression V2, so that an insulation I is formed which covers the depressions VI and V2 only on the side walls and the lower surface (see FIG. 6). Subsequently, a lower auxiliary layer H2 is applied to the lower side of the substrate 1, and a second lateral shielding element Alb made of metal and a lower horizontal shielding element A2b are applied over it (see FIG.
  • a third layer is first generated, for example by sputtering.
  • the third layer consists of a material, for example Ti or TiN, which facilitates the wetting of the surface with metal and is, for example, 100 nm thick.
  • a fourth layer of metal is then applied, for example by sputtering or evaporation with an electron beam, over the third layer.
  • the fourth layer contains, for example, copper, tin, gallium, nickel or tungsten and is, for example, 1 to 2 ⁇ m thick.
  • the lower auxiliary layer H2 When using a metal of the fourth layer, which wets the surface of the insulation I well, the lower auxiliary layer H2 can be dispensed with. If tin is used, an additional one above the lower one
  • Substrate la has an upper electrical contact Kl *, a lower electrical contact K2 *, an electrical connection E *, a first side shielding element Ala *, a second side shielding element Alb *, an upper horizontal shielding element A2a *, a lower horizontal shielding element A2b * , an insulation I *, an upper auxiliary layer Hl * and a lower auxiliary layer H2 * analogous to the embodiment shown in FIG. 7.
  • the substrate 1b has an upper electrical contact K1 **, a lower electrical contact K2 **, an electrical connection E **, an insulation I ** and a lower auxiliary layer H2 ** analogous to the exemplary embodiment shown in FIG .
  • a metal layer (not shown) covers the auxiliary layer H2 **.
  • the substrates are arranged so that the contact K2 ** is electrically connected to the contact Kl *.
  • the metal layer and the upper horizontal shielding element A2a are soldered together, as a result of which the substrates 1a and 1b are firmly connected.
  • the metal of the metal layer and for the metal of the upper shielding element A2a the alloy of which has a melting temperature which is above the melting temperature of at least one metal.
  • the connection of the substrates la and lb is then carried out by heating to a temperature below the melting temperature of the alloy, at which one metal is solid and the other liquid, whereby the metals mix, which, due to the higher melting temperature of the alloy, leads to hardening Consequence.
  • the metal of the upper horizontal shielding element A2a * serves at the same time for the firm connection of the substrates la and lb.
  • At least one undiluted substrate such as that substrate from the exemplary embodiment shown in FIG. 1 or 2, in the stack.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un circuit intégré contenant plusieurs composants dont au moins un est entouré d'une structure de blindage métallique. Ce composant est ainsi protégé contre l'entrée d'impulsions parasites provenant de son environnement. En particulier, les composants de ce circuit peuvent être disposés les uns à côté des autres ou les uns sur les autres. Pour réaliser la structure de blindage métallique d'un composant du circuit, on forme au moins une cavité qui entoure le composant et dans laquelle on applique un revêtement métallique. Les contacts et les liaisons électriques du composant sont isolés électriquement du métal constituant la structure de blindage. Pour relier deux composants à l'intérieur d'un circuit tridimensionnel, on peut recouvrir les surfaces en vis à vis desdits composants avec deux métaux différents, dont l'alliage présente une température de fusion (Ts) qui est supérieure à la température de fusion (T1) d'au moins un des métaux, le chauffage à une température comprise entre les deux températures de fusion ayant pour résultat un assemblage solide.
EP98925394A 1997-04-17 1998-03-13 Circuit integre a plusieurs composants et son procede de production Withdrawn EP0976156A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19716102A DE19716102C2 (de) 1997-04-17 1997-04-17 Integrierte Schaltungsanordnung mit mehreren Bauelementen und Verfahren zu deren Herstellung
DE19716102 1997-04-17
PCT/DE1998/000769 WO1998048459A1 (fr) 1997-04-17 1998-03-13 Circuit integre a plusieurs composants et son procede de production

Publications (1)

Publication Number Publication Date
EP0976156A1 true EP0976156A1 (fr) 2000-02-02

Family

ID=7826820

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98925394A Withdrawn EP0976156A1 (fr) 1997-04-17 1998-03-13 Circuit integre a plusieurs composants et son procede de production

Country Status (7)

Country Link
US (1) US6597053B1 (fr)
EP (1) EP0976156A1 (fr)
JP (1) JP3786429B2 (fr)
KR (1) KR100433870B1 (fr)
DE (1) DE19716102C2 (fr)
TW (1) TW405218B (fr)
WO (1) WO1998048459A1 (fr)

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DE19853703A1 (de) 1998-11-20 2000-05-25 Giesecke & Devrient Gmbh Verfahren zur Herstellung eines beidseitig prozessierten integrierten Schaltkreises
DE10003112C1 (de) * 2000-01-13 2001-07-26 Infineon Technologies Ag Chip mit allseitigem Schutz sensitiver Schaltungsteile vor Zugriff durch Nichtberechtigte durch Abschirmanordnungen (Shields) unter Verwendung eines Hilfschips
US8212331B1 (en) * 2006-10-02 2012-07-03 Newport Fab, Llc Method for fabricating a backside through-wafer via in a processed wafer and related structure
EP2031653B1 (fr) * 2007-08-27 2014-03-05 Denso Corporation Procédé de fabrication pour un dispositif à semi-conducteur disposant de plusieurs régions de formation d'éléments
KR101131782B1 (ko) 2011-07-19 2012-03-30 디지털옵틱스 코포레이션 이스트 집적 모듈용 기판
US8890247B2 (en) * 2012-10-15 2014-11-18 International Business Machines Corporation Extremely thin semiconductor-on-insulator with back gate contact
US9786613B2 (en) 2014-08-07 2017-10-10 Qualcomm Incorporated EMI shield for high frequency layer transferred devices
DE102016125042A1 (de) * 2015-12-28 2017-06-29 Oerlikon Surface Solutions Ag, Pfäffikon Infrarotspiegel mit einer thermisch stabilen Schicht

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Also Published As

Publication number Publication date
JP3786429B2 (ja) 2006-06-14
US6597053B1 (en) 2003-07-22
DE19716102A1 (de) 1998-10-22
KR100433870B1 (ko) 2004-06-04
DE19716102C2 (de) 2003-09-25
KR20010006415A (ko) 2001-01-26
WO1998048459A1 (fr) 1998-10-29
JP2001517376A (ja) 2001-10-02
TW405218B (en) 2000-09-11

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