EP0823129A1 - Capot de puce - Google Patents

Capot de puce

Info

Publication number
EP0823129A1
EP0823129A1 EP96908022A EP96908022A EP0823129A1 EP 0823129 A1 EP0823129 A1 EP 0823129A1 EP 96908022 A EP96908022 A EP 96908022A EP 96908022 A EP96908022 A EP 96908022A EP 0823129 A1 EP0823129 A1 EP 0823129A1
Authority
EP
European Patent Office
Prior art keywords
chip
activator
cover according
chip cover
cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96908022A
Other languages
German (de)
English (en)
Inventor
Detlef Houdeau
Josef Kirschbauer
Christl Niederle
Peter Stampka
Hans-Hinnerk Steckhan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0823129A1 publication Critical patent/EP0823129A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
  • Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
  • the chip covers have hitherto been removable, for example by chemical methods (for example using smoking HNO3), so that a precise analysis of the chip circuit and / or manipulations of the chip chips can be carried out in a relatively simple manner. Circuit is possible.
  • the chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip and to find possibilities by manipulating suitable bridges or the like, he can thereby be able to use a fee-based service free of charge.
  • the present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
  • an activator which, when activated, is capable of completely or partially destroying the electrical, electronic, optoelectronic and / or electromechanical components of the chip, and by attempting to remove the chip cover from the chip , can be activated.
  • the figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. It although a section is shown, hatching has been omitted for reasons of clarity.
  • reference number 1 denotes a first chip without a housing in the form of a controller.
  • the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller.
  • the first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
  • the system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead fra e.
  • Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
  • the conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5.
  • This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness.
  • a second chip cover layer in the form of a polyimide layer 6 is provided above the Si3N4 layer 5.
  • the polyimide layer 6 protects the underlying chip structures from mechanical damage.
  • cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
  • ASIC component customer-specific component
  • the second chip 8 is glued to the previously mentioned polyimide layer 6 by means of an adhesive 9.
  • the second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure.
  • the contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
  • the Globe Top 11 is made of epoxy resin.
  • the first to third chip cover layers 5, 6 and 11 and the adhesives 2, 8 generally consist of materials which can be removed chemically.
  • smoking HNO3 is suitable for this, since it destroys the chip cover, but not the conductor tracks 4 and contact points 7 made of aluminum.
  • activators are provided in the chip cover above these areas.
  • the security-relevant area which is to be protected against external analysis and manipulation is the controller chip 1 which is generally located below in the case of chips arranged one above the other. This area should also be the safety-relevant area in the present exemplary embodiment.
  • the activator is a substance that is activated when it meets a substance that chemically dissolves the chip cover in the form of a solvent, an etching agent or the like, that is to say, for example, when it meets smoking HNO3.
  • a substance with a reducing effect is released, which destroys chip structures made of aluminum, such as the conductor tracks 4, and thus makes external analysis and / or manipulation of the security-relevant chip areas impossible.
  • the activator When not activated, the activator does not attack the chip.
  • the activator is formed by RCI2.
  • Free radicals are formed which, owing to their reducing character, destroy the aluminum structures lying under the chip cover.
  • activators which release oxidizing substances when they meet HNO3, does not lead to the desired success here, because oxidizing substances only influence the aluminum structures until they are coated with an oxide layer, which then forms the aluminum structure gives a self-protection function and therefore does not lead to destruction of the aluminum structures.
  • the activators designated by the reference numeral 12 in the figure can be provided above the security-sensitive area in window-like spaces or recesses which are exposed in the Si 3 4 layer 5 and / or in the polyimide layer 6 for this purpose; In the finished state of the chip card, smart card and the like, the activator is encased by the chip cover in these free spaces or recesses.
  • the activator can also be inserted into the polyimide matrix.
  • the position and location of the activator can be adapted to the changing requirements or the respective chips.
  • the type of activator is preferably adapted to the chemical substances that are suitable for dissolving the chip cover, so that the desired activation of the activator reliably occurs when any solvent meets the activator.
  • the effect of the activation can, however, be chosen as long as this only prevents the analysis and / or the manipulation of the chip.
  • it could also be provided, for example, to destroy the chip by generating heat energy or the like.
  • It can also be provided to provide several different activators, each of which reacts with different solvents in the manner intended, so that even the most varied types of solvents activate at least one activator each.
  • a separate substance can be provided in the chip cover in the same way as the activator, which substance is capable of activating the activator as intended.
  • the activator substance can thus be selected independently of the solvents in question, because when the chip cover is removed, both the activator and the substance which is intended to activate it are released.
  • the provision of the activator described above in the chip cover enables the safety-relevant areas of the chip to be destroyed automatically if an attempt is made to make them accessible by removing the chip cover.
  • the amount of activator to be provided is likewise extremely small with appropriate positioning.
  • Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, ie in the present embodiment, the ASIC chip 2 exactly above the security-relevant area of the other chip, ie in the present embodiment exactly above the most security-relevant area of the controller chip 1 is arranged. In the absence of optical accessibility, this also prevents the possibility of being able to analyze and / or manipulate the chip without removing the cover.
  • the exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un capot de puce (5, 6, 11) destiné à recouvrir totalement ou partiellement des composants électriques, électroniques, optoélectroniques et/ou électromécaniques d'une puce (1, 8). Ce capot de puce (5, 6, 11) se caractérise par le fait qu'un activateur (12), lorsqu'il est activé, peut détruire totalement ou partiellement les composants électriques, électroniques, optoélectroniques et/ou électromécaniques de la puce (1, 8), et peut être activé par tentative d'éloignement du capot (5, 6, 11) de la puce (1, 8). Ce système permet d'éviter de manière fiable, tout risque d'analyses d'origine extérieure et/ou de manipulations frauduleuses de la puce (1, 8).
EP96908022A 1995-04-25 1996-04-09 Capot de puce Ceased EP0823129A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19515188 1995-04-25
DE19515188A DE19515188C2 (de) 1995-04-25 1995-04-25 Chip-Abdeckung
PCT/DE1996/000616 WO1996034409A1 (fr) 1995-04-25 1996-04-09 Capot de puce

Publications (1)

Publication Number Publication Date
EP0823129A1 true EP0823129A1 (fr) 1998-02-11

Family

ID=7760323

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96908022A Ceased EP0823129A1 (fr) 1995-04-25 1996-04-09 Capot de puce

Country Status (9)

Country Link
EP (1) EP0823129A1 (fr)
JP (1) JPH11504164A (fr)
KR (1) KR100407042B1 (fr)
CN (1) CN1135616C (fr)
DE (1) DE19515188C2 (fr)
IN (1) IN188645B (fr)
RU (1) RU2164720C2 (fr)
UA (1) UA57704C2 (fr)
WO (1) WO1996034409A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19841498C2 (de) * 1998-09-10 2002-02-21 Beru Ag Verfahren zum Herstellen eines Elektronikbauelementes, insbesondere eines Hallsensors
DE19957120A1 (de) * 1999-11-26 2001-05-31 Infineon Technologies Ag Vertikal integrierte Schaltungsanordnung und Verfahren zum Betreiben einer vertikal integrierten Schaltungsanordnung
DE10105987A1 (de) 2001-02-09 2002-08-29 Infineon Technologies Ag Datenverarbeitungsvorrichtung
DE10131014C1 (de) * 2001-06-27 2002-09-05 Infineon Technologies Ag Gegen Analyse geschütztes Halbleiterbauelement und zugehöriges Herstellungsverfahren
FR2872610B1 (fr) * 2004-07-02 2007-06-08 Commissariat Energie Atomique Dispositif de securisation de composants
JP5194932B2 (ja) * 2008-03-26 2013-05-08 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725671A (en) * 1970-11-02 1973-04-03 Us Navy Pyrotechnic eradication of microcircuits
DE3602960C1 (de) * 1986-01-31 1987-02-19 Philips Patentverwaltung Dickschicht-Schaltungsanordnung mit einer keramischen Substratplatte
MY107292A (en) * 1989-10-03 1995-10-31 Univ Sydney Technology Electro-active cradle circuits for the detection of access or penetration.
JPH0521655A (ja) * 1990-11-28 1993-01-29 Mitsubishi Electric Corp 半導体装置および半導体装置用パツケージ
US5072331A (en) * 1991-04-26 1991-12-10 Hughes Aircraft Company Secure circuit structure
US5233563A (en) * 1992-01-13 1993-08-03 Ncr Corporation Memory security device
US5389738A (en) * 1992-05-04 1995-02-14 Motorola, Inc. Tamperproof arrangement for an integrated circuit device
US5399441A (en) * 1994-04-12 1995-03-21 Dow Corning Corporation Method of applying opaque coatings

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9634409A1 *

Also Published As

Publication number Publication date
CN1182499A (zh) 1998-05-20
WO1996034409A1 (fr) 1996-10-31
UA57704C2 (uk) 2003-07-15
DE19515188A1 (de) 1996-11-07
JPH11504164A (ja) 1999-04-06
DE19515188C2 (de) 1998-02-19
KR19990008167A (ko) 1999-01-25
KR100407042B1 (ko) 2004-02-18
RU2164720C2 (ru) 2001-03-27
IN188645B (fr) 2002-10-26
CN1135616C (zh) 2004-01-21

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