EP0823129A1 - Chip cover - Google Patents

Chip cover

Info

Publication number
EP0823129A1
EP0823129A1 EP96908022A EP96908022A EP0823129A1 EP 0823129 A1 EP0823129 A1 EP 0823129A1 EP 96908022 A EP96908022 A EP 96908022A EP 96908022 A EP96908022 A EP 96908022A EP 0823129 A1 EP0823129 A1 EP 0823129A1
Authority
EP
European Patent Office
Prior art keywords
chip
activator
cover according
chip cover
cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96908022A
Other languages
German (de)
French (fr)
Inventor
Detlef Houdeau
Josef Kirschbauer
Christl Niederle
Peter Stampka
Hans-Hinnerk Steckhan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0823129A1 publication Critical patent/EP0823129A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
  • Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
  • the chip covers have hitherto been removable, for example by chemical methods (for example using smoking HNO3), so that a precise analysis of the chip circuit and / or manipulations of the chip chips can be carried out in a relatively simple manner. Circuit is possible.
  • the chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip and to find possibilities by manipulating suitable bridges or the like, he can thereby be able to use a fee-based service free of charge.
  • the present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
  • an activator which, when activated, is capable of completely or partially destroying the electrical, electronic, optoelectronic and / or electromechanical components of the chip, and by attempting to remove the chip cover from the chip , can be activated.
  • the figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. It although a section is shown, hatching has been omitted for reasons of clarity.
  • reference number 1 denotes a first chip without a housing in the form of a controller.
  • the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller.
  • the first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
  • the system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead fra e.
  • Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
  • the conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5.
  • This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness.
  • a second chip cover layer in the form of a polyimide layer 6 is provided above the Si3N4 layer 5.
  • the polyimide layer 6 protects the underlying chip structures from mechanical damage.
  • cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
  • ASIC component customer-specific component
  • the second chip 8 is glued to the previously mentioned polyimide layer 6 by means of an adhesive 9.
  • the second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure.
  • the contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
  • the Globe Top 11 is made of epoxy resin.
  • the first to third chip cover layers 5, 6 and 11 and the adhesives 2, 8 generally consist of materials which can be removed chemically.
  • smoking HNO3 is suitable for this, since it destroys the chip cover, but not the conductor tracks 4 and contact points 7 made of aluminum.
  • activators are provided in the chip cover above these areas.
  • the security-relevant area which is to be protected against external analysis and manipulation is the controller chip 1 which is generally located below in the case of chips arranged one above the other. This area should also be the safety-relevant area in the present exemplary embodiment.
  • the activator is a substance that is activated when it meets a substance that chemically dissolves the chip cover in the form of a solvent, an etching agent or the like, that is to say, for example, when it meets smoking HNO3.
  • a substance with a reducing effect is released, which destroys chip structures made of aluminum, such as the conductor tracks 4, and thus makes external analysis and / or manipulation of the security-relevant chip areas impossible.
  • the activator When not activated, the activator does not attack the chip.
  • the activator is formed by RCI2.
  • Free radicals are formed which, owing to their reducing character, destroy the aluminum structures lying under the chip cover.
  • activators which release oxidizing substances when they meet HNO3, does not lead to the desired success here, because oxidizing substances only influence the aluminum structures until they are coated with an oxide layer, which then forms the aluminum structure gives a self-protection function and therefore does not lead to destruction of the aluminum structures.
  • the activators designated by the reference numeral 12 in the figure can be provided above the security-sensitive area in window-like spaces or recesses which are exposed in the Si 3 4 layer 5 and / or in the polyimide layer 6 for this purpose; In the finished state of the chip card, smart card and the like, the activator is encased by the chip cover in these free spaces or recesses.
  • the activator can also be inserted into the polyimide matrix.
  • the position and location of the activator can be adapted to the changing requirements or the respective chips.
  • the type of activator is preferably adapted to the chemical substances that are suitable for dissolving the chip cover, so that the desired activation of the activator reliably occurs when any solvent meets the activator.
  • the effect of the activation can, however, be chosen as long as this only prevents the analysis and / or the manipulation of the chip.
  • it could also be provided, for example, to destroy the chip by generating heat energy or the like.
  • It can also be provided to provide several different activators, each of which reacts with different solvents in the manner intended, so that even the most varied types of solvents activate at least one activator each.
  • a separate substance can be provided in the chip cover in the same way as the activator, which substance is capable of activating the activator as intended.
  • the activator substance can thus be selected independently of the solvents in question, because when the chip cover is removed, both the activator and the substance which is intended to activate it are released.
  • the provision of the activator described above in the chip cover enables the safety-relevant areas of the chip to be destroyed automatically if an attempt is made to make them accessible by removing the chip cover.
  • the amount of activator to be provided is likewise extremely small with appropriate positioning.
  • Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, ie in the present embodiment, the ASIC chip 2 exactly above the security-relevant area of the other chip, ie in the present embodiment exactly above the most security-relevant area of the controller chip 1 is arranged. In the absence of optical accessibility, this also prevents the possibility of being able to analyze and / or manipulate the chip without removing the cover.
  • the exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)

Abstract

The description relates to a chip cover (5, 6, 11) to cover electrical, electronic, opto-electronic and/or electromechanical components of a chip (1, 8) completely or partly. In the chip cover (5, 6, 11), there is an activator (12) which, when activated, is capable of completely or partly destroying the electrical, electronic, opto-electronic and/or electromechanical components of the chip (1, 8) and can be activated by an attempt to remove the cover (5, 6, 11) from the chip (1, 8). It is thus possible reliably to prevent the unauthorised analysis and/or manipulation of the chip (1, 8).

Description

Beschreibungdescription
Chip-AbdeckungChip cover
Die vorliegende Erfindung bezieht sich auf eine Chip- Abdeckung zur vollständigen oder teilweisen Abdeckung von elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten eines Chips.The present invention relates to a chip cover for the complete or partial covering of electrical, electronic, optoelectronic and / or electromechanical components of a chip.
Derartige Chip-Abdeckungen schützen die abgedeckten Bereiche des Chips vor Beschädigungen durch mechanische Gewalt und Umwelteinflüsse.Such chip covers protect the covered areas of the chip from damage caused by mechanical force and environmental influences.
Bei auf Chip Cards, Smart Cards und dergleichen vorgesehenen Chips sind die Chip-Abdeckungen bislang beispielsweise durch chemische Verfahren (z.B. unter Verwendung rauchender HNO3) entfernbar, so daß auf relativ einfache Weise eine genaue Analyse der Chip-Schaltung und/oder Manipulationen der Chip- Schaltung möglich ist.In the case of chips provided on chip cards, smart cards and the like, the chip covers have hitherto been removable, for example by chemical methods (for example using smoking HNO3), so that a precise analysis of the chip circuit and / or manipulations of the chip chips can be carried out in a relatively simple manner. Circuit is possible.
Die Möglichkeit der Durchführung derartiger Analysen und/oder Manipulationen der Chip-Schaltung ist unerwünscht, weil damit die Möglichkeit des Mißbrauchs besteht.The possibility of carrying out such analyzes and / or manipulations of the chip circuit is undesirable because there is a possibility of misuse.
Als Beispiel hierfür seien die auf dem Pay-TV-Sektor zum Ein¬ satz kommenden Chip Cards bzw. Smart Cards genannt. Gelingt es einem Hacker, die den Zugang zu einem bestimmten TV-Pro¬ gramm eröffnende Chip-Schaltung bezüglich der Lage und der Funktion einzelner Komponenten und/oder des Verlaufs der Lei- terbahnen innerhalb des Chips zu analysieren und Möglichkei¬ ten zu finden, diese durch geeignete Oberbrückungen oder der¬ gleichen zu manipulieren, so kann er dadurch in die Lage ver¬ setzt werden, einen kostenpflichtigen Service gratis zu be¬ nutzen.The chip cards or smart cards used in the pay-TV sector may be mentioned as an example of this. If a hacker succeeds in analyzing the chip circuit opening the access to a certain TV program with regard to the position and function of individual components and / or the course of the conductor tracks within the chip and to find possibilities by manipulating suitable bridges or the like, he can thereby be able to use a fee-based service free of charge.
Derartige Manipulationsmöglichkeiten sind nicht nur auf dem Pay-TV-Sektor, sondern bei allen Arten von zu Berechtigungs- kontrollen dienenden Chips von Bedeutung und eröffnen unzäh¬ lige Mißbrauchsmöglichkeiten, welche nicht nur finanzielle Verluste, sondern auch ein erhebliches Sicherheitsrisiko zur Folge haben können.Such manipulation options are not only in the pay TV sector, but in all types of authorization Control serving chips of importance and open up countless possibilities of misuse, which can not only result in financial losses, but also a considerable security risk.
Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, die Chip-Abdeckung gemäß dem Oberbegriff des Patentanspruchs 1 derart weiterzubilden, daß Fremdanalysen und/oder Manipula¬ tionen von Chips zuverlässig verhinderbar sind.The present invention is therefore based on the object of developing the chip cover in accordance with the preamble of claim 1 in such a way that third-party analyzes and / or manipulations of chips can be reliably prevented.
Diese Aufgabe wird erfindungsgemäß durch die im kennzeichnen¬ den Teil des Patentanspruchs 1 beanspruchten Merkmale gelöst.According to the invention, this object is achieved by the features claimed in the characterizing part of patent claim 1.
Demnach ist ein Aktivator vorgesehen, der im aktivierten Zu- stand in der Lage ist, die elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten des Chips ganz oder teilweise zu zerstören, und der durch den Versuch, die Chip-Abdeckung vom Chip zu entfernen, aktivierbar ist.Accordingly, an activator is provided which, when activated, is capable of completely or partially destroying the electrical, electronic, optoelectronic and / or electromechanical components of the chip, and by attempting to remove the chip cover from the chip , can be activated.
Damit ist es möglich, mit der Entfernung der Chip-Abdeckung gleichzeitig eine Zerstörung der sicherheitsrelevanten Berei¬ che des Chips herbeizuführen.It is thus possible, with the removal of the chip cover, to simultaneously destroy the security-relevant areas of the chip.
Fremdanalysen und Manipulationen des Chips sind somit zuver¬ lässig verhinderbar.External analyzes and manipulations of the chip can thus be reliably prevented.
Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche.Advantageous developments of the invention are the subject of the dependent claims.
Die Erfindung wird nachfolgend anhand von Ausführungsbeispie¬ len unter Bezugnahme auf die Figur näher erläutert.The invention is explained in more detail below on the basis of exemplary embodiments with reference to the figure.
Die Figur zeigt zwei übereinandergesetzte Chips, deren sicherheitsrelevante Bereiche durch eine Chip-Abdeckung gemäß einem Ausführungεbeispiel der Erfindung abgedeckt sind. Es ist zwar ein Schnitt dargestellt, jedoch ist aus Gründen der Übersichtlichkeit auf eine Schraffur verzichtet worden.The figure shows two stacked chips, the security-relevant areas of which are covered by a chip cover according to an exemplary embodiment of the invention. It although a section is shown, hatching has been omitted for reasons of clarity.
In der Figur ist mit Bezugszeichen 1 ein erster gehäuseloser Chip in Form eines Controllers bezeichnet. Als Controller ist beispielsweise der Siemens-Baustein SLE 44C20 mit ROM, PROM, EEPROM und RAM einsetzbar.In the figure, reference number 1 denotes a first chip without a housing in the form of a controller. For example, the Siemens SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as a controller.
Der erste Chip 1 ist mittels eines Klebstoffes 2 auf einem Systemträger 3 befestigt.The first chip 1 is attached to a system carrier 3 by means of an adhesive 2.
Der Systemträger 3 kann beispielsweise eine Kunststoffkarte zur Herstellung einer Chip Card oder Smart Card sein; es kann sich aber auch um eine flexible Leiterplatte oder um ein so- genanntes lead fra e handeln.The system carrier 3 can be, for example, a plastic card for producing a chip card or smart card; however, it can also be a flexible printed circuit board or a so-called lead fra e.
An der gemäß der Figur oberen Oberfläche des ersten Chips 1 verlaufen Leiterbahnen 4 aus Aluminium.Conductor tracks 4 made of aluminum run on the upper surface of the first chip 1 according to the figure.
Die Leiterbahnen 4 sind durch eine ersten Chip-Abdeckungs- schicht in Form einer Struktur-Si-Nitrid(Si3N4) -Schicht 5 bedeckt. Diese Schicht 5 dient dazu, den Chip vor Beschädi¬ gungen durch Umgebungseinflüsse, insbesondere vor Beschädi¬ gungen durch Feuchtigkeit und Nässe zu schützen.The conductor tracks 4 are covered by a first chip cover layer in the form of a structured Si nitride (Si3N4) layer 5. This layer 5 serves to protect the chip against damage from environmental influences, in particular against damage from moisture and wetness.
Ober der Si3N4-Schich 5 ist eine zweite Chip-Abdeckungs- schicht in Form einer Polyimid-Schicht 6 vorgesehen. Die Polyimid-Schicht 6 schützt die darunterliegenden Chip-Struk¬ turen vor mechanischen Beschädigungen.A second chip cover layer in the form of a polyimide layer 6 is provided above the Si3N4 layer 5. The polyimide layer 6 protects the underlying chip structures from mechanical damage.
In den genannten Chip-Abdeckungsschichten 5 und 6 sind Aus¬ sparungen vorgesehen, an welchen Kontaktstellen 7 aus Alu¬ minium (Al-Pads) freigelegt sind.In the chip covering layers 5 and 6 mentioned, cutouts are provided at which contact points 7 made of aluminum (Al pads) are exposed.
Ober dem ersten Chip 1 ist ein zweiter gehäuseloser Chip 8 inAbove the first chip 1 there is a second chip 8 in
Form eines ASIC-Bausteins (kundenspezifischer Baustein) vor¬ gesehen. Der zweite Chip 8 ist mittels eines Klebstoffes 9 auf die zuvor bereits erwähnte Polyimid-Schicht 6 aufgeklebt.Form of an ASIC component (customer-specific component) is provided. The second chip 8 is glued to the previously mentioned polyimide layer 6 by means of an adhesive 9.
Der zweite Chip 2 weist an seiner gemäß der Figur oberen Seite ebenfalls Kontaktstellen 7 aus Aluminium auf.The second chip 2 also has contact points 7 made of aluminum on its upper side according to the figure.
Die Kontaktstellen des ersten Chips und die Kontaktstellen des zweiten Chips sind durch Bonddrähte 10 miteinander ver- bunden.The contact points of the first chip and the contact points of the second chip are connected to one another by bonding wires 10.
Die gesamte vorstehend beschriebene Anordnung ist von einer dritten Chip-Abdeckungschicht in Form eines sogenannten Globe Top 11 umgeben, welches dazu dient, die Anordnung vor Umge- bungseinflüssen und mechanischen Beschädigungen zu schützen. Das Globe Top 11 besteht im vorliegenden Fall aus Epoxidharz.The entire arrangement described above is surrounded by a third chip cover layer in the form of a so-called globe top 11, which serves to protect the arrangement from environmental influences and mechanical damage. In the present case, the Globe Top 11 is made of epoxy resin.
Die vorstehend beschriebene, in der Figur gezeigte Anordnung ist Teil einer Chip Card, Smart Card oder dergleichen.The arrangement described above and shown in the figure is part of a chip card, smart card or the like.
Die ersten bis dritten Chip-Abdeckungsschichten 5, 6 und 11 und die Klebstoffe 2, 8 bestehen in der Regel aus Materia¬ lien, die chemisch entfernbar sind. Hierfür eignet sich beispielsweise rauchende HNO3, da diese zwar die Chip- Abdeckung, nicht aber die aus Aluminium bestehenden Leiter¬ bahnen 4 und Kontaktstellen 7 zerstört.The first to third chip cover layers 5, 6 and 11 and the adhesives 2, 8 generally consist of materials which can be removed chemically. For example, smoking HNO3 is suitable for this, since it destroys the chip cover, but not the conductor tracks 4 and contact points 7 made of aluminum.
Um zu verhindern, daß auf diese Weise die Möglichkeit einer Femdanalyse und/oder einer Manipulation von sicherheitsrele- vanten Bereichen der Chips eröffnet wird, sind über diesen Bereichen Aktivatoren in der Chip-Abdeckung vorgesehen.In order to prevent the possibility of external analysis and / or manipulation of security-relevant areas of the chips being opened in this way, activators are provided in the chip cover above these areas.
Der sicherheitsrelevante Bereich, der vor Fremdanalysen und Manipulation zu schützen ist, ist bei Chip Cards, Smart Cards und dergleichen der bei übereinander angeordneten Chips in der Regel unten liegende Controller-Chip 1. Dieser Bereich soll auch im vorliegenden Ausführungsbeispiel der sicher¬ heitsrelevante Bereich sein.In the case of chip cards, smart cards and the like, the security-relevant area which is to be protected against external analysis and manipulation is the controller chip 1 which is generally located below in the case of chips arranged one above the other. This area should also be the safety-relevant area in the present exemplary embodiment.
Der Aktivator ist im vorliegenden Ausführungsbeispiel ein Stoff, der beim Zusammentreffen mit einem die Chip-Abdeckung chemisch auflösenden Stoff in Form eines Lösungsmittels, eines Ätzmittels oder dergleichen, also beispielsweise beim Zusammentreffen mit rauchender HNO3 aktiviert wird. Bei der Aktivierung wird eine Substanz mit reduzierender Wirkung freigesetzt, welche aus Aluminium bestehende Chip-Strukturen wie beispielsweise die Leiterbahnen 4 zerstört und somit eine Fremdanalyse und/oder Manipulation der sicherheitsrelevanten Chip-Bereiche unmöglich macht.In the present exemplary embodiment, the activator is a substance that is activated when it meets a substance that chemically dissolves the chip cover in the form of a solvent, an etching agent or the like, that is to say, for example, when it meets smoking HNO3. Upon activation, a substance with a reducing effect is released, which destroys chip structures made of aluminum, such as the conductor tracks 4, and thus makes external analysis and / or manipulation of the security-relevant chip areas impossible.
Im nicht aktivierten Zustand greift der Aktivator den Chip nicht an.When not activated, the activator does not attack the chip.
Die Zerstörung der Chip-Strukturen nach Aktivierung des Akti¬ vators erfolgt beim vorliegenden Ausführungsbeispiel durch Auflösung derselben mittels chemischer Reduktion.The destruction of the chip structures after activation of the activator takes place in the present exemplary embodiment by dissolving them by means of chemical reduction.
Der Aktivator wird im vorliegenden Ausführungsbeispiel durch RCI2 gebildet. Beim Zusammentreffen mit HNO3 werden nach der ReaktionsgleichungIn the present exemplary embodiment, the activator is formed by RCI2. When encountering HNO3, according to the reaction equation
HNO3 + RCI2 → 2C1" +HNO3 + RCI2 → 2C1 " +
freie Radikale gebildet, die infolge ihres reduzierenden Cha¬ rakters die unter der Chip-Abdeckung liegenden Strukturen aus Aluminium zerstören.Free radicals are formed which, owing to their reducing character, destroy the aluminum structures lying under the chip cover.
Die Verwendung von Aktivatoren, die beim Zusamrrientreffen mit HNO3 oxidierende Substanzen freisetzen, führt hier nicht zu gewünschten Erfolg, denn oxidierende Substanzen bewirken nur so lange eine Beeinflussung der Aluminium-Strukturen bis diese mit einer Oxidschicht überzogen sind, welche der Alu¬ minium-Struktur sodann eine Selbstschutzfunktion verleiht und demnach gerade nicht zu einer Zerstörung der Aluminium-Struk¬ turen führt.The use of activators, which release oxidizing substances when they meet HNO3, does not lead to the desired success here, because oxidizing substances only influence the aluminum structures until they are coated with an oxide layer, which then forms the aluminum structure gives a self-protection function and therefore does not lead to destruction of the aluminum structures.
Die in der Figur mit dem Bezugszeichen 12 bezeichneten Akti- vatoren können über dem sicherheitsempfindlichen Bereich in fensterartigen Freiräumen oder Aussparungen vorgesehen wer¬ den, die in der Si3 4~Schicht 5 und/oder in der Polyimid- Schicht 6 zu diesem Zweck freigelegt sind; im fertiggestell¬ ten Zustand der Chip Card, Smart Card und dergleichen ist der Aktivator in diesen Freiräumen bzw. Aussparungen von der Chip-Abdeckung ummantelt.The activators designated by the reference numeral 12 in the figure can be provided above the security-sensitive area in window-like spaces or recesses which are exposed in the Si 3 4 layer 5 and / or in the polyimide layer 6 for this purpose; In the finished state of the chip card, smart card and the like, the activator is encased by the chip cover in these free spaces or recesses.
Alternativ hierzu kann der Aktivator auch in die Polyimid- atrix eingesetzt werden.Alternatively, the activator can also be inserted into the polyimide matrix.
Es ist nicht erforderlich, daß der Aktivator im nicht akti¬ vierten Zustand bereits mit den gegebenenfalls zu zerstören¬ den Aluininium-Strukturen in Kontakt kommt.It is not necessary for the activator to come into contact with the aluminum structures which may be to be destroyed in the non-activated state.
Lage und Ort des Aktivators können den wechselnden Anfor¬ derungen bzw. den jeweiligen Chips angepaßt werden.The position and location of the activator can be adapted to the changing requirements or the respective chips.
Die Art des Aktivators ist vorzugsweise an die zur Auflösung der Chip-Abdeckung in Frage kommenden chemischen Substanzen angepaßt, so daß beim Zusammentreffen beliebiger Lösungs¬ mittel mit dem Aktivator zuverlässig die gewünschte Aktivie¬ rung des Aktivators eintritt.The type of activator is preferably adapted to the chemical substances that are suitable for dissolving the chip cover, so that the desired activation of the activator reliably occurs when any solvent meets the activator.
Die Wirkung der Aktivierung kann jedoch beliebig gewählt wer- den, solange dadurch nur die Analyse und/oder die Manipula¬ tion des Chips verhinderbar ist. Anstelle der vorstehend er¬ läuterten Zerstörung der Aluminium-Struktur durch chemische Reduktion derselben könnte so beispielsweise auch vorgesehen werden, den Chip durch Erzeugung von Hitzeenergie oder der- gleichen zu zerstören. Es kann auch vorgesehen werden, mehrere verschiedene Aktiva¬ toren vorzusehen, welche jeweils mit verschiedenen Lösungs¬ mitteln in der bestimmungsgemäßen Art reagieren, so daß selbst unterschiedlichste Arten von Lösungsmitteln zumindest jeweils einen Aktivator aktivieren.The effect of the activation can, however, be chosen as long as this only prevents the analysis and / or the manipulation of the chip. Instead of the above-described destruction of the aluminum structure by chemical reduction thereof, it could also be provided, for example, to destroy the chip by generating heat energy or the like. It can also be provided to provide several different activators, each of which reacts with different solvents in the manner intended, so that even the most varied types of solvents activate at least one activator each.
In der Chip-Abdeckung kann neben dem Aktivator getrennt von diesem in der gleichen Weise wie dieser auch eine weitere Substanz vorgesehen werden, welche in der Lage ist, den Akti- vator bestimmungsgemäß zu aktivieren. Damit kann die Aktiva¬ torsubstanz unabhängig von den in Frage kommenden Lösungs¬ mitteln gewählt werden, denn beim Entfernen der Chip- Abdeckung werden sowohl der Aktivator als auch die diesen bestimmungsgemäß aktivierende Substanz freigesetzt.In addition to the activator, a separate substance can be provided in the chip cover in the same way as the activator, which substance is capable of activating the activator as intended. The activator substance can thus be selected independently of the solvents in question, because when the chip cover is removed, both the activator and the substance which is intended to activate it are released.
Die zuletzt genannte Möglichkeit bietet den Vorteil, daß eine Zerstörung der sicherheitsrelevanten Chip-Strukturen auch bei dem Versuch erfolgen kann, diese auf eine nicht chemische Art zugänglich zu machen.The latter possibility offers the advantage that the security-relevant chip structures can also be destroyed when an attempt is made to make them accessible in a non-chemical manner.
Das Vorsehen des vorstehend beschriebenen Aktivators in der Chip-Abdeckung ermöglicht es, daß die sicherheitsrelevanten Bereiche des Chips automatisch zerstört werden, wenn versucht wird, diese durch Entfernen der Chip-Abdeckung zugängig zu machen.The provision of the activator described above in the chip cover enables the safety-relevant areas of the chip to be destroyed automatically if an attempt is made to make them accessible by removing the chip cover.
In Anbetracht der Tatsache, daß die dabei zu zerstörenden Strukturen äußerst kleine Ausmaße haben, ist die vorzusehende Aktivator-Menge bei entsprechender Positionierung ebenfalls äußerst gering.In view of the fact that the structures to be destroyed in the process are extremely small in size, the amount of activator to be provided is likewise extremely small with appropriate positioning.
Eine weitere Maßnahme zur Erhöhung der Sicherheit gegen Fremdanalysen und/oder Manipulationen von Chips besteht darin, daß der weniger sicherheitsrelevante Chip, d.h. im vorliegenden Ausführungsbeispiel der ASIC-Chip 2 genau über dem sicherheitsrelevanten Bereich des anderen Chips, d.h. im vorliegenden Ausführungsbeispiel genau über dem am meisten sicherheitsrelevanten Bereich des Controller-Chips 1 ange¬ ordnet wird. Mangels optischer Zugänglichkeit wird damit auch die Möglichkeit unterbunden, den Chip ohne Entfernen der Abdeckung analysieren und/oder manipulieren zu können.Another measure to increase security against third-party analysis and / or manipulation of chips is that the less security-relevant chip, ie in the present embodiment, the ASIC chip 2 exactly above the security-relevant area of the other chip, ie in the present embodiment exactly above the most security-relevant area of the controller chip 1 is arranged. In the absence of optical accessibility, this also prevents the possibility of being able to analyze and / or manipulate the chip without removing the cover.
Das vorstehend beschriebene Ausführungsbeispiel betraf einen sogenannten chip-on-chip-on-flex-Aufbau mit einer chip-and- wire-Verbindungstechnologie. Es versteht sich von selbst, daß die Erfindung nicht auf einen derartigen Aufbau beschränkt ist, sondern auch bei Einzel-Chips und bei jeder beliebigen Anzahl von beliebig angeordneten und beliebig miteinander verbundenen Chips zum Einsatz kommen kann.The exemplary embodiment described above concerned a so-called chip-on-chip-on-flex structure with chip-and-wire connection technology. It goes without saying that the invention is not limited to such a structure, but can also be used with individual chips and with any number of arbitrarily arranged and arbitrarily connected chips.
Ferner besteht auch keine Einschränkung auf die gemäß der vorstehenden Beschreibung verwendeten Materialien. Diese können durch beliebige andere Materialien ersetzt werden, so lange diese nur den ihnen zugedachten Zweck erfüllen.Furthermore, there is also no restriction to the materials used as described above. These can be replaced by any other materials, as long as they only serve the intended purpose.
Durch die beschriebene erfindungsgemäße Ausbildung der Chip- Abdeckung ist es weitgehend unabhängig von der Ausbildung der Anordnung auf einfache Weise möglich, Fremdanalysen und Mani¬ pulationen des Chips zuverlässig zu verhindern. Due to the described design of the chip cover according to the invention, it is largely possible, independently of the design of the arrangement, to reliably prevent external analyzes and manipulations of the chip.

Claims

Patentansprüche claims
1. Chip-Abdeckung zur vollständigen oder teilweisen Ab¬ deckung von elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten eines Chips, d a d u r c h g e k e n n z e i c h n e t, daß ein Aktivator vorgesehen ist, der im aktivierten Zustand in der Lage ist, die elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten des Chips ganz oder teilweise zu zerstören, und der durch den Versuch, die Chip-Abdeckung vom Chip zu entfernen, aktivierbar ist.1. Chip cover for complete or partial coverage of electrical, electronic, optoelectronic and / or electromechanical components of a chip, characterized in that an activator is provided which is capable of the electrical, electronic, optoelectronic and in the activated state / or to destroy all or part of the electromechanical components of the chip, and which can be activated by trying to remove the chip cover from the chip.
2. Chip-Abdeckung nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, daß durch die Abdeckung ein auf einer Chip Card oder einer Smart Card vorgesehener gehäuseloser Chip abdeckbar ist.2. Chip cover according to claim 1, so that a housing-less chip provided on a chip card or a smart card can be covered by the cover.
3. Chip-Abdeckung nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t, daß der Chip ein Controller- oder ein ASIC-Baustein ist.3. Chip cover according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the chip is a controller or an ASIC chip.
4. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß der Aktivator in einer in der Chip-Abdeckung vorgesehenen Aussparung vorgesehen is .4. Chip cover according to one of the preceding claims, that the activator is provided in a recess provided in the chip cover.
5. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e , daß der Aktivator in die Abdeckungsmaterial-Matrix eingebun¬ den ist.5. Chip cover according to one of the preceding claims, that the activator is integrated into the cover material matrix.
6. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß bei der Aktivierung des Aktivators eine Substanz mit re¬ duzierender Wirkung freigesetzt wird. 6. Chip cover according to one of the preceding claims, characterized in that a substance with re¬ reducing effect is released when the activator is activated.
7. Chip -Abdeckung nach Anspruch 6, d a d u r c h g e k e n n z e i c h n e t, daß die elektrischen, elektronischen, optoelektronischen und/oder mechanischen Komponenten des Chips durch die Sub- stanz mit reduzierender Wirkung zerstört werden.7. Chip cover according to claim 6, so that the electrical, electronic, optoelectronic and / or mechanical components of the chip are destroyed by the substance with a reducing effect.
8. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die elektrischen, elektronischen, optoelektronischen und/oder elektromechanischen Komponenten des Chips Aluminium- Strukturen sind.8. Chip cover according to one of the preceding claims, that the electrical, electronic, optoelectronic and / or electromechanical components of the chip are aluminum structures.
9. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß der Aktivator RCI2 ist.9. Chip cover according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the activator is RCI2.
10. Chip -Abdeckung nach Anspruch 9, d a d u r c h g e k e n n z e i c h n e , daß beim Aktivieren von RCI2 ein freies Radikal gebildet wird.10. Chip cover according to claim 9, that a free radical is formed when activating RCI2.
11. Chip -Abdeckung nach Anspruch 10, d a d u r c h g e k e n n z e i c h n e t, daß das freie Radikal die Substanz mit reduzierender Wirkung ist.11. Chip cover according to claim 10, that the free radical is the substance with a reducing effect.
12. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Aktivierung des Aktivators durch ein die Chip- Abdeckung auflösendes Lösungsmittel erfolgt.12. Chip cover according to one of the preceding claims, that the activation of the activator is carried out by a solvent dissolving the chip cover.
13. Chip-Abdeckung nach einem der Ansprüche 1 bis 11, d a d u r c h g e k e n n z e i c h n e t, daß die Aktivierung des Aktivators durch ein innerhalb der Chip-Abdeckung gespeichertes Aktivierungsmittel erfolgt.13. Chip cover according to one of claims 1 to 11, so that the activation of the activator is carried out by an activation means stored within the chip cover.
14. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e , daß über einem εicherheitsrelevanten Bereich des Chips ein zweiter Chip angeordnet ist.14. Chip cover according to one of the preceding claims, characterized in that a second chip is arranged over a safety-relevant area of the chip.
15. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß der Aktivator in der Chip-Abdeckung über dem sicherheits- relevanten Bereich des Chips vorgesehen ist.15. Chip cover according to one of the preceding claims, that the activator is provided in the chip cover over the safety-relevant area of the chip.
16. Chip-Abdeckung nach einem der vorhergehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, daß die Chip-Abdeckung aus mehreren Schichten aufgebaut ist. 16. Chip cover according to one of the preceding claims, that the chip cover is made up of several layers.
EP96908022A 1995-04-25 1996-04-09 Chip cover Ceased EP0823129A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19515188 1995-04-25
DE19515188A DE19515188C2 (en) 1995-04-25 1995-04-25 Chip cover
PCT/DE1996/000616 WO1996034409A1 (en) 1995-04-25 1996-04-09 Chip cover

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EP0823129A1 true EP0823129A1 (en) 1998-02-11

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KR (1) KR100407042B1 (en)
CN (1) CN1135616C (en)
DE (1) DE19515188C2 (en)
IN (1) IN188645B (en)
RU (1) RU2164720C2 (en)
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DE19841498C2 (en) 1998-09-10 2002-02-21 Beru Ag Method for producing an electronic component, in particular a Hall sensor
DE19957120A1 (en) * 1999-11-26 2001-05-31 Infineon Technologies Ag Vertical structure integrated circuit arrangement
DE10105987A1 (en) 2001-02-09 2002-08-29 Infineon Technologies Ag Data processing device
DE10131014C1 (en) * 2001-06-27 2002-09-05 Infineon Technologies Ag Semiconductor element used in a chip card in the pay-per-view television sector comprises a chip, and a device for deactivating the chip consisting of a hollow chamber containing an activator
FR2872610B1 (en) * 2004-07-02 2007-06-08 Commissariat Energie Atomique DEVICE FOR SECURING COMPONENTS
JP5194932B2 (en) * 2008-03-26 2013-05-08 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of semiconductor device

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WO1996034409A1 (en) 1996-10-31
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JPH11504164A (en) 1999-04-06
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