CN1135616C - Chip cover - Google Patents

Chip cover Download PDF

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Publication number
CN1135616C
CN1135616C CNB961934808A CN96193480A CN1135616C CN 1135616 C CN1135616 C CN 1135616C CN B961934808 A CNB961934808 A CN B961934808A CN 96193480 A CN96193480 A CN 96193480A CN 1135616 C CN1135616 C CN 1135616C
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CN
China
Prior art keywords
chip
activator
chip cover
cover
cover according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB961934808A
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Chinese (zh)
Other versions
CN1182499A (en
Inventor
D�����°�
D·霍德奥
J·基尔施鲍尔
C·尼德列
��������˹�����տ�����
P·斯坦普卡
H-H·施特克汉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of CN1182499A publication Critical patent/CN1182499A/en
Application granted granted Critical
Publication of CN1135616C publication Critical patent/CN1135616C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention relates to a chip cover for complete or partial covering of electrical, electronic, optoelectronic and/or electromechanical components,which includes an activator capable of fully or partially destroying the electrical, electronic, optoelectronic and/or electromechanical components of the chip when activated. The activator can be activated by an attempt to remove the chip cover from the chip. In this way It is thus possible reliably to prevent the unauthorised analysis and/or manipulation of the chip.

Description

Chip cover
The invention relates to a chip cover for an electrical, electronic, optoelectronic and/or electromechanical component which covers the chip in whole or in part.
Such a chip cover prevents the covered area of the chip from being damaged due to mechanical forces or environmental conditions.
Chip covers for mounting chips on chip cards, smart cards (smart cards) and the like have hitherto been removable, for example by chemical means (e.g. by fuming nitric acid treatment), so that the chip circuitry can be accurately analysed and/or the chip circuitry can be manipulated in a relatively simple manner.
The possibility of performing such analysis and/or manipulation of the chip circuitry is undesirable because of the potential for abuse.
For example, the pay television field is about to use a chip or a smart card. If a user successfully analyses the chip circuits which allow the reception of a certain specific television program, i.e. the function and position of the various components and/or the interconnecting lines within the chip, and obtains a change in their performance by means of suitable jumpers or similar, it is thus possible to use the services for free.
These operating possibilities are not limited to the field of pay television but can be used for all kinds of chips for access control of legal rights and open up countless possible abuse opportunities, which not only lead to economic losses but also may lead to considerable security consequences.
The object of the invention is to further develop a chip cover which reliably prevents an unauthorized analysis and/or manipulation of the chip.
To this end, according to the invention, a chip cover for an electrical, electronic and/or electromechanical component which covers the chip in whole or in part is provided, characterized in that an activator is provided which, when activated by a solvent, releases a substance with a reducing action which is capable of decomposing the chip cover or which remains in the chip cover in an attempt to remove the chip cover from the chip.
When the activator is in an activated state, the electrical, electronic, optoelectronic and/or electromechanical components of each chip are totally or partially eliminated, which can be activated when an attempt is made to remove its cover from the chip.
Here, it is possible that: this results in destruction of the security-relevant areas of the chip while the chip cover is removed.
This makes it possible to reliably prevent improper analysis and operation of the chip.
Advantageous refinements of the invention are found in the dependent claims.
The invention is described below in embodiments with the aid of the drawings.
The figure shows two chips stacked on top of each other, the security relevant area of which is covered by a chip cover according to an embodiment of the invention. Although a cross-sectional view is provided, shading is omitted for clarity of presentation.
In the figure, reference numeral 1 denotes a first unpackaged chip as a controller. For example, the Siemens component SLE 44C20 with ROM, PROM, EEPROM and RAM may be used as a controller.
The first chip 1 is fixed to a system carrier 3 by means of an adhesive 2.
The system carrier 3 can be, for example, a plastic card which is used to form a chip card or smart card, or it can be a flexible printed circuit board or a so-called lead frame.
The wires 4 of aluminum are distributed over the upper surface of the first chip 1 according to the drawing.
Each of the wires 4 is made of a material in the form of silicon nitride (Si)3N4) The first chip cover layer of the structured thin layer 5. This thin layer 5 is intended to protect the chip from damage due to external influences, in particular moisture and humidity.
Si3N4On top of the layer 5 is a second chip cover layer in the form of a thin polyimide layer 6, the polyimide layer 6 protecting the underlying chip structures from mechanical damage.
In the chip coverlayers 5 and 6, recesses are provided, in which aluminum contact points 7 (aluminum lands) are distributed.
Above the first chip 1 is a second unpackaged chip 8 in the form of an ASIC module (user specific module).
The second chip 8 is bonded to the polyimide film 6 by an adhesive 9.
The second chip 8 likewise has aluminium contact points 7, which are on its upper side according to the drawing.
The contact points of the first chip and the contact points of the second chip are connected to each other by bonding wires 10.
The entire assembly is surrounded by a third chip cover 11 in the form of a Globe top (Globe top) which is intended to protect the assembly from external influences and mechanical damage. In the above range, the third chip cover 11 of the dome is epoxy resin.
As mentioned above, the combination device shown in the figure is part of a chip card or smart card or similar.
The first through third chip covers 5, 6 and 11 and the adhesive 2 are generally composed of a chemically removable material. Fuming nitric acid, for example, is suitable for this purpose, and although it destroys the chip cover, it does not destroy the leads 4 and the contacts 7 made of aluminum.
In order to prevent in this way possible improper analyses and/or manipulations in the areas of the chip concerned with the security protection, in these areas, a quantity of an initiator is provided within the cover of the chip.
The security-relevant area to be protected against unauthorized analysis and manipulation is here, in chip cards, smart cards and the like, the underlying controller chip 1, the chips of which are superposed on one another. This area should also be a safety-relevant area in this embodiment.
In this embodiment, the activator is a material that is activated upon encountering a chemically soluble material of the chip lid in the form of a solvent, etchant, or the like, for example, fuming nitric acid. On activation, a reducing substance is released which destroys the aluminum chip structures, such as the wires 4, thereby making it impossible to perform any improper analysis and/or manipulation of the chip area in connection with the security protection.
In the non-activated state, the activator does not attack the chip.
In this embodiment, after the starter is started, the chip structure is destroyed, wherein the dissolution of the structure is due to chemical reduction.
In this embodiment, the initiator is RCl2And (4) forming. Encounter HNO3When, the free radical is generated by the following reaction formula:
. Due to their reducing nature, these radicals destroy the aluminum structures under the chip lid.
Use ofEncounter HNO3The desired result cannot be achieved here with starters which release substances which act in an oxidizing manner, since the substances which act in an oxidizing manner have a period of time which is only so long that an oxide layer forms on the surface of the aluminum structures. This oxide layer gives a self-protection to the aluminum structure itself, so that the aluminum structure is not damaged.
The initiator, which is denoted by reference numeral 12 in the figure, can be provided in the form of windowed slots or pits on the security-sensitive area, which are distributed for this purpose in Si3N4The layer 5 and/or the polyimide layer 6 enclose the activator in these gaps or recesses by the chip cover after the chip card,the smart card and the like have been mounted.
Another approach is to: the initiator is disposed in a polyimide carrier.
It is not necessary to bring the initiator in its non-priming state into contact with the aluminum structure to be destroyed if necessary.
The arrangement of the initiator can be determined according to various requirements or according to the individual chips.
The type of activator is preferably compatible with the chemicals used to dissolve the chip cover so that the activator can be reliably activated as desired when any solvent encounters the activator.
The manner of activation can be chosen in a variety of ways as long as analysis and/or manipulation of the individual chips can be prevented. For example, instead of destroying the aluminum structure by chemical reduction as described above, the chip may be destroyed by heat generation or the like.
It is also possible to use a plurality of different starters, reacting with different solvents according to the requirements specified, so that a single starter can be started at least at a time by a plurality of different solvents.
In the chip cover, another substance can be used to activate the activator as needed in the same manner. Therefore, the activator substance can be selected independently of the solvent used, and the activator is released as well as the desired activator substance when the chip cover is removed.
The last mentioned possibility has the advantageous benefit of: even if access to the security-relevant chip structure is attempted by a non-chemical means, the structure may be destroyed.
The above-mentioned initiator, which is arranged in the chip cover, makes it possible to automatically destroy the security-relevant areas of the chip when an attempt is made to remove the chip cover.
In view of the very small dimensions of the structure to be destroyed, the amount of activator provided is likewise very small at the corresponding location.
Another measure for increasing the security against unauthorized analysis and/or manipulation of the chip consists in arranging the chip with the lower security relevance, i.e. in the exemplary embodiment the ASIC chip 8, to be placed exactly above the security-relevant region of the other chips, i.e. in the exemplary embodiment exactly above the region of the controller chip 1 which is most security-relevant. Thus, without optical access means, the chip can be analyzed and/or manipulated without removing the cover, which would also be impossible.
The above embodiments relate to a so-called chip-on-chip architecture (chip-on-chip-on-flex-Aufbau) and use a chip-and-wire combination process (chip-and-wire-Verbindungstenchologie). It is evident that: the invention is not limited to such a structure and may be applied to individual chips, to any number of chips arbitrarily arranged joined together in any desired manner.
In addition, there is no limitation on various materials used according to the above description. These materials may be replaced with any other desired materials as long as the desired function is achieved.
By the design of the chip cover according to the invention described above, a misanalysis and/or manipulation of the chip can be easily and reliably avoided, which is largely independent of the design of the device.

Claims (13)

1. A chip cover for an electrical, electronic and/or electromechanical component which covers the chip in whole or in part, characterized in that an activator is provided which, when activated by a solvent, releases a substance with a reducing action which can decompose the chip cover or which is retained in the chip cover, the activator being activated when the chip cover is removed from the chip.
2. The chip cover according to claim 1, characterized in that an unpackaged chip on a chip card or a smart card can be covered by the cover.
3. Chip cover according to claim 1 or 2, characterized in that the chip is a control module or an ASIC module.
4. The chip cover according to claim 1 or 2, wherein the activator is provided in a void provided in the chip cover.
5. The chip cover according to claim 1 or 2, characterized in that the activator is integrated in the cover material carrier.
6. Chip cover according to claim 1, characterized in that the electrical, electronic, optoelectronic and/or electromechanical components of the chip are destroyed by the reducing substance.
7. Chip cover according to claim 1 or 2, characterized in that the electrical, electronic, optoelectronic and/or electromechanical components of the chip are aluminum structures.
8. Chip cover according to claim 1 or 2, characterized in that the activator is RCl2。
9. The chip cover of claim 8, wherein when RCl is applied2When activated, a free radical is formed.
10. The chip cover according to claim 9, wherein the radical is a reducing substance.
11. The chip cover according to claim 1 or 2, wherein the activator is activated by a solvent which dissolves the chip cover.
12. The chip cover according to claim 1 or 2, wherein the activator is activated by an activator material stored within the chip cover.
13. Chip cover according to claim 1 or 2, characterized in that a second chip is mounted above the chip security relevant area.
CNB961934808A 1995-04-25 1996-04-09 Chip cover Expired - Lifetime CN1135616C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19515188A DE19515188C2 (en) 1995-04-25 1995-04-25 Chip cover
DE19515188.7 1995-04-25

Publications (2)

Publication Number Publication Date
CN1182499A CN1182499A (en) 1998-05-20
CN1135616C true CN1135616C (en) 2004-01-21

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EP (1) EP0823129A1 (en)
JP (1) JPH11504164A (en)
KR (1) KR100407042B1 (en)
CN (1) CN1135616C (en)
DE (1) DE19515188C2 (en)
IN (1) IN188645B (en)
RU (1) RU2164720C2 (en)
UA (1) UA57704C2 (en)
WO (1) WO1996034409A1 (en)

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DE10105987A1 (en) 2001-02-09 2002-08-29 Infineon Technologies Ag Data processing device
DE10131014C1 (en) * 2001-06-27 2002-09-05 Infineon Technologies Ag Semiconductor element used in a chip card in the pay-per-view television sector comprises a chip, and a device for deactivating the chip consisting of a hollow chamber containing an activator
FR2872610B1 (en) * 2004-07-02 2007-06-08 Commissariat Energie Atomique DEVICE FOR SECURING COMPONENTS
JP5194932B2 (en) * 2008-03-26 2013-05-08 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of semiconductor device

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Also Published As

Publication number Publication date
WO1996034409A1 (en) 1996-10-31
IN188645B (en) 2002-10-26
DE19515188A1 (en) 1996-11-07
UA57704C2 (en) 2003-07-15
KR100407042B1 (en) 2004-02-18
JPH11504164A (en) 1999-04-06
CN1182499A (en) 1998-05-20
EP0823129A1 (en) 1998-02-11
KR19990008167A (en) 1999-01-25
DE19515188C2 (en) 1998-02-19
RU2164720C2 (en) 2001-03-27

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