KR19990008167A - Chip cover - Google Patents

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Publication number
KR19990008167A
KR19990008167A KR1019970707692A KR19970707692A KR19990008167A KR 19990008167 A KR19990008167 A KR 19990008167A KR 1019970707692 A KR1019970707692 A KR 1019970707692A KR 19970707692 A KR19970707692 A KR 19970707692A KR 19990008167 A KR19990008167 A KR 19990008167A
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South Korea
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chip
cover
chip cover
activator
activated
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KR1019970707692A
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Korean (ko)
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KR100407042B1 (en
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데틀레프 후도이
요제프 키르쉬바우어
크리스틀 니델레
페터 슈탐프카
한스-힌네르크 슈테칸
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로더리히네테부쉬
지멘스악티엔게젤샤프트
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)

Abstract

전기, 전자, 광전자 또는 전기 기계 칩 부품을 전체 또는 부분적으로 커버링하기 위한 칩 커버가 개시된다. 상기 칩 커버는, 활성화된 상태에서 전기, 전자, 광전자 또는 전기 기계 칩 부품을 전체 또는 부분적으로 파괴할 수 있고, 상기 칩에서 상기 칩 커버를 제거하려는 시도에 의해 활성화될 수 있는 활성체가 제공된다는 점에서 구별된다. 이러한 방법으로, 칩에 대한 역 처리 또는 조작이 신뢰성 있게 방지되는 것이 가능해진다.A chip cover is disclosed for totally or partially covering an electrical, electronic, optoelectronic or electromechanical chip component. The chip cover is provided with an activator which, in the activated state, can destroy the electrical, electronic, optoelectronic or electromechanical chip components in whole or in part and which can be activated by an attempt to remove the chip cover from the chip. Is distinguished from. In this way, reverse processing or manipulation to the chip can be reliably prevented.

Description

칩 커버Chip cover

이러한 타입의 칩 커버는 칩의 커버링된 영역을 기계적 힘 및 주변 조건으로 인한 손상으로부터 보호한다.This type of chip cover protects the covered area of the chip from damage due to mechanical forces and ambient conditions.

스마트 카드 등과 같은 칩 카드상에 제공된 칩에 있어서, 지금까지 칩 커버는 예를 들어 화학적 방법(예를 들면, HNO3을 사용하여)에 의해 제거 가능하기 때문에 정확한 칩 회로 분석 및 칩 회로의 조작은 비교적 쉽게 수행될 수 있다.In chips provided on a chip card such as a smart card, so far, the chip cover can be removed by, for example, chemical methods (for example, using HNO 3 ), so that accurate chip circuit analysis and manipulation of the chip circuit are performed. It can be done relatively easily.

이러한 것은 오용의 가능성을 유발하기 때문에, 이러한 분석 또는 칩 회로의 조작을 수행하는 가능성은 바람직하지 않다.Since this causes the possibility of misuse, the possibility of performing such an analysis or manipulation of the chip circuit is undesirable.

이러한 예로서, 유료의 텔레비젼 섹터에서 사용할 수 있는 칩 카드 또는 스마트 카드가 언급될 수 있다. 헤커가 특별한 텔레비젼 채널로 액세스할 수 있는 칩 회로를 회로 내의 개별적인 소자의 위치 및 기능 또는 상호 연결에 관하여 분석하는 데 성공하고 적합한 점퍼링 등에 의해 그들을 조작할 수 있는 능력을 쌓는 데 성공하였다면, 이에 따라 그는 무료의 서비스에 대한 사용할 수 있게 된다.As such an example, a chip card or a smart card that can be used in the pay television sector may be mentioned. If Hecker succeeded in analyzing the chip circuits accessible by a particular television channel with respect to the location and function or interconnection of the individual elements in the circuit, and gained the ability to manipulate them by suitable jumpers, etc. He will be available for a free service.

조작의 이같은 가능성은 유료의 텔레비젼 섹터뿐만 아니라 액세스 제어를 위하여 사용되는 칩의 모든 타입에 있어서도 중요하며, 오용에 대한 무한한 가능성을 개방하게 되며, 이것은 금전적인 손실뿐만 아니라 고려할 만한 기밀 보호 위험을 유발시킨다.This possibility of manipulation is important not only for the paying television sector, but also for all types of chips used for access control, which opens up unlimited possibilities for misuse, which creates not only financial losses but also considerable confidentiality risks. .

본 발명은 전기, 전자, 광전자 또는 전기 기계 칩 부품을 전체 또는 부분적으로 보호하기 위한 칩 커버에 관한 것이다.The present invention relates to chip covers for total or partial protection of electrical, electronic, optoelectronic or electromechanical chip components.

도 1은 하나의 칩 위에 다른 칩이 설비된 두 개의 칩을 도시한다.1 shows two chips with one chip on another.

따라서 본 발명의 목적은 칩의 역 처리 또는 조작이 신뢰성 있게 방지될 수 있는 방식으로 청구항 1의 전제부에 따르는 칩 커버를 제공하는 것이다.It is therefore an object of the present invention to provide a chip cover according to the preamble of claim 1 in such a way that reverse processing or manipulation of the chip can be reliably prevented.

상기 목적은 본 발명에 따라 청구항 1의 전제부에서 청구된 특징에 의해 달성된다.This object is achieved in accordance with the invention as claimed in the preamble of claim 1.

이에 따라, 활성화된 상태에서, 전기, 전자, 광전자 또는 전기 기계 칩 부품을 전적 또는 부분적으로 파괴할 수 있고, 칩으로부터 칩 커버를 제거하려는 시도에 의해 활성화 될 수 있는 활성체가 제공된다.Thus, in the activated state, an activator is provided which can destroy the electrical, electronic, optoelectronic or electromechanical chip components in whole or in part and which can be activated by attempting to remove the chip cover from the chip.

이에 따라, 칩 커버의 제거와 동시에 기밀 보호와 관련된 칩 영역의 파괴가 발생할 가능성이 있게 된다.As a result, there is a possibility that destruction of the chip area associated with the airtight protection occurs at the same time as the chip cover is removed.

칩의 역 처리 및 조작은 신뢰성 있게 방지될 수 있다.Reverse processing and manipulation of the chip can be reliably prevented.

본 발명에 관한 유용한 개선은 종속항의 주요 문제를 구성한다.Useful refinements concerning the invention constitute the main problem of the dependent claims.

본 발명은 도면을 참조한 상세한 실시예를 사용하여 보다 상세하게 설명된다.The invention is explained in more detail using the detailed embodiments with reference to the drawings.

도 1은 하나의 칩 위에 다른 칩이 설비된 두 개의 칩을 도시하며, 칩의 기밀 보호와 관련된 영역은 본 발명에 관한 실질적인 실시예에 따른 칩 커버에 의해 커버링된다. 구획이 표시되었을 지라도, 음영은 깨끗함을 목적으로 하여 제거된다.Fig. 1 shows two chips with one chip on top of another, with the area associated with the tight protection of the chip covered by a chip cover according to a practical embodiment of the invention. Although the compartment is marked, the shading is removed for the purpose of cleanliness.

도 1에서, 부호 1은 제어기의 형태로 케이싱 되지 않은 제 1 칩을 나타낸다. 예로서, ROM, PROM, EEPROM 및 RAM을 갖는 지멘스 모듈 SLE 44C20은 제어기로서 사용될 수 있다.In Fig. 1, reference numeral 1 denotes a first chip which is not cased in the form of a controller. As an example, the Siemens module SLE 44C20 with ROM, PROM, EEPROM and RAM can be used as the controller.

제 1 칩은 접착층(2)에 의해 시스템 지지체(3) 상에 고착된다.The first chip is fixed on the system support 3 by the adhesive layer 2.

상기 시스템 지지체(3)는 예를 들어 칩 카드 또는 스마트 카드를 생산하기 위한 플라스틱 카드일 수 있고, 또한 융통성 있는 PCB(Printed Circuit Board) 또는 소위 리드 프레임일 수도 있다.The system support 3 may be a plastic card for producing a chip card or a smart card, for example, and may also be a flexible printed circuit board (PCB) or so-called lead frame.

알루미늄의 상호 접속(4)은 도면상의 제 1 칩의 상부 표면인 표면 상측에 뻗어 있다.The interconnection 4 of aluminum extends above the surface, which is the upper surface of the first chip on the drawing.

상호 접속(4)은 실리콘 나이트라이드(Si3N4) 층(5)으로 구성된 형태로 제 1 칩 커버 층에 의해 커버링된다. 이러한 층(5)의 목적은 주변 조건으로 인한 손상 특히 습기 및 수분으로 인한 손상으로부터 칩을 보호하는 것이다.The interconnect 4 is covered by a first chip cover layer in the form of a silicon nitride (Si 3 N 4 ) layer 5. The purpose of this layer 5 is to protect the chip from damage caused by ambient conditions, in particular moisture and moisture.

Si3N4층(5)의 상부에 제 2 칩 커버 층이 폴리이미드 층(6)의 형태로 제공된다. 상기 폴리이미드 층(6)은 아래에 놓인 칩 구조를 기계적인 손상으로부터 보호한다.On top of the Si 3 N 4 layer 5 a second chip cover layer is provided in the form of a polyimide layer 6. The polyimide layer 6 protects the underlying chip structure from mechanical damage.

노출된 알루미늄 접촉 점(7)(Al 패드)이 위치한 오목부가 상기 칩 커버 층(5 및 6) 상에 제공된다.A recess in which the exposed aluminum contact point 7 (Al pad) is located is provided on the chip cover layers 5 and 6.

제 1 칩 상측에, 제 2의 케이싱되지 않은 칩(8)이 ASIC (Application specific Integrated Circuit) 모듈의 형태로 제공된다.On top of the first chip, a second uncased chip 8 is provided in the form of an Application Specific Integrated Circuit (ASIC) module.

상기 제 2 칩(8)은 이미 상술한 폴리이미드 층(6) 상의 접착층(9)에 의해 본딩된다.The second chip 8 is bonded by an adhesive layer 9 on the polyimide layer 6 described above.

유사하게 상기 제 2 칩은 도면의 상측 측부에 위치한 칩의 측부상에 있는 알루미늄 접촉 점(7)을 포함한다.Similarly the second chip comprises an aluminum contact point 7 on the side of the chip located on the upper side of the figure.

상기 제 1 칩의 접촉점과 제 2 칩의 접촉점은 서로 본딩 와이어(10)에 의해 연결된다.The contact point of the first chip and the contact point of the second chip are connected to each other by a bonding wire 10.

상술한 전체 장치는 제 3 칩 커버 층으로 소위 글로브 탑(11) 형태로 둘러싸이며, 상기 층의 목적은 주변 조건과 기계적 손상으로부터 장치를 보호하기 위한 것이다. 제시된 경우에 있어서, 글로브 탑(11)은 에폭시 레진으로 구성된다.The entire device described above is enclosed in the form of a so-called glove top 11 with a third chip cover layer, the purpose of which is to protect the device from ambient conditions and mechanical damage. In the case presented, the glove top 11 is composed of epoxy resin.

상술되고 도 1에 도시된 상기 장치는 스마트 카드 등과 같은 칩 카드의 일부이다.The device described above and shown in FIG. 1 is part of a chip card, such as a smart card.

일반적으로, 제 1 내지 제 3의 칩 커버 층(5,6 및 11)과 접착층(2, 8)은 화학적으로 제거될 수 있는 물질로 구성된다. 예를 들어 발연 HNO3이 이것에 적합하며, 이것은 그것이 칩 커버를 손상시키더라도, 그것은 알루미늄으로 구성된 상호 접속(4)과 접촉 점(7)을 파괴하지 않기 때문이다.In general, the first to third chip cover layers 5, 6 and 11 and the adhesive layers 2, 8 are composed of a material that can be chemically removed. For example, fuming HNO 3 is suitable for this, because even if it damages the chip cover, it does not destroy the interconnection points 4 and the contacts 7 made of aluminum.

칩의 기밀과 관련된 영역에 대한 역 처리 또는 조작의 가능성을 제공하는 것으로부터 이러한 것을 보호하기 위하여, 칩 커버 내의 활성체는 이러한 영역의 상부에 제공된다.In order to protect this from providing the possibility of reverse processing or manipulation of the area associated with the airtightness of the chip, an activator in the chip cover is provided on top of this area.

스마트 카드와 같은 칩 카드의 경우, 하나의 상부에 다른 하나가 배열된 칩을 사용하여 역 처리 또는 조작으로부터 보호된 안정성과 관련된 영역은 일반적으로 아래에 놓은 제어기 칩(1)이다. 또한 이러한 영역은 제시된 실질적인 실시예의 안정도와 관련된 영역일 수도 있다.In the case of a chip card such as a smart card, the area related to stability protected from reverse processing or manipulation by using chips arranged one on top of the other is generally the controller chip 1 laid down. Such areas may also be areas related to the stability of the presented practical embodiments.

제시된 실시예에서, 활성체는 화학적으로 칩 커버를 용해시키는 에천트 등과 같은 용매 형태의 물질과 접하게 될 때, 즉 예를 들어 발연 HNO3과 접할 때 활성화되는 물질이다. 활성화시, 환원 작용을 가지는 물질이 방출되며, 상기 물질은 예를 들어 상호 접속(4)과 같은 알루미늄으로 구성된 이러한 칩 구조를 파괴시키고, 그에 의해 기밀 보호와 관련된 영역에 대한 역 처리 또는 조작을 불가능하게 한다.In the examples shown, the activator is a substance that is activated when it comes into contact with a solvent form material such as etchant which chemically dissolves the chip cover, ie when it comes into contact with fuming HNO 3 , for example. Upon activation, a substance with a reducing action is released, which destroys such a chip structure made of aluminum, for example interconnect 4, thereby making it impossible to reverse process or manipulate the area associated with hermetic protection. Let's do it.

비활성화된 상태에서, 활성체는 칩을 손상시키지 않는다.In the deactivated state, the activator does not damage the chip.

제시된 실질적인 실시예서, 활성체의 활성화 이후에 칩 구조의 파괴는 화학적 환원에 의해 이러한 구조물을 용해시킴으로써 발생한다.In the practical example shown, the breakdown of the chip structure after activation of the activator occurs by dissolving this structure by chemical reduction.

제시된 실질적인 실시예에서, 활성체는 RCl2로 형성된다. HNO3과 접할 때, 아래의 반응식에 따라 자유기가 형성되며, 그들의 성질을 환원시키는 결과로서, 이러한 자유기는 칩 커버 아래에 위치한 알루미늄 구조물을 파괴한다.In the practical examples shown, the activator is formed of RCl 2 . When contacted with HNO 3 , free groups are formed according to the following reactions, and as a result of reducing their properties, these free groups destroy the aluminum structures located under the chip cover.

HNO3+RCl2→2Cl-+……HNO 3 + RCl 2 → 2Cl - +... …

단지 알루미늄 구조물가 산화물 층으로 코팅될 때까지 산화 물질이 알루미늄에 영향을 미치기 때문에, HNO3과 접한 상태에서 산화 물질을 방출하는 활성체는 여기에서 바람직한 결과를 초래하지 않으며, 상기 산화물 층은 자기 보호 기능을 알루미늄 구조물에 제공하며, 전혀 알루미늄 구조물의 파괴를 초래하지 않는다.Since the oxidizing material affects aluminum only until the aluminum structure is coated with the oxide layer, an activator that releases the oxidizing material in contact with HNO 3 does not produce a desirable result here, and the oxide layer has a self-protecting function. To the aluminum structure and does not cause destruction of the aluminum structure at all.

도 1에서 부호 12로 나타내어진 활성체는 윈도우 형태의 갭 또는 오목부 내의 기밀 보호 감지 영역 상부에 제공되며, 상기 영역은 Si3N4층(5) 또는 폴리이미드 층(6)내에서 이것의 끝까지 노출된다. 스마트 카드와 같은 칩 카드가 제조될 때, 상기 활성체는 이러한 갭 또는 오목부내에 칩 커버에 의해 봉입된다.The activator indicated by reference numeral 12 in FIG. 1 is provided on top of the airtight protective sensing region in the gap or recess in the form of a window, the region of which is made of Si 3 N 4 layer 5 or polyimide layer 6 thereof. Exposed to the end. When a chip card such as a smart card is manufactured, the active body is enclosed by the chip cover in this gap or recess.

이것에 대한 대안으로, 활성체는 또한 폴리이미드 매트릭스에 통합될 수 있다.As an alternative to this, the activator may also be incorporated into the polyimide matrix.

비활성화 상태에서는 활성체가 적합한 시기에 파괴되는 알루미늄과 접촉되는 것이 요구되지는 않는다. 활성체의 위치는 다양한 요구 또는 각 칩에 적합하도록 만들어져야 한다.In the deactivated state, it is not required that the activator be contacted with aluminum, which is destroyed at a suitable time. The position of the activator must be made to suit a variety of needs or for each chip.

활성체의 타입은 칩 커버를 용해하기 위하여 사용되는 화학적 물질에 매칭되도록 바람직하게 만들어지므로, 어떤 용매가 상기 활성체에 접할 때, 활성체의 바람직한 활성화는 신뢰성 있게 초기화된다.The type of activator is preferably made to match the chemicals used to dissolve the chip cover, so that when a solvent encounters the activator, the desired activation of the activator is reliably initiated.

그러나, 이에 의하여 칩의 분석 또는 조작이 방지되는 한, 상기 활성화의 효과는 바람직한 방법으로 선택된다. 그것에 대하여 화학적 환원에 의한 상술한 알루미늄의 파괴 대신에, 예를 들어 열 에너지 등을 제공하므로써 칩을 파괴시키는 준비가 될 수 있다.However, so long as the analysis or manipulation of the chip is thereby prevented, the effect of the activation is selected in a preferred manner. Instead of destroying the above-mentioned aluminum by chemical reduction, it can be prepared to destroy the chip by providing thermal energy or the like, for example.

요구에 따라 각각 상이한 용매와 반응하는 복수개의 상이한 활성체가 준비되므로, 최고의 다양화된 타입의 용매가 적어도 한 개의 활성체를 각기 활성화시킨다.Since a plurality of different activators are prepared, each reacting with a different solvent as required, the best diversified type of solvent activates each of the at least one activator individually.

요구에 따라 활성체를 활성화시킬 수 있는 다른 물질이 또한 칩 커버내에 활성체에 부가적으로 활성체와 동일한 방법으로, 상기 활성체와는 분리되어 제공될 수 있다. 따라서 칩 커버가 제거될 때, 활성체 및 요구에 따라 활성체를 활성화시키는 물질 모두 방출되기 때문에, 상기 활성체 물질은 요구된 용매제와는 별도로 선택될 수 있다.Other materials capable of activating the activator as desired may also be provided separately from the activator in the same way as the activator in addition to the activator in the chip cover. Therefore, when the chip cover is removed, both the activator and the material activating the activator on demand are released, so that the activator material can be selected separately from the required solvent.

마지막에 언급한 가능성은, 비화학적 수단을 사용함에 의해 이러한 구조가 액세스 가능하도록 하는 시도가 있을 때, 기밀 보장과 관련된 칩 구조의 파괴가 발생한다는 장점을 제공한다.The last mentioned possibility offers the advantage that destruction of the chip structure associated with confidentiality occurs when attempts are made to make this structure accessible by using non-chemical means.

칩 커버를 제거하므로써, 이러한 것이 액세스 가능하게 되는 시도가 존재하면, 칩 커버내의 상술한 활성체의 제공은 기밀 보장과 관련된 칩의 영역이 자동적으로 파괴되는 것을 가능케 한다.If there is an attempt to make this accessible by removing the chip cover, the provision of the above-mentioned activator in the chip cover enables the area of the chip associated with the confidentiality to be automatically destroyed.

이러한 경우에 파괴되는 구조가 극도로 작은 넓이를 갖는다는 것을 고려하면, 위치 설정과 상응하여 제공되어야 하는 활성체의 양은 유사하게 극도로 소량이다.Considering that the structure to be broken in this case has an extremely small area, the amount of activator which must be provided correspondingly to the positioning is similarly extremely small.

칩의 역 처리 또는 조작에 반하는 기밀 보장을 증가시키기 위한 추가의 방법은, 최소의 기밀 보장과 관련된 칩, 즉 제시된 실시예에서는 ASIC 칩(2)을 다른 칩의 기밀 보장과 관련된 영역 상부에 정확하게, 다시 말하면, 제시된 실시예에서는 제어기 칩(1)의 최고의 기밀 보장과 관련된 영역의 상부에 정확하게 배열하는 것으로 구성된다. 광학적 액세스 가능성의 결여 때문에, 칩이 커버가 제거되지 않고 분석 또는 조작 될 수 있는 가능성 또한 이에 의해 배제된다.A further method for increasing the confidentiality against the reverse processing or manipulation of the chip is that the chip associated with the least confidentiality, ie the ASIC chip 2 in the present embodiment, is placed exactly above the area associated with the confidentiality of the other chip. In other words, in the presented embodiment it consists of arranging precisely on top of the area associated with the highest confidentiality of the controller chip 1. Because of the lack of optical accessibility, the possibility that the chip can be analyzed or manipulated without removing the cover is also ruled out by this.

상술한 실질적인 실시예는, 칩과 와이어 연결 기술을 사용한 소위 융통성 있는 구조물 상의 칩 위에 칩에 관련된다. 본 발명은 이러한 구조에만 국한되지 않고, 단일 칩의 경우 및 바람직한 방법으로 연결되어 중재적으로 배열된 복수개의 칩의 경우에서도 사용될 수 있다는 것이 명백하다.The practical embodiments described above relate to chips on chips on so-called flexible structures using chip and wire connection techniques. It is evident that the present invention is not limited to this structure, but may be used in the case of a single chip and in the case of a plurality of chips connected arbitrarily arranged in a preferred manner.

더욱이 상기 설명에 따라 사용된 물질의 한정은 존재하지 않는다. 대체 물질이 상기 물질 대신에 그들의 기능을 충족시킨다면 이러한 물질은 어떤 다른 바람직한 물질로 대체될 수 있다.Moreover, there is no limitation of the materials used according to the above description. Such materials may be replaced with any other desired material if the replacement materials fulfill their function in place of the material.

상술한 본 발명에 따른 칩 커버 설계에 의하여, 칩의 역 처리 및 조작은 장치의 설계와는 아주 관계없이 신뢰성 있고 쉽게 방지된다.By the chip cover design according to the present invention described above, reverse processing and manipulation of the chip is reliably and easily prevented regardless of the design of the device.

이상에서는 본 발명의 양호한 일 실시예에 따라 본 발명이 설명되었지만, 첨부된 청구 범위에 의해 한정되는 바와 같은 본 발명의 사상을 일탈하지 않는 범위 내에서 다양한 변형이 가능함은 본 발명이 속하는 기술 분야의 당업자에게는 명백하다.Although the present invention has been described above in accordance with one preferred embodiment of the present invention, various modifications may be made without departing from the spirit of the present invention as defined by the appended claims. It is obvious to those skilled in the art.

Claims (16)

전기, 전자, 광전자 또는 전기 기계 칩 부품을 전체 또는 부분적으로 커버링하기 위한 칩 커버에 있어서,A chip cover for covering an entirety or part of an electrical, electronic, optoelectronic or electromechanical chip component, 활성화된 상태에서 전기, 전자, 광전자 또는 전기 기계 칩 부품을 완전히 또는 부분적으로 파괴할 수 있고, 상기 칩으로부터 상기 칩 커버를 제거하려는 시도에 의해 활성화될 수 있는 활성체를 포함하는 것을 특징으로 하는 칩 커버.A chip, characterized in that it comprises an activator which, in an activated state, can completely or partially destroy an electrical, electronic, optoelectronic or electromechanical chip component and which can be activated by an attempt to remove the chip cover from the chip. cover. 제 1 항에 있어서, 칩 카드 또는 스마트 카드상에 제공된 케이싱되지 않은 칩은 상기 커버에 의해 커버링될 수 있는 것을 특징으로 하는 칩 커버.2. The chip cover of claim 1, wherein uncased chips provided on a chip card or smart card can be covered by the cover. 제 1 항 또는 제 2 항에 있어서, 상기 칩은 제어기 모듈 또는 ASIC 모듈인 것을 특징으로 하는 칩 커버.The chip cover of claim 1 or 2, wherein the chip is a controller module or an ASIC module. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 상기 활성체는 상기 칩 커버에 제공된 오목부내에 제공되는 것을 특징으로 하는 칩 커버.4. A chip cover according to any one of claims 1 to 3, wherein said active body is provided in a recess provided in said chip cover. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 상기 활성체는 커버 물질 매트릭스 내에 통합되는 것을 특징으로 하는 칩 커버.5. The chip cover of claim 1, wherein the active agent is integrated into a cover material matrix. 6. 제 1 항 내지 제 5 항 중 어느 한 항에 있어서, 환원 작용을 갖는 물질은 상기 활성체가 활성화될 때 방출되는 것을 특징으로 하는 칩 커버.The chip cover according to any one of claims 1 to 5, wherein the substance having a reducing action is released when the activator is activated. 제 6 항에 있어서, 상기 전기 전자, 광전자 또는 전기 기계 칩 부품은 상기 환원 작용을 갖는 물질에 의해 파괴되는 것을 특징으로 하는 칩 커버.7. The chip cover of claim 6, wherein the electrical, optoelectronic or electromechanical chip component is destroyed by a material having the reducing action. 제 1 항 내지 제 7 항 중 어느 한 항에 있어서, 상기 전기, 전자, 광전자 또는 전기 기계 칩 부품은 알루미늄 구조물인 것을 특징으로 하는 칩 커버.8. The chip cover of claim 1, wherein the electrical, electronic, optoelectronic or electromechanical chip component is an aluminum structure. 9. 제 1 항 내지 제 8 항 중 어느 한 항에 있어서, 상기 활성체는 RCl2인 것을 특징으로 하는 칩 커버.The chip cover according to any one of claims 1 to 8, wherein the activator is RCl 2 . 제 9 항에 있어서, 상기 RCl2가 활상화될 때, 자유기가 형성되는 것을 특징으로 하는 칩 커버.10. The chip cover of claim 9, wherein a free group is formed when RCl 2 is solvated. 제 10 항에 있어서, 상기 자유기는 환원 작용을 갖는 물질인 것을 특징으로 하는 칩 커버.The chip cover of claim 10, wherein the free group is a material having a reducing effect. 제 1 항 내지 제 11 항 중 어느 한 항에 있어서, 상기 활성체는 상기 칩 커버를 용해시키는 용매에 의해 활성화되는 것을 특징으로 하는 칩 커버.The chip cover according to any one of claims 1 to 11, wherein the activator is activated by a solvent for dissolving the chip cover. 제 1 항 내지 제 11 항 중 어느 한 항에 있어서, 상기 활성체는 상기 칩 커버 내에 저장된 활성 작용제에 의해 활성화되는 것을 특징으로 하는 칩 커버.12. The chip cover of claim 1, wherein the activator is activated by an active agent stored within the chip cover. 제 1 항 내지 제 13 항 중 어느 한 항에 있어서, 제 2 칩은 상기 칩의 기밀 보호와 관련된 영역 상부에 배열되는 것을 특징으로 하는 칩 커버.14. A chip cover according to any one of the preceding claims, wherein the second chip is arranged over an area associated with the gas tight protection of the chip. 제 1 항 내지 제 14 항 중 어느 한 항에 있어서, 상기 칩 커버 내의 상기 활성체는 상기 칩의 기밀 보호와 관련된 영역의 상부에 제공되는 것을 특징으로 하는 칩 커버.15. The chip cover according to any one of the preceding claims, wherein the active material in the chip cover is provided on top of an area associated with the gas tight protection of the chip. 제 1 항 내지 제 15 항 중 어느 한 항에 있어서, 상기 칩 커버는 다수개의 층으로 구성되는 것을 특징으로 하는 칩 커버.The chip cover according to any one of claims 1 to 15, wherein the chip cover is composed of a plurality of layers.
KR1019970707692A 1995-04-25 1996-04-09 Chip cover KR100407042B1 (en)

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