EP0807898B1 - Dispositif de circuit pour ajustement de paramètres - Google Patents

Dispositif de circuit pour ajustement de paramètres Download PDF

Info

Publication number
EP0807898B1
EP0807898B1 EP97107745A EP97107745A EP0807898B1 EP 0807898 B1 EP0807898 B1 EP 0807898B1 EP 97107745 A EP97107745 A EP 97107745A EP 97107745 A EP97107745 A EP 97107745A EP 0807898 B1 EP0807898 B1 EP 0807898B1
Authority
EP
European Patent Office
Prior art keywords
circuit arrangement
signal
current
reference signal
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97107745A
Other languages
German (de)
English (en)
Other versions
EP0807898A2 (fr
EP0807898A3 (fr
Inventor
Stephan Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP0807898A2 publication Critical patent/EP0807898A2/fr
Publication of EP0807898A3 publication Critical patent/EP0807898A3/fr
Application granted granted Critical
Publication of EP0807898B1 publication Critical patent/EP0807898B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division

Definitions

  • the invention relates to a circuit arrangement for setting parameters with at least one first analog multiplier, to which an input signal and a first control signal corresponding to a parameter is supplied and which outputs an output signal.
  • the object of the invention is to provide a circuit arrangement of the type mentioned at the outset which enables an exact and constant setting of parameters with little circuit complexity.
  • the circuit arrangement according to the invention allows, for example, the setting of the cut-off frequency of an analog universal filter by means of a single external resistor, which saves both connections, costs and space, increases the accuracy and offers high flexibility for the respective user.
  • the circuit arrangement comprises a control device which compares the output signal of the second multiplier device with a second reference signal and derives the control signals therefrom.
  • the first reference signal is selected in proportion to a third reference signal and the second reference signal is selected in proportion to the third reference signal and to a physical quantity determined by a reference element.
  • the second reference signal is given by a current which is generated by a current source controlled by the third reference signal with a transmission ratio determined by the reference element.
  • the control signals can be given by currents that are provided by a current bank at the output of the control device. These currents can be related to one another in given relationships determined by the power bank. Fixed ratios of the parameters to one another are thus set in a simple manner with high accuracy.
  • the multipliers can have differential amplifier stages which are driven by the input signals and which are fed with a current which is proportional to the respective control current.
  • the differential amplifier stages allow multiplication devices to be implemented in a simple manner, temperature influences and other effects being eliminated by the circuit arrangement according to the invention.
  • three multipliers 1, 2, 3 are provided, each of which is formed by a differential amplifier stage.
  • the differential amplifier stages each include two npn transistors 4, 5; 6, 7; 8, 9, the emitters of which are each coupled to one another and the collectors of which are each connected to a supply potential 16 via a resistor 10 to 15.
  • the base of a transistor 4, 6, 8 of the differential amplifier stage is driven by an input signal 17, 18, 19, while the bases of the other transistors 5, 7, 9 of the differential amplifier stage, the collectors of which carry output signals 20, 21, 22 a reference potential 23 is set.
  • a further multiplier 25 which has two emitter-coupled npn transistors 26 and 27.
  • the base of transistor 27 is at the reference potential 23 and the collectors of the two transistors 26 and 27 are connected via a resistor 28 and 29 to the positive supply potential 16.
  • the coupled emitters of transistors 26 and 27 are like the coupled emitters of transistors 4, 5; 6, 7; 8, 9 each connected to a negative supply potential 24 via a current source.
  • the current sources are formed by the outputs of a current bank, the input branch of which has an NPN transistor 35 connected in the forward direction by connecting the base and emitter to form a diode.
  • the emitter of transistor 35 is connected to negative supply potential 24.
  • the voltage drop across the collector-emitter path of the transistor 35 is fed to the bases of the npn transistors 28 to 34, which act as output branches of the current bank.
  • output currents are created which are in specific relationships to one another in accordance with the respectively combined outputs.
  • only one output branch - formed by the collector-emitter path of the transistor 34 or 28 - is provided in the multipliers 3 and 25, while two or three output branches are used to feed the differential amplifier stages in the multipliers 2 and 1 become.
  • the coupled emitters of transistors 6 and 7 are coupled to negative supply potential 24 via the collector-emitter paths of transistors 32 and 33 connected in parallel with one another.
  • the coupled emitters of the transistors 4 and 5 are accordingly connected to the negative supply potential 24 via the collector-emitter paths of the transistors 29, 30, 31 connected in parallel with one another. Accordingly, the input signals 17, 18, 19 are multiplied by parameters which are in a 3: 2: 1 ratio.
  • the multiplier 25 is integrated in a control loop, the control variable not only controlling the multiplier 25 but also the multipliers 1, 2, 3.
  • the control circuit also contains a comparison device 38 with a current output, which compares the voltage dropping across the resistor 37 with a voltage dropping across a resistor 39 and feeds a current proportional to the voltage difference into the transistor 35.
  • a reference voltage source 40 is provided, which on the one hand feeds voltage dividers consisting of two resistors 41 and 42 and on the other hand controls a current source.
  • the current source contains an operational amplifier 43, the non-inverting input of which is connected to a connection of the reference voltage source 40.
  • the inverting input of the operational amplifier 43 is connected to one terminal of a resistor 44, the other terminal of which, like a terminal of the resistor 42 and the reference voltage source 40, is connected to the negative supply potential 24.
  • the inverting input of the operational amplifier 43 is also connected to the emitter of a transistor 45, the base of which is connected to the output of the operational amplifier 43 and the collector of which is coupled to an input of the comparator 38 and to a connection of the resistor 39.
  • the other connection of the resistor 39 is connected to the positive supply potential 16.
  • the tap of the voltage divider is connected to the base of transistor 26.
  • the slope of the differential amplifier stages used in the multipliers 1, 2, 3, 25 depends on the respective control current fed into the coupled emitters and is set by the control loop so that the slope is inversely proportional to the value Re.
  • the resistor 44 is provided for setting the target signal. A voltage is present across the resistor 44 which is equal to the voltage Ur output by the reference voltage source 40. A current Is is thus fed into the resistor 39, which is equal to the ratio of the voltage Ur to the resistance value Re.
  • the multiplier 25, which is constructed identically to the multipliers 1, 2, 3, is supplied on the input side with a voltage which is equal to the voltage Ur multiplied by an attenuation factor. The damping factor results from the resistance values R1 and R2 of the resistors 41 and 42.
  • the resistors 37 and 39 can also be dispensed with and the currents flowing through them can be fed directly into the comparison device 36.
  • the ratios of the slopes of the individual differential amplifier stages to one another can be set in a simple manner via the ratios of the corresponding output currents of the current bank.
  • the differential amplifier stages like other circuit parts, can be operated symmetrically.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Feedback Control In General (AREA)
  • Electrophonic Musical Instruments (AREA)

Claims (6)

  1. Montage d'ajustement de paramètres ayant au moins un premier dispositif (1, 2, 3) multiplicateur analogique auquel est envoyé un signal (17, 18, 19) d'entrée, ainsi qu'un premier signal de commande correspondant à un paramètre et qui émet un signal (20, 21, 22) de sortie,
       caractérisé par un deuxième dispositif (25) multiplicateur identique au premier dispositif (1, 2, 3) multiplicateur auquel est envoyé un premier signal de référence, ainsi qu'un deuxième signal de commande correspondant au premier signal de commande et qui émet un signal (Ui) de sortie et par un dispositif (38 à 45) de régulation qui compare le signal (Ui) de sortie du deuxième dispositif (25) multiplicateur à un deuxième signal (Us) de référence et qui en déduit les signaux de commande pour tous les dispositifs (1, 2, 3, 25) multiplicateur.
  2. Montage suivant la revendication 1,
       caractérisé en ce que le premier signal de référence est proportionnel à un troisième signal (Ur) de référence et en ce que le deuxième signal (Us) de référence est proportionnel au troisième signal (Ur) de référence ainsi qu'à une grandeur (Re) physique définie par un élément (44) de référence.
  3. Montage suivant la revendication 2,
       caractérisé en ce que le deuxième signal (Us) de référence provient d'un courant (Is) qui est produit par une source (43, 44, 45) de courant qui est commandée par le troisième signal (Ur) de référence et qui a un rapport de multiplication déterminé par l'élément (44) de référence.
  4. Montage suivant la revendication 3,
       caractérisé en ce que les signaux de commande sont donnés par des courants qui sont mis à disposition par un banc (28 à 35) de courant à la sortie du dispositif (38 à 45) de régulation.
  5. Montage suivant la revendication 4,
       caractérisé en ce que les courants formant des signaux de commande sont entre eux dans des rapports donnés déterminés par le banc (28 à 35) de courant.
  6. Montage suivant l'une des revendications 1 à 4,
       caractérisé en ce que les dispositifs (1, 2, 3, 25) multiplicateurs ont des étages amplificateurs différentiels qui sont commandés par les signaux (17, 18, 19) d'entrée et qui sont alimentés par un courant proportionnel au courant de commande respectif.
EP97107745A 1996-05-17 1997-05-12 Dispositif de circuit pour ajustement de paramètres Expired - Lifetime EP0807898B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19620033A DE19620033C1 (de) 1996-05-17 1996-05-17 Schaltungsanordnung zur Parametereinstellung
DE19620033 1996-05-17

Publications (3)

Publication Number Publication Date
EP0807898A2 EP0807898A2 (fr) 1997-11-19
EP0807898A3 EP0807898A3 (fr) 1998-06-17
EP0807898B1 true EP0807898B1 (fr) 2003-01-29

Family

ID=7794643

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97107745A Expired - Lifetime EP0807898B1 (fr) 1996-05-17 1997-05-12 Dispositif de circuit pour ajustement de paramètres

Country Status (3)

Country Link
US (1) US5834963A (fr)
EP (1) EP0807898B1 (fr)
DE (2) DE19620033C1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7313452A (nl) * 1973-10-01 1975-04-03 Philips Nv Absoluut nauwkeurige geintegreerde impedantie.
US4586155A (en) * 1983-02-11 1986-04-29 Analog Devices, Incorporated High-accuracy four-quadrant multiplier which also is capable of four-quadrant division
DE3917714A1 (de) * 1989-05-31 1990-12-06 Siemens Ag Multiplizierschaltung
JPH0632061B2 (ja) * 1990-08-27 1994-04-27 喜光 松本 アナログ乗算・平均回路及び該回路を使用した電力計回路

Also Published As

Publication number Publication date
DE19620033C1 (de) 1997-12-11
EP0807898A2 (fr) 1997-11-19
EP0807898A3 (fr) 1998-06-17
DE59709210D1 (de) 2003-03-06
US5834963A (en) 1998-11-10

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