EP0807898B1 - Circuit arrangement for parameter adjustment - Google Patents
Circuit arrangement for parameter adjustment Download PDFInfo
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- EP0807898B1 EP0807898B1 EP97107745A EP97107745A EP0807898B1 EP 0807898 B1 EP0807898 B1 EP 0807898B1 EP 97107745 A EP97107745 A EP 97107745A EP 97107745 A EP97107745 A EP 97107745A EP 0807898 B1 EP0807898 B1 EP 0807898B1
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- European Patent Office
- Prior art keywords
- circuit arrangement
- signal
- current
- reference signal
- arrangement according
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
Definitions
- the invention relates to a circuit arrangement for setting parameters with at least one first analog multiplier, to which an input signal and a first control signal corresponding to a parameter is supplied and which outputs an output signal.
- the object of the invention is to provide a circuit arrangement of the type mentioned at the outset which enables an exact and constant setting of parameters with little circuit complexity.
- the circuit arrangement according to the invention allows, for example, the setting of the cut-off frequency of an analog universal filter by means of a single external resistor, which saves both connections, costs and space, increases the accuracy and offers high flexibility for the respective user.
- the circuit arrangement comprises a control device which compares the output signal of the second multiplier device with a second reference signal and derives the control signals therefrom.
- the first reference signal is selected in proportion to a third reference signal and the second reference signal is selected in proportion to the third reference signal and to a physical quantity determined by a reference element.
- the second reference signal is given by a current which is generated by a current source controlled by the third reference signal with a transmission ratio determined by the reference element.
- the control signals can be given by currents that are provided by a current bank at the output of the control device. These currents can be related to one another in given relationships determined by the power bank. Fixed ratios of the parameters to one another are thus set in a simple manner with high accuracy.
- the multipliers can have differential amplifier stages which are driven by the input signals and which are fed with a current which is proportional to the respective control current.
- the differential amplifier stages allow multiplication devices to be implemented in a simple manner, temperature influences and other effects being eliminated by the circuit arrangement according to the invention.
- three multipliers 1, 2, 3 are provided, each of which is formed by a differential amplifier stage.
- the differential amplifier stages each include two npn transistors 4, 5; 6, 7; 8, 9, the emitters of which are each coupled to one another and the collectors of which are each connected to a supply potential 16 via a resistor 10 to 15.
- the base of a transistor 4, 6, 8 of the differential amplifier stage is driven by an input signal 17, 18, 19, while the bases of the other transistors 5, 7, 9 of the differential amplifier stage, the collectors of which carry output signals 20, 21, 22 a reference potential 23 is set.
- a further multiplier 25 which has two emitter-coupled npn transistors 26 and 27.
- the base of transistor 27 is at the reference potential 23 and the collectors of the two transistors 26 and 27 are connected via a resistor 28 and 29 to the positive supply potential 16.
- the coupled emitters of transistors 26 and 27 are like the coupled emitters of transistors 4, 5; 6, 7; 8, 9 each connected to a negative supply potential 24 via a current source.
- the current sources are formed by the outputs of a current bank, the input branch of which has an NPN transistor 35 connected in the forward direction by connecting the base and emitter to form a diode.
- the emitter of transistor 35 is connected to negative supply potential 24.
- the voltage drop across the collector-emitter path of the transistor 35 is fed to the bases of the npn transistors 28 to 34, which act as output branches of the current bank.
- output currents are created which are in specific relationships to one another in accordance with the respectively combined outputs.
- only one output branch - formed by the collector-emitter path of the transistor 34 or 28 - is provided in the multipliers 3 and 25, while two or three output branches are used to feed the differential amplifier stages in the multipliers 2 and 1 become.
- the coupled emitters of transistors 6 and 7 are coupled to negative supply potential 24 via the collector-emitter paths of transistors 32 and 33 connected in parallel with one another.
- the coupled emitters of the transistors 4 and 5 are accordingly connected to the negative supply potential 24 via the collector-emitter paths of the transistors 29, 30, 31 connected in parallel with one another. Accordingly, the input signals 17, 18, 19 are multiplied by parameters which are in a 3: 2: 1 ratio.
- the multiplier 25 is integrated in a control loop, the control variable not only controlling the multiplier 25 but also the multipliers 1, 2, 3.
- the control circuit also contains a comparison device 38 with a current output, which compares the voltage dropping across the resistor 37 with a voltage dropping across a resistor 39 and feeds a current proportional to the voltage difference into the transistor 35.
- a reference voltage source 40 is provided, which on the one hand feeds voltage dividers consisting of two resistors 41 and 42 and on the other hand controls a current source.
- the current source contains an operational amplifier 43, the non-inverting input of which is connected to a connection of the reference voltage source 40.
- the inverting input of the operational amplifier 43 is connected to one terminal of a resistor 44, the other terminal of which, like a terminal of the resistor 42 and the reference voltage source 40, is connected to the negative supply potential 24.
- the inverting input of the operational amplifier 43 is also connected to the emitter of a transistor 45, the base of which is connected to the output of the operational amplifier 43 and the collector of which is coupled to an input of the comparator 38 and to a connection of the resistor 39.
- the other connection of the resistor 39 is connected to the positive supply potential 16.
- the tap of the voltage divider is connected to the base of transistor 26.
- the slope of the differential amplifier stages used in the multipliers 1, 2, 3, 25 depends on the respective control current fed into the coupled emitters and is set by the control loop so that the slope is inversely proportional to the value Re.
- the resistor 44 is provided for setting the target signal. A voltage is present across the resistor 44 which is equal to the voltage Ur output by the reference voltage source 40. A current Is is thus fed into the resistor 39, which is equal to the ratio of the voltage Ur to the resistance value Re.
- the multiplier 25, which is constructed identically to the multipliers 1, 2, 3, is supplied on the input side with a voltage which is equal to the voltage Ur multiplied by an attenuation factor. The damping factor results from the resistance values R1 and R2 of the resistors 41 and 42.
- the resistors 37 and 39 can also be dispensed with and the currents flowing through them can be fed directly into the comparison device 36.
- the ratios of the slopes of the individual differential amplifier stages to one another can be set in a simple manner via the ratios of the corresponding output currents of the current bank.
- the differential amplifier stages like other circuit parts, can be operated symmetrically.
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Control Of Amplification And Gain Control (AREA)
- Feedback Control In General (AREA)
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Description
Die Erfindung betrifft eine Schaltungsanordnung zur Parametereinstellung mit mindestens einer ersten analogen Multipliziereinrichtung, der ein Eingangssignal sowie ein einem Parameter entsprechendes erstes Steuersignal zugeführt wird und die ein Ausgangssignal abgibt.The invention relates to a circuit arrangement for setting parameters with at least one first analog multiplier, to which an input signal and a first control signal corresponding to a parameter is supplied and which outputs an output signal.
Der Einsatz von analogen Multiplizierern zur Einstellung von Parametern, insbesondere von Filterparametern, wird beispielsweise bei U. Tietze, Ch. Schenk, Electronic Circuits-Design and Applications, Springer Verlag Berlin, Heidelberg 1991 vorgeschlagen. Problematisch ist bei derartigen Schaltungsanordnungen zum einen das exakte Einstellen der gewünschten Parameter und zum anderen das Konstanthalten der eingestellten Parameter. Das Einstellen der Parameter erfolgte bisher meist durch jeweils ein externes Referenzelement pro einzustellendem Parameter. Nachteilig ist bei einer Integration der Schaltung die nötige hohe Anzahl externer Referenzelemente sowie der zugehörigen Anschlüsse bei der integrierten Schaltung. Hinsichtlich der Konstanthaltung der gewünschten Parameter werden die verwendeten Multiplizierer einzeln derart ausgelegt, daß ihre Eigenschaften durch die jeweils zugehörigen Referenzelemente exakt und konstant definiert sind. Der notwendige Schaltungsaufwand erhöht sich dadurch.The use of analog multipliers for setting parameters, in particular filter parameters, is proposed, for example, by U. Tietze, Ch. Schenk, Electronic Circuits-Design and Applications, Springer Verlag Berlin, Heidelberg 1991. The problem with such circuit arrangements is on the one hand the exact setting of the desired parameters and on the other hand keeping the set parameters constant. Up to now, the parameters have mostly been set by one external reference element for each parameter to be set. A disadvantage of integrating the circuit is the high number of external reference elements required and the associated connections for the integrated circuit. With regard to keeping the desired parameters constant, the multipliers used are individually designed such that their properties are precisely and constantly defined by the associated reference elements. This increases the necessary circuitry.
Aufgabe der Erfindung ist es, eine Schaltungsanordnung der eingangs genannten Art anzugeben, die mit geringem Schaltungsaufwand eine exakte und konstante Einstellung von Parametern ermöglicht.The object of the invention is to provide a circuit arrangement of the type mentioned at the outset which enables an exact and constant setting of parameters with little circuit complexity.
Die Aufgabe wird durch eine Schaltungsanordnung gemäß Patentanspruch 1 gelöst. Ausgestaltungen und Weiterbildungen der Erfindung sind Gegenstand von Unteransprüchen.The object is achieved by a circuit arrangement according to claim 1. Refinements and developments of the invention are the subject of dependent claims.
Die erfindungsgemäße Schaltungsanordnung erlaubt beispielsweise die Einstellung der Grenzfrequenz eines analogen Universalfilters durch einen einzigen externen Widerstand, was sowohl Anschlüsse, Kosten und Platz einspart, die Genauigkeit erhöht und eine hohe Flexibilität für den jeweiligen Anwender bietet.The circuit arrangement according to the invention allows, for example, the setting of the cut-off frequency of an analog universal filter by means of a single external resistor, which saves both connections, costs and space, increases the accuracy and offers high flexibility for the respective user.
Erzielt wird dies insbesondere mit mindestens einer ersten analogen Multipliziereinrichtung, der ein Eingangssignal sowie ein einem Parameter entsprechendes erstes Steuersignal zugeführt wird und die ein Ausgangssignal abgibt. Außerdem ist eine zur ersten Multiplikationseinrichtung identisch ausgeführte zweite Multiplikationseinrichtung vorgesehen, der ein erstes Referenzsignal sowie ein dem ersten Steuersignal entsprechendes zweites Steuersignal zugeführt werden und die ein Ausgangssignal abgibt. Schließlich umfaßt die erfindungsgemäße Schaltungsanordnung eine Regeleinrichtung, die das Ausgangssignal der zweiten Multipliziereinrichtung mit einem zweiten Referenzsignal vergleicht und daraus die Steuersignale herleitet.This is achieved in particular with at least one first analog multiplier device, which is supplied with an input signal and a first control signal corresponding to a parameter and which outputs an output signal. In addition, a second multiplication device which is identical to the first multiplication device is provided, to which a first reference signal and a second control signal corresponding to the first control signal are supplied and which emits an output signal. Finally, the circuit arrangement according to the invention comprises a control device which compares the output signal of the second multiplier device with a second reference signal and derives the control signals therefrom.
Bei der Weiterbildung der Erfindung wird das erste Referenzsignal proportional zu einem dritten Referenzsignal und das zweite Referenzsignal proportional zu dem dritten Referenzsignal sowie zu einer durch ein Referenzelement bestimmten physikalischen Größe gewählt. Vorteil dabei ist, daß an das dritte Referenzsignal keine zu hohen Genauigkeitsanforderungen gestellt werden müssen, da Schwankungen durch die Schaltung kompensiert werden.In the development of the invention, the first reference signal is selected in proportion to a third reference signal and the second reference signal is selected in proportion to the third reference signal and to a physical quantity determined by a reference element. The advantage here is that the accuracy of the third reference signal does not have to be too high, since fluctuations are compensated for by the circuit.
Weiterhin kann vorgesehen werden, daß das zweite Referenzsignal durch einen Strom gegeben ist, der durch eine durch das dritte Referenzsignal gesteuerte Stromquelle mit einem durch das Referenzelement bestimmten Übersetzungsverhältnis erzeugt wird.Furthermore, it can be provided that the second reference signal is given by a current which is generated by a current source controlled by the third reference signal with a transmission ratio determined by the reference element.
Die Steuersignale können dabei durch Ströme gegeben sein, die durch eine Strombank am Ausgang der Regeleinrichtung bereitgestellt werden. Diese Ströme können in gegebenen, durch die Strombank bestimmten Verhältnissen zueinander stehen. Damit werden auf einfache Weise feste Verhältnisse der Parameter untereinander mit hoher Genauigkeit eingestellt.The control signals can be given by currents that are provided by a current bank at the output of the control device. These currents can be related to one another in given relationships determined by the power bank. Fixed ratios of the parameters to one another are thus set in a simple manner with high accuracy.
Schließlich können die Multipliziereinrichtungen Differenzverstärkerstufen aufweisen, die durch die Eingangssignale angesteuert werden und die mit einem zum jeweiligen Steuerstrom proportionalen Strom gespeist werden. Durch die Differenzverstärkerstufen werden auf einfache Weise Multipliziereinrichtungen realisiert, wobei Temperatureinflüsse und sonstige Einwirkungen durch die erfindungsgemäße Schaltungsanordnung ausgeschaltet werden.Finally, the multipliers can have differential amplifier stages which are driven by the input signals and which are fed with a current which is proportional to the respective control current. The differential amplifier stages allow multiplication devices to be implemented in a simple manner, temperature influences and other effects being eliminated by the circuit arrangement according to the invention.
Die Erfindung wird nachfolgend anhand des in der einzigen Figur der Zeichnung dargestellten Ausführungsbeispiels näher erläutert.The invention is explained in more detail below with reference to the embodiment shown in the single figure of the drawing.
Beim gezeigten Ausführungsbeispiel sind drei Multipliziereinrichtungen 1, 2, 3 vorgesehen, die jeweils durch eine Differenzverstärkerstufe gebildet werden. Die Differenzverstärkerstufen umfassen dabei jeweils zwei npn-Transistoren 4, 5; 6, 7; 8, 9, deren Emitter jeweils miteinander gekoppelt sind und deren Kollektoren über jeweils einen Widerstand 10 bis 15 an ein Versorgungspotential 16 angeschlossen sind. Die Basis jeweils eines Transistors 4, 6, 8 der Differenzverstärkerstufe wird dabei durch ein Eingangssignal 17, 18, 19 angesteuert, während die Basen der jeweils anderen Transistoren 5, 7, 9 der Differenzverstärkerstufe, deren Kollektoren Ausgangssignale 20, 21, 22 führen, an ein Bezugspotential 23 gelegt sind.In the exemplary embodiment shown, three multipliers 1, 2, 3 are provided, each of which is formed by a differential amplifier stage. The differential amplifier stages each include two npn transistors 4, 5; 6, 7; 8, 9, the emitters of which are each coupled to one another and the collectors of which are each connected to a supply potential 16 via a resistor 10 to 15. The base of a transistor 4, 6, 8 of the differential amplifier stage is driven by an input signal 17, 18, 19, while the bases of the other transistors 5, 7, 9 of the differential amplifier stage, the collectors of which carry output signals 20, 21, 22 a reference potential 23 is set.
Zudem ist eine weitere Multipliziereinrichtung 25 vorgesehen, die zwei emittergekoppelte npn-Transistoren 26 und 27 aufweist. Die Basis des Transistors 27 ist dabei an das Bezugspotential 23 gelegt und die Kollektoren der beiden Transistoren 26 und 27 sind über jeweils einen Widerstand 28 und 29 mit dem positiven Versorgungspotential 16 verschaltet. Die gekoppelten Emitter der Transistoren 26 und 27 sind ebenso wie die gekoppelten Emitter der Transistoren 4, 5; 6, 7; 8, 9 über jeweils eine Stromquelle mit einem negativen Versorgungspotential 24 verbunden. Die Stromquellen werden durch die Ausgänge einer Strombank gebildet, deren Eingangszweig einen durch Verbinden von Basis und Emitter zu einer Diode in Durchlaßrichtung verschalteten npn-Transistor 35 aufweist. Der Emitter des Transistors 35 ist an das negative Versorgungspotential 24 angeschlossen. Die über der Kollektor-Emitter-Strecke des Transistors 35 abfallende Spannung wird dabei den Basen der npn-Transistoren 28 bis 34 zugeführt, die als Ausgangszweige der Strombank fungieren.In addition, a further multiplier 25 is provided, which has two emitter-coupled npn transistors 26 and 27. The base of transistor 27 is at the reference potential 23 and the collectors of the two transistors 26 and 27 are connected via a resistor 28 and 29 to the positive supply potential 16. The coupled emitters of transistors 26 and 27 are like the coupled emitters of transistors 4, 5; 6, 7; 8, 9 each connected to a negative supply potential 24 via a current source. The current sources are formed by the outputs of a current bank, the input branch of which has an NPN transistor 35 connected in the forward direction by connecting the base and emitter to form a diode. The emitter of transistor 35 is connected to negative supply potential 24. The voltage drop across the collector-emitter path of the transistor 35 is fed to the bases of the npn transistors 28 to 34, which act as output branches of the current bank.
Beispielsweise durch Zusammenfassen einzelner Stromausgänge werden Ausgangsströme geschaffen, die entsprechend der jeweils zusammengefaßten Ausgänge in bestimmten Verhältnissen zueinander stehen. So ist gemäß dem Ausführungsbeispiel bei den Multipliziereinrichtungen 3 und 25 jeweils nur ein Ausgangszweig - gebildet durch die Kollektor-Emitter-Strecke des Transistors 34 bzw. 28 - vorgesehen, während zur Speisung der Differenzverstärkerstufen bei den Multipliziereinrichtungen 2 und 1 zwei bzw. drei Ausgangszweige verwendet werden. Demzufolge sind die gekoppelten Emitter der Transistoren 6 und 7 über die einander parallel geschalteten Kollektor-Emitter-Strecken der Transistoren 32 und 33 mit dem negativen Versorgungspotential 24 gekoppelt. Die gekoppelten Emitter der Transistoren 4 und 5 sind demgemäß über die einander parallel geschalteten Kollektor-Emitter-Strecken der Transistoren 29, 30, 31 an das negative Versorgungspotential 24 gelegt. Dem entsprechend werden die Eingangssignale 17, 18, 19 mit Parametern multipliziert, die im Verhältnis 3:2:1 zueinander stehen.For example, by combining individual current outputs, output currents are created which are in specific relationships to one another in accordance with the respectively combined outputs. Thus, according to the exemplary embodiment, only one output branch - formed by the collector-emitter path of the transistor 34 or 28 - is provided in the multipliers 3 and 25, while two or three output branches are used to feed the differential amplifier stages in the multipliers 2 and 1 become. As a result, the coupled emitters of transistors 6 and 7 are coupled to negative supply potential 24 via the collector-emitter paths of transistors 32 and 33 connected in parallel with one another. The coupled emitters of the transistors 4 and 5 are accordingly connected to the negative supply potential 24 via the collector-emitter paths of the transistors 29, 30, 31 connected in parallel with one another. Accordingly, the input signals 17, 18, 19 are multiplied by parameters which are in a 3: 2: 1 ratio.
Zur Eliminierung von Temperatureinflüssen und sonstiger Einwirkungen auf die Multipliziereinrichtungen 1, 2, 3 ist die Multipliziereinrichtung 25 in einen Regelkreis eingebunden, wobei durch die Steuergröße nicht nur die Multipliziereinrichtung 25, sondern auch die Multipliziereinrichtungen 1, 2, 3 angesteuert werden.To eliminate temperature influences and other effects on the multipliers 1, 2, 3, the multiplier 25 is integrated in a control loop, the control variable not only controlling the multiplier 25 but also the multipliers 1, 2, 3.
Der Regelkreis enthält zudem eine Vergleichseinrichtung 38 mit Stromausgang, die die über den Widerstand 37 abfallende Spannung mit einer über einem Widerstand 39 abfallenden Spannung vergleicht und einen zur Spannungsdifferenz proportionalen Strom in den Transistor 35 einspeist. Weiterhin ist eine Referenzspannungsquelle 40 vorgesehen, die zum einen einen aus zwei Widerständen 41 und 42 bestehenden Spannungsteiler speist und zum anderen eine Stromquelle steuert. Die Stromquelle enthält einen Operationsverstärker 43, dessen nichtinvertierender Eingang mit einem Anschluß der Referenzspannungsquelle 40 verbunden ist. Der invertierende Eingang des Operationsverstärkers 43 ist mit einem Anschluß eines Widerstands 44 verbunden, dessen anderer Anschluß ebenso wie ein Anschluß des Widerstandes 42 und der Referenzspannungsquelle 40 mit dem negativen Versorgungspotential 24 verschaltet ist. Der invertierende Eingang des Operationsverstärkers 43 ist zudem mit dem Emitter eines Transistors 45 verbunden, dessen Basis mit dem Ausgang des Operationsverstärkers 43 verschaltet ist und dessen Kollektor zum einen mit einem Eingang des Vergleichers 38 sowie mit einem Anschluß des Widerstandes 39 gekoppelt ist. Der andere Anschluß des Widerstandes 39 ist an das positive Versorgungspotential 16 gelegt. Schließlich ist der Abgriff des Spannungsteilers mit der Basis des Transistors 26 verbunden.The control circuit also contains a comparison device 38 with a current output, which compares the voltage dropping across the resistor 37 with a voltage dropping across a resistor 39 and feeds a current proportional to the voltage difference into the transistor 35. Furthermore, a reference voltage source 40 is provided, which on the one hand feeds voltage dividers consisting of two resistors 41 and 42 and on the other hand controls a current source. The current source contains an operational amplifier 43, the non-inverting input of which is connected to a connection of the reference voltage source 40. The inverting input of the operational amplifier 43 is connected to one terminal of a resistor 44, the other terminal of which, like a terminal of the resistor 42 and the reference voltage source 40, is connected to the negative supply potential 24. The inverting input of the operational amplifier 43 is also connected to the emitter of a transistor 45, the base of which is connected to the output of the operational amplifier 43 and the collector of which is coupled to an input of the comparator 38 and to a connection of the resistor 39. The other connection of the resistor 39 is connected to the positive supply potential 16. Finally, the tap of the voltage divider is connected to the base of transistor 26.
Die Steilheit der in den Multipliziereinrichtungen 1, 2, 3, 25 verwendeten Differenzverstärkerstufen hängt vom jeweiligen in die gekoppelten Emitter eingespeisten Steuerstrom ab und wird von dem Regelkreis so eingestellt, daß die Steilheit umgekehrt proportional zum Wert Re ist. Der Widerstand 44 ist dabei zur Einstellung des Sollsignals vorgesehen. Über dem Widerstand 44 liegt eine Spannung, die gleich der von der Referenzspannungsquelle 40 abgegebenen Spannung Ur ist. Somit wird in den Widerstand 39 ein Strom Is eingespeist, der gleich dem Verhältnis der Spannung Ur zum Widerstandswert Re ist. Die Multipliziereinrichtung 25, die identisch zu den Multipliziereinrichtungen 1, 2, 3 aufgebaut ist, wird eingangsseitig mit einer Spannung versorgt, die gleich der Spannung Ur multipliziert mit einem Dämpfungsfaktor ist. Der Dämpfungsfaktor ergibt sich aus den Widerstandswerten R1 und R2 der Widerstände 41 und 42. Er ist gleich dem Widerstandswert R1 geteilt durch die Summe der Widerstandswerte R1 und R2. Zusammen mit der Steilheit G der Multiplikationseinrichtung 25 ergibt sich über dem Widerstand 37 folgende Spannung Ui:
Wird eine Vergleichseinrichtung 36 mit Stromeingängen verwendet, so kann zudem auf die Widerstände 37 und 39 verzichtet werden und die sie jeweils durchfließenden Ströme direkt in die Vergleichseinrichtung 36 eingespeist werden. Die Verhältnisse der Steilheiten der einzelnen Differenzverstärkerstufen zueinander können über die Verhältnisse der entsprechenden Ausgangsströme der Strombank auf einfache Weise eingestellt werden. Schließlich können die Differenzverstärkerstufen, wie auch andere Schaltungsteile, symmetrisch betrieben werden.If a comparison device 36 with current inputs is used, the resistors 37 and 39 can also be dispensed with and the currents flowing through them can be fed directly into the comparison device 36. The ratios of the slopes of the individual differential amplifier stages to one another can be set in a simple manner via the ratios of the corresponding output currents of the current bank. Finally, the differential amplifier stages, like other circuit parts, can be operated symmetrically.
Claims (6)
- Circuit arrangement for parameter setting, having at least one first analog multiplying device (1, 2, 3), to which an input signal (17, 18, 19) and also a first control signal which corresponds to a parameter are fed and which outputs an output signal (20, 21, 22), characterized by a second multiplying device (25), which is identical to the first multiplying device (1, 2, 3) and to which a first reference signal and also a second control signal which corresponds to the first control signal are fed and which outputs an output signal (Ui), and by a regulating device (38 to 45), which compares the output signal (Ui) of the second multiplying device (25) with a second reference signal (Us) and from this derives the control signals for all the multiplying devices (1, 2, 3, 25).
- Circuit arrangement according to Claim 1, characterized in that the first reference signal is proportional to a third reference signal (Ur), and in that the second reference signal (Us) is proportional to the third reference signal (Ur) and also to a physical quantity (Re) determined by a reference element (44).
- Circuit arrangement according to Claim 2, characterized in that the second reference signal (Us) originates from a current (Is) which is generated by a current source (43, 44, 45) which is controlled by the third reference signal (Ur) and has a translation ratio determined by the reference element (44).
- Circuit arrangement according to Claim 3, characterized in that the control signals are given by currents which are provided by a current bank (28 to 35) at the output of the regulating device (38 to 45).
- Circuit arrangement according to Claim 4, characterized in that the currents which form control signals are in given ratios to one another which are determined by the current bank (28 to 35).
- Circuit arrangement according to one of Claims 1 to 4, characterized in that the multiplying devices (1, 2, 3, 25) have differential amplifier stages which are driven by the input signals (17, 18, 19) and are fed with a current which is proportional to the respective control current.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19620033A DE19620033C1 (en) | 1996-05-17 | 1996-05-17 | Circuit arrangement for parameter setting |
| DE19620033 | 1996-05-17 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0807898A2 EP0807898A2 (en) | 1997-11-19 |
| EP0807898A3 EP0807898A3 (en) | 1998-06-17 |
| EP0807898B1 true EP0807898B1 (en) | 2003-01-29 |
Family
ID=7794643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP97107745A Expired - Lifetime EP0807898B1 (en) | 1996-05-17 | 1997-05-12 | Circuit arrangement for parameter adjustment |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5834963A (en) |
| EP (1) | EP0807898B1 (en) |
| DE (2) | DE19620033C1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7313452A (en) * | 1973-10-01 | 1975-04-03 | Philips Nv | ABSOLUTELY ACCURATE INTEGRATED IMPEDANCE. |
| US4586155A (en) * | 1983-02-11 | 1986-04-29 | Analog Devices, Incorporated | High-accuracy four-quadrant multiplier which also is capable of four-quadrant division |
| DE3917714A1 (en) * | 1989-05-31 | 1990-12-06 | Siemens Ag | MULTIPLIZER CIRCUIT |
| JPH0632061B2 (en) * | 1990-08-27 | 1994-04-27 | 喜光 松本 | Analog multiplication / averaging circuit and power meter circuit using the circuit |
-
1996
- 1996-05-17 DE DE19620033A patent/DE19620033C1/en not_active Expired - Fee Related
-
1997
- 1997-05-12 DE DE59709210T patent/DE59709210D1/en not_active Expired - Lifetime
- 1997-05-12 EP EP97107745A patent/EP0807898B1/en not_active Expired - Lifetime
- 1997-05-19 US US08/858,818 patent/US5834963A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5834963A (en) | 1998-11-10 |
| EP0807898A3 (en) | 1998-06-17 |
| EP0807898A2 (en) | 1997-11-19 |
| DE59709210D1 (en) | 2003-03-06 |
| DE19620033C1 (en) | 1997-12-11 |
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