EP0797183B1 - Matrixanzeigevorrichtung und Verfahren zu ihrer Ansteuerung - Google Patents

Matrixanzeigevorrichtung und Verfahren zu ihrer Ansteuerung Download PDF

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Publication number
EP0797183B1
EP0797183B1 EP97301749A EP97301749A EP0797183B1 EP 0797183 B1 EP0797183 B1 EP 0797183B1 EP 97301749 A EP97301749 A EP 97301749A EP 97301749 A EP97301749 A EP 97301749A EP 0797183 B1 EP0797183 B1 EP 0797183B1
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EP
European Patent Office
Prior art keywords
sampling
clock signal
reference clock
sampling interval
period
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EP97301749A
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English (en)
French (fr)
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EP0797183A1 (de
Inventor
Katsuya Mizukata
Manabu Tanaka
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/0122—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal the input and the output signals having different aspect ratios
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0421—Horizontal resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0442—Handling or displaying different aspect ratios, or changing the aspect ratio
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/045—Zooming at least part of an image, i.e. enlarging it or shrinking it
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • the present invention relates to a matrix-type display device, such as an active matrix-type liquid crystal display device, having a characteristic method for sampling displayed data, and also relates to a method for driving the matrix-type display device.
  • a conventional matrix-type display device incorporates a plurality of pixel electrodes 21 (represented as. PIX in the figure) arranged in matrix, and a row electrode driving circuit 22 and a column electrode driving circuit 23 for turning on/off the pixel electrodes 21.
  • Each pixel electrode 21 is connected to a switching element 24, and opening/closing of each switching element 24 is controlled by the column electrode driving circuit 23.
  • Display data outputted from the row electrode driving circuit 22 are supplied through the switching elements 24 to the pixel electrodes 21.
  • the row electrode driving circuit 22 samples and holds a video signal S in inputted during one horizontal period, in synchronization with a sampling clock signal CK s during a horizontal scanning period. Then, during the next horizontal scanning period, the data thus held are supplied as display data S out (S out1 , S out2 , ...) to the row electrodes in a single step.
  • the column electrode driving circuit 23 sequentially outputs scanning signals G 1 , G 2 , ..., one signal per one horizontal scanning period, which cause the column electrodes to turned on so that the display data S out thus supplied to the row electrodes are supplied to the pixel electrodes 21.
  • a display medium liquid crystal, etc., not shown in the figures
  • a display medium liquid crystal, etc., not shown in the figures
  • An image is displayed in a manner such that a vertical scanning is carried out with respect to each field so that the image is displayed from an upper part of the screen downward.
  • the scanning is suspended for a predetermined period of time (flyback time), and thereafter the scanning is resumed from the upper part of the screen.
  • TVs each having a screen at an aspect ratio of 16:9 are recently in common use, whereas TV stations have started broadcasting in a display mode for a high definition television (HDTV) and in a display mode for an extended definition television 2 (EDTV2). Therefore, among flat plate-type display devices such as liquid crystal display devices, those having laterally long screens (wide screens) come to be viewed with interest.
  • HDMI high definition television
  • EDTV2 extended definition television 2
  • an electron beam is controlled by the use of deflecting coils, so that the display quality does not deteriorate even when images in the mode for the present broadcasting are displayed.
  • types of display by this method there are a so-called normal display mode and a so-called wide display mode.
  • a display screen size (aspect ratio) is determined from the viewpoint of production efficiency, the aspect ratio subtly varies with widths across corners of individual display screens. This is because glass substrates for the screens actually cut out from a mother glass have aspect ratios of 16:9.1, 15.9:9, etc. in the case of wide screens, so that as many glass substrates as possible can be obtained. Therefore, the use of the same sampling frequency may cause the roundness to deteriorate. Therefore, anyway, the clock frequency should be adjusted or changed.
  • FIG. 13 illustrates respective examples of sampling timings in these display modes.
  • sampling timings are in synchronization with rising and falling edges of a sampling clock signal.
  • the sampling frequency is switched so as to be lower, during the effective scanning period, than that during the horizontal flyback period.
  • the sampling frequency is arranged so as to gradually change during the effective scanning period.
  • a sampling clock signal is obtained by dividing, by a frequency dividing circuit 26, a reference clock signal CK g generated by a reference clock oscillator 25 incorporating a crystal oscillator or a voltage control oscillator (VCO). Therefore, to change the sampling frequency, it is necessary to change either a division ratio 1/N (N is an integral number) of the dividing circuit 26, or a frequency of the reference clock signal CK g .
  • the circuit has a plurality of reference clock oscillators RG 11 , RG 12 , ... which have different oscillation frequencies and output reference clock signals CK g1 , CK g2 , ... , respectively.
  • One reference clock signal is selected among those above by a switching circuit 27 and is outputted as the reference clock signal CK g .
  • the reference clock signals CK g1 , CK g2 , ... are sequentially chosen as the reference clock signal CK g by switching operations of the switching circuit 27 in response to switching control signals supplied from outside, thereby causing the reference clock signal CK g to have different oscillation frequencies.
  • the switching control signals are generated at predetermined timings based on an external clock signal which has a higher frequency than that of a horizontal synchronization signal and those of the reference clock signals CK g1 , CK g2 , ....
  • N may be adjusted.
  • the reference clock signal CK g has a frequency of 95 MHz and N is set to 19 and 20, sampling frequencies of 5 MHz and 4.75 MHz are obtained, whose rate of change is 5 percent.
  • N since N is set to a great number, the reference clock signal CK g has an extremely high frequency, thereby causing radiation to increase and costs of the display device to rise.
  • the sampling interval may become too small depending on the switching timings, thereby causing hitches in sampling operations by the row electrode driving circuit 22. Since provided as the row electrode driving circuit 22 is usually an integrated circuit composed of transistors or the like, a minimum sampling interval is determined depending on an operation frequency of the integrated circuit. Therefore, in the case where a sampling interval is set smaller than the minimum sampling interval thus determined, the reliability of the sampling operation of the integrated circuit cannot be ensured.
  • a reference clock signal CK g1 and a reference clock signal CK g2 having a cycle which is 1.5 fold of that of the reference clock signal CK g1 are switched from one to the other, the following may occur since the reference clock signals CK g1 and CK g2 differ in phases: in the case where a switching timing in accordance with an external clock signal, for switching from the reference clock signal CK g1 to the reference clock signal CK g2 , falls in a period where the reference clock signal CK g1 is at a high level, a sampling interval in this case, as indicated by t 2 , may be smaller than the other sampling intervals.
  • the driving system has a complicated arrangement since means for adjusting a control voltage is necessitated. Furthermore, there arises an inconvenience that costs of the display device rise, since a phase-locked loop (PLL) including a VCO capable of high-speed response is necessitated so that the frequency is changed during one horizontal scanning period (63.5 ⁇ s in the case of a TV signal).
  • PLL phase-locked loop
  • JP-A-60 059 643 discloses a further example of the prior art approach described above in which a VCO is used as the reference clock oscillator.
  • EP-A-0 765 078 which is prior art under Article 54(3) EPC, discloses a liquid crystal display in which the output from a clock generator is supplied to an array of frequency dividers arranged in parallel to one another. The output from one of the frequency dividers is selected by a switch.
  • a first aspect of the present invention provides a method of driving a matrix-type display device as clamed in claim 1.
  • a second aspect of the present invention provides a matrix-type display device as clamed in claim 8.
  • the present invention is made in light of the above problems, and the object of the present invention is to restrain a rate of change of sampling frequencies without raising a frequency of a reference clock signal, to enhance reliability of sampling operations, and to realize the sampling operations with a simpler arrangement.
  • a method for driving a matrix-type display device comprising the steps of (a) sampling an analogue display signal of at least one horizontal scanning period in synchronization with sampling clocks, and supplying the sampled display signal to each pixel electrode row aligned in a horizontal direction among pixels provided in matrix, and (b) sequentially selecting the pixel electrode rows in a vertical direction, one pixel electrode row being selected during one horizontal scanning period, in order to supply the sampled display signal from a signal supplying circuit to the selected pixel electrode row, wherein sampling intervals are changed within one horizontal scanning period, so as to provide at least a first sampling interval and a second, different sampling interval even during a period when the sampling intervals are set substantially constant.
  • the sampling intervals include at least a first sampling interval and a second, different sampling interval
  • division ratios which are switched so as to change the sampling intervals can be set close to each other in the case where the sampling clocks are obtained by dividing reference clock signal.
  • N of a division ratio 1/N is set to an integral number, but in this case where the sampling intervals, that is, the sampling clocks, have unequal parts, N may be set to a number other than integral numbers, namely, a number having decimals.
  • restrictions on the setting of the division ratio is relaxed, thereby allowing N to be set to a smaller number.
  • the frequency of the reference clock signal can be set lower.
  • a matrix-type display device having a laterally long screen which is capable of displaying an image at an aspect ratio of 4:3 without giving a sense of incongruity can be realized in a simple arrangement and with lower costs.
  • the present driving method it is also possible to achieve an effect that the design efficiency can be improved and standardization of components used is promoted.
  • a display device having a screen at an aspect ratio of 16:9 is enabled to display images in the wide display mode or in the normal display mode.
  • different images can be displayed on a right half and a left half of the screen, respectively.
  • an image at an aspect ratio of 4:3 is displayed by a display device having a screen at an aspect ratio of 16:9, it is possible to display the image with a shift either to the right side or to the left side, and an image of a black level (corresponding to horizontal flyback periods) is displayed to a space.
  • images giving less sense of incongruity can be displayed, by changing the sampling intervals during one horizontal scanning period at least either so that each interval becomes greater or so that each interval become smaller. For example, by changing the sampling intervals so that each interval becomes smaller from the center to the periphery, images displayed in the wide display mode or in the normal display mode can have a superior roundness in the central part of the screen.
  • a first matrix-type display device includes (1) pixel electrodes provided in matrix, constituting pixel electrode rows provided in a horizontal direction, (2) a signal supplying circuit for sampling an analogue display signal of at least one horizontal scanning period in synchronization with sampling clocks, and supplying the sampled display signal to each pixel electrode row, (3) a selecting circuit for sequentially selecting the pixel electrode rows in a vertical direction so that one pixel electrode row is selected during one horizontal scanning period in order to supply the sampled display signal to the selected pixel electrode row from the signal supplying circuit, and (4) a sampling clock generator for generating sampling clocks, and changing a sampling frequency so that, even during a period while sampling intervals are set substantially equal, the sampling intervals include an unequal discontinuous part.
  • the sampling clock generator generates sampling clocks such that sampling intervals unequal to the others are contained among the sampling intervals equal to each other. Therefore, in the case where a plurality of division ratios are selected so that a proper sampling frequency is obtained per each selection by dividing reference clock with the selected division ratio, division ratios which are switched so as to change the sampling intervals can be set close to each other. As a result, the frequency of the reference clock signal can be set lower. Besides, since it is possible to obtain, from a single reference clock signal, any frequency lower than the frequency of the reference clock signal, there is no need to anew set the frequency of the reference clock signal when the number of the pixels in one screen changes.
  • a matrix-type display device having a laterally long screen which is capable of displaying an image at an aspect ratio of 4:3 without giving a sense of incongruity can be realized in a simple arrangement and with lower costs.
  • the sampling clock generator preferably has the following arrangement. Namely, the sampling clock generator includes (1) a reference clock oscillator for oscillating a reference clock signal having a predetermined constant frequency, (2) a plurality of dividing circuits for dividing the reference clock with respective division ratios and outputting the divided clock as sampling clock, at least one of the dividing circuits being an irregular dividing circuit for outputting a sampling clock including a clock of unequal interval among clocks of equal interval, the clock of unequal interval being different from the clock of equal interval in the interval thereof, (3) a switching control circuit for controlling switching timings for switching the sampling clock in accordance with a horizontal synchronization signal and the reference clock, and (4) a switching circuit for selecting one among the sampling clocks supplied from the dividing circuits and outputting it to the signal supplying circuit, while switching the selection at the switching timings.
  • the dividing circuits can be composed of logical circuits such as counters.
  • the switching control circuit can be also composed of a logical circuit, since it controls switching timings in accordance with the horizontal synchronization signal and the reference clock signal.
  • the switching circuit can be also composed of a logical circuit such as a data selector. Therefore, all the parts of the sampling clock generator except the reference clock oscillator, namely, the dividing circuits, the switching control circuit, and the switching circuit, can be realized with an LSI such as a gate array. Since those circuits can be thus integrated, an analog processing circuit such as an operational amplifier is unnecessary. Therefore, the matrix-type display device can be realized in a simpler arrangement and with lower costs.
  • the irregular dividing circuit outputs a sampling clock in which a plurality of the clocks of unequal interval are dispersed.
  • a sampling clock in which a plurality of the clocks of unequal interval are dispersed.
  • the reference clock oscillator oscillates a reference clock signal having a duty cycle of substantially 50 percent.
  • the minimum interval to determine the timing of the division are made uniform.
  • the designing of clocks becomes easier, thereby ensuring that the unequal intervals are more easily set.
  • the sampling clock generator preferably has a characteristic that a difference of a single cycle between the equal and unequal clocks of the sampling clock signal is 0.5 clock of the reference clock signal, in addition to the characteristic that the reference clock signal has a duty cycle of substantially 50 percent. This ensures that the equal and unequal clocks have a minimum difference therebetween. Therefore, it is possible to obtain substantially uniform sampling intervals. As a result, in images displayed, influences of the unequal clocks are not noticeable, thereby enhancing the display quality.
  • a second matrix-type display device includes (1) pixel electrodes provided in matrix, constituting pixel electrode rows provided in a horizontal direction, (2) a signal supplying circuit for sampling an analogue display signal of at least one horizontal scanning period in synchronization with sampling clocks, and supplying the sampled display signal to each pixel electrode row, (3) a selecting circuit for sequentially selecting the pixel electrode rows in a vertical direction so that one pixel electrode row is selected during one horizontal scanning period, in order to supply the sampled display signal to the selected pixel electrode row from the signal supplying circuit, (4) a plurality of reference clock oscillators for oscillating reference clocks having predetermined frequencies, respectively, (5) a switching control circuit for controlling switching timings for switching the reference clocks in accordance with a horizontal synchronization signal and one of the reference clocks which is to be selected next, so that each of sampling intervals in accordance with the sampling clocks is set not smaller than a minimum sampling interval which allows the signal supplying circuit to carry out proper sampling operations, (6) a
  • a plurality of reference clock signals are switched so that one reference clock signal is selected. Therefore, in the case where the reference clock signals are arranged so as to have frequencies close to each other, a rate of change between sampling clocks becomes lower. Besides, since the switching timings are controlled in accordance with the reference clock signal which is to be selected in the next period, it is possible to synchronize each switching timing with the reference clock signal to be selected as a result of switching by the switching circuit. Furthermore, since the switching timings are controlled so that each sampling interval based on the sampling clocks is not smaller then the minimum sampling interval which allows the signal supplying circuit to carry out proper sampling operations, sampling clocks causing samplings at sampling intervals smaller than the minimum sampling interval are by no means outputted. In addition, as is the case with the first matrix-type display device, the dividing circuit, the switching control circuit, and the switching circuit can be realized with an LSI such as a gate array.
  • a matrix-type display device having a laterally long screen which is capable of displaying even an image at an aspect ratio of 4:3 without giving a sense of incongruity can be realized in a simple arrangement and with lower costs so that it conducts stable sampling operations.
  • the reference clock signal has a duty cycle of substantially 50 percent.
  • a matrix-type display device in accordance with the present embodiment has a pixel array 1, a row electrode driving circuit 2, a column electrode driving circuit 3, and a sampling clock generator 4, as illustrated in Figure 1.
  • the pixel array 1 has a plurality of pixel electrodes 5 provided in matrix (represented as PIX in the figure), and switching elements 6 one of which is connected to each pixel electrode 5.
  • a voltage is applied for driving a display medium which is not shown.
  • the liquid crystal is driven so as to become in an active state or in a non-active state, by applying a voltage across the pixel electrodes 5 and oppositely provided electrodes which are not shown.
  • the switching elements 6 are turned on in response to an ON signal (scanning signal) supplied thereto from the column electrode driving circuit 3 through column electrodes, and supply display data (display signal) from the row electrode driving circuit 2 to the pixel electrodes 5.
  • ON signal scanning signal
  • display data display signal
  • TFT thin film transistor
  • MIM metal insulator metal
  • the row electrode driving circuit 2 as a signal supplying circuit samples a video signal S in supplied thereto by the use of a sampling clock signal CK s supplied from the sampling clock generator 4 (described later), and then, outputs the sampled data as display data S out1 , S out2 , ... to the row electrodes all at once.
  • the column electrode driving circuit 3 as a selecting circuit sequentially outputs the ON signal to the column electrodes, at a ratio of one column electrode per one horizontal scanning period, in response to a horizontal synchronization signal and a vertical synchronization signal.
  • the scanning of the column electrodes in a vertical direction is repeated so that one scanning operation is carried out per one field.
  • a picture in accordance with the video signal is displayed.
  • the sampling clock generator 4 is composed of a reference clock oscillator 7, a frequency dividing unit 8, a switching circuit 9, and a switching control circuit 10.
  • the reference clock oscillator 7 is arranged so as to have a frequency which can be obtained by the use of an oscillator available at stores, and so as to generate a reference clock signal CK g whose duty cycle is about 50 percent and whose frequency is constant.
  • the reference clock oscillator 7 is composed of a crystal oscillator, or a voltage control oscillator (VCO).
  • the frequency dividing unit 8 is composed of a plurality of frequency dividing circuits FD 1 , FD 2 , ....
  • the frequency dividing circuits FD 1 , FD 2 , ... divide the reference clock signal CK g with division ratios of 1/N 1 , 1/N 2 , ..., respectively, and each frequency dividing circuit is composed of a logical circuit including a counter or the like.
  • the switching circuit 9 selects one division clock signal among those outputted from the frequency dividing circuits FD 1 , FD 2 , ..., and supplies it to the row electrode driving circuit 2 as the sampling clock signal CK s .
  • the switching circuit 9 is composed of a logical circuit such as a data selector. The switching circuit 9 switches the division clock signals during one horizontal scanning period in response to a switching control signal generated by the switching control circuit 10.
  • the switching control circuit 10 generates the switching control signal in accordance with the reference clock signal CK g and the horizontal synchronization signal H sync , and is composed of a logical circuit including a counter or the like. To be more specific, the switching control circuit 10 generates the switching control signal in synchronization with the reference clock signal CK g by using the horizontal synchronization signal H sync for setting a reference point for the switching operation, so that the division clock signals are switched at predetermined timings in accordance with the roundness, the aspect ratio, and the display mode.
  • the switching control circuit 10 detects how many clocks or cycles (hereinafter referred to as reference clocks) of the reference clock signal CK g have been counted by the use of a counter since the horizontal synchronization signal H sync was supplied, and outputs the switching timing as the switching control signal when the count reaches a value corresponding to a predetermined switching point.
  • reference clocks clocks or cycles
  • the frequency dividing unit 8 has two frequency dividing circuits FD 1 and FD 2 .
  • the reference clock signal CK g has a frequency f g of 20 MHz, and the division ratios of 1/N 1 and 1/N 2 of the frequency dividing circuits FD 1 and FD 2 are set to 1/5 and 1/5.25, respectively.
  • different sampling frequencies are selected during the horizontal flyback period and the effective display period, respectively (see Figure 13).
  • N 1 and N 2 are determined in the following manner.
  • an integral number n is given, which satisfies that Nxn is a minimum integral number M.
  • the division clock signal CK d1 outputted through the switching circuit 9 is given to the row electrode driving circuit 2 as a sampling clock signal CK s . Then, the row electrode driving circuit 2 samples the video signal at sampling timings indicated by arrows directed upwards in Figure 2(a), that is, sampling timings which correspond rising and falling edges of the sampling clock signal CK g .
  • the division clock signal CK d2 outputted through the switching circuit 9 is given to the row electrode driving circuit 2 as the sampling clock signal CK s . Then, the row electrode driving circuit 2 samples the video signal at sampling timings indicated by arrows directed upwards in Figure 2(b).
  • frequencies of the sampling clock signal obtained by the frequency dividing circuit FD 1 and FD 2 that is, sampling frequencies f s1 and f s2 , are 4 MHz and 3.8095 MHz, respectively. Therefore, a rate of change of the sampling frequencies f s1 and f s2 is substantially 5 percent.
  • each of the second and fourth clocks among the four clocks obtained by dividing the 21 reference clocks, has a width equivalent to five reference clocks.
  • each first half at a high level of the first and third clocks of the division clock signal CK d2 has a width T equivalent to three reference clocks, which is unequal to the others. Therefore, each of the first and third clocks has a total width equivalent to 5.5 reference clocks.
  • the frequency dividing circuit FD 2 functioning as an irregular dividing circuit is arranged so that regarding (1) a clock of the division clock signal CK d2 which substantially corresponds to the first through third reference clocks and (2) a clock of the division clock signal CK d2 which substantially corresponds to the eleventh through fourteenth reference clocks, each of them has a width which is 0.5 reference clock more than the width of the other clocks of the division clock signal CK d2 .
  • the frequency dividing circuit FD 2 causes the output level of the division clock signal CK d2 to change per 2.5 reference clocks among the 21 reference clocks CK g , except for the above-described specific clocks (i.e., clocks of unequal interval) in each of which the output level is changed with a delay equivalent to 0.5 reference clock.
  • the sampling timings are not constant at the clock level, whereas effects of the irregular intervals (unequal intervals) cannot be recognized by human eyes when the video signals (analogue value) are sampled at the sampling interval and display is carried out in accordance with the video signals thus sampled. Therefore, even though the sampling intervals are not equal, the sampling frequency f s2 can be regarded as 3.8095 MHz in average provided that parts whose intervals are unequal to the others are provided as scatteredly as possible, and practically there will be no problem.
  • positions of the clocks whose width is unequal to that of the others may be shifted per field, per horizontal scanning period, or per field and per horizontal scanning period, so that the parts are provided as scatteredly as possible.
  • outputs of the frequency dividing circuits FD 1 and FD 2 also change only at rising and falling edges of the reference clock signal CK g .
  • the frequency dividing circuits FD 1 and FD 2 can change the outputs thereof only at intervals whose unit is 0.5 reference clock.
  • the frequency dividing circuit FD 2 outputs the division clock signal CK d2 which changes per 2.5 clocks or 3 reference clocks though its division ratio is set to 1/5.25.
  • the division clock signal CK d2 has irregular cycles, thereby enabling to lower the value of N and allow the frequency f g to be set to a practical value. Therefore, the reference clock oscillator 7 is allowed to be composed of parts available at stores. Besides, since the frequency f g is set to a lower value, unnecessary radiation can be greatly reduced.
  • the division clock signal CK d2 obtained by the frequency dividing method of the present embodiment have unequal discontinuous parts which are different from the other parts by 0.5 clock of the reference clock CK g . Therefore, the condition that N must be an integral number can be negated. As a result, any sampling clock signal CK s having a frequency not higher than the frequency f g can be obtained.
  • a difference between a cycle T 1 of an irregular clock and a cycle T 2 of a regular clock of the sampling clock signal CK s is equivalent to 0.5 reference clock, which is smallest possible. Therefore, the sampling clock signal CK s can be considered to have an averaged frequency, even though the sampling clock signal CK s contains irregular clocks having a cycle unequal to that of the others. Therefore, in images displayed by the use of the sampling clock signal CK s , the effects of the irregular clocks are not noticeable, thereby giving substantially no sense of incongruity to the user.
  • each of all the parts of the sampling clock generator 4 except for the reference clock oscillator 7 is composed of a logical circuit.
  • each of the frequency dividing unit 8, the switching circuit 9, and the switching control circuit 10 of the sampling clock generator 4 is composed of a logical circuit. Therefore, these circuits can be realized with an LSI such as a gate array, thereby ensuring that the driving system including the sampling clock generator 4 can be simplified and that the costs thereof can be lowered.
  • the switching control circuit 10 is arranged so as to have a plurality of structures which respectively generate different switching control signals, and to switch the structures in response to an n'th (within one vertical scanning period) horizontal synchronization signal, in response to which the frequency of the sampling clock signal CK s is switched.
  • a structure having two frequency dividing circuits FD 1 and FD 2 is discussed as an embodiment of the present invention, but the same effect described above can be obtained in the case where a display device has a structure wherein not less than three frequency dividing circuits FD 1 , FD 2 , ... are provided.
  • a division clock signal CK d3 is obtained by setting a division ratio of the frequency dividing circuit FD 3 to 1/4.75, as illustrated in Figure 4.
  • the division clock signal CK d3 has a frequency of 4.2 MHz and has four clocks which are obtained by frequency division with respect to 19 reference clocks.
  • Each of a first half of the first clock and a first half of the third clock of the division clock signal CK d3 also has a width T 2 which is unequal to that of the other first and latter halves of the clocks, as is the case with the division clock CK 2 .
  • the frequency dividing circuit FD 3 causes the output level of the division clock signal CK d3 to change per 2.5 reference clocks, except for the following specific clocks in each of which the output level change is advanced by 0.5 reference clock, namely, (1) a clock corresponding to the first and second reference clocks and (2) a clock substantially corresponding to the tenth through twelfth reference clocks.
  • the division ratio is switched, from the left to the center of the screen, from 1/4.75, to 1/5, and then, to 1/5.25, and from the center to the right side of the screen, from 1/5.25, to 1/5, and then, to 1/4.75.
  • a display suitable for the wide display mode can be realized.
  • a matrix-type display device has a pixel array 1, a row electrode driving circuit 2, a column electrode driving circuit 3, and a sampling clock oscillating unit 11, as illustrated in Figure 6.
  • the sampling clock oscillating unit 11 is composed of a reference clock oscillating section 12, a switching circuit 13, a switching control circuit 14, and dividing circuit 15.
  • the reference clock oscillating section 12 is composed of a plurality of reference clock oscillators RG 1 , RG 2 , ...
  • the reference clock oscillators RG 1 , RG 2 , ... are the same as the reference clock oscillator 7 of the first embodiment, and are arranged so as to generate reference clock signals.
  • CK g1 , CK g2 , ... having different frequencies, respectively.
  • Each frequency of the reference clock signals CK g1 , CK g2 , ... is constant and has a duty cycle of around 50 percent.
  • the switching circuit 13 for selecting one among the reference clock signals CK g1 , CK g2 , ... outputted from the reference clock oscillators RG 1 , RG 2 , ... and outputting the selected one, is composed of a logical circuit such as a data selector.
  • the switching circuit 13 switches the reference clock signals CK g1 , CK g2 , ... in response to a switching control signal generated by the switching control circuit 14.
  • the switching control circuit 14 for outputting a switching control signal in accordance with an external clock signal CK, a horizontal synchronization signal H sync , and the reference clock signals CK g1 , CK g2 , ..., is composed of a logical circuit including a counter or the like. To be more specific, the switching control circuit 14 is arranged so as to generate the switching control signal having a desired switching timing in accordance with the roundness, the aspect ratio, and the display mode, by using the horizontal synchronization signal H sync for setting a reference point for switching operations. So as to determine switching timings, the switching control circuit 14 refers to a reference clock signal (hereinafter referred to as switching timing determining signal) to be switched by the switching circuit 13.
  • switching timing determining signal a reference clock signal
  • Switching timings are determined, using the count number of clocks of the external clock signal CK from the horizontal synchronization signal H sync , so that the sampling clock signal CK s ensures a minimum sampling interval which allows the row electrode driving circuit 2 to carry out proper sampling operations.
  • each timing for switching the reference clock signals which after their division are outputted as the sampling clock signal CK s that a reference clock signal is switched to another reference clock signal having a different frequency when the last cycle of the former clock signal is completed, so that during each period between two switching points the cycle of the sampling clock signal CK s is constant.
  • the frequency dividing circuit 15 divides one reference clock signal CK g outputted from the switching circuit 13 by a predetermined division ratio 1/N, and outputs the divided result to the row electrode driving circuit 2 as the sampling clock CK s .
  • the frequency dividing circuit 15 is composed of a logical circuit including a counter or the like.
  • Figure 7 corresponds, for example, to a left half of the screen in the wide display mode.
  • the reference clock oscillating section 12 has three reference clock oscillators RG 1 , RG 2 , and RG 3 is discussed.
  • the reference clock signals CK g1 , CK g2 , and CK g3 have frequencies f g1 , f g2 , and f g3 , respectively, which satisfy f g1 >f g2 >f g3 .
  • the division ratio of the frequency dividing circuit 15 is set to 1/5.
  • the sampling frequencies are switched so that the roundness in the center of the screen is improved as compared with the roundness of the peripheral parts of the screen (see Figure 12).
  • the reference clock signal CK g2 of the reference clock oscillator RG 2 is outputted through the switching circuit 13 as the reference clock signal CK g , it is divided by the frequency dividing circuit 15, thereby becoming the sampling clock signal CK s (sampling frequency f s2 ).
  • the sampling clock CK s (sampling frequency f s3 ) is obtained by the use of the switching circuit 13 and the frequency dividing circuit 15. The switching from the reference clock signal CK g3 to another reference clock signal CK g1 or CK g2 is carried out in the same manner.
  • the sampling timings are also switched.
  • the switching timings of the switching circuit 13 are determined so that the sampling clock signal CK s ensures a minimum sampling interval which allows the row electrode driving circuit 2 to carry out proper sampling operations. Therefore, in the case where a half cycle of the reference clock signal CK g1 shown in Figure 7 is equivalent to the minimum sampling interval, the sampling interval by no means becomes smaller than the minimum sampling interval, thereby ensuring suitable sampling operations.
  • the external clock signal CK is supplied from outside, but an equivalent clock signal may be obtained inside the sampling clock generator 4 in the case of the first embodiment and inside the sampling clock oscillating unit 11 in the case of the second example.

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  • Details Of Television Scanning (AREA)

Claims (12)

  1. Verfahren zum Ansteuern einer matrixartigen Anzeigevorrichtung, die Pixelelemente besitzt, die in einer horizontalen Richtung in Zeilen und in einer vertikalen Richtung in Spalten ausgerichtet sind, wobei das Verfahren die folgenden Schritte enthält:
    Abtasten eines analogen Anzeigesignals in wenigstens einer horizontalen Abtastperiode synchron mit einem Referenztaktsignal (CKg);
    nacheinander Auswählen von Zeilen von Pixelelementen in einer vertikalen Richtung, wobei jede Zeile von Pixelelementen während einer horizontalen Abtastperiode ausgewählt wird; und
    Liefern des abgetasteten analogen Anzeigesignals an die Pixelelemente der ausgewählten Zeile,
    wobei das Verfahren ferner die folgenden Schritte enthält:
    Ausführen der Abtastung durch Definieren wenigstens einer ersten und einer zweiten Unterperiode in der horizontalen Abtastperiode, wobei die erste Unterperiode eine erste durchschnittliche Abtastfrequenz (fs1) besitzt und die zweite Unterperiode eine zweite durchschnittliche Abtastfrequenz (fs2), die von der ersten durchschnittlichen Abtastfrequenz verschieden ist, besitzt;
    wobei sich die Länge des Abtastintervalls wenigstens in einer Unterperiode ändert, um so wenigstens ein erstes Abtastintervall (T) und ein zweites Abtastintervall in der einen Unterperiode zu schaffen, wobei das erste Abtastintervall eine andere Länge als das zweite Abtastintervall hat;
    und wobei zwischen zwei aufeinander folgenden Auftritten des ersten Abtastintervalls (T) das zweite Abtastintervall wenigstens einmal auftritt.
  2. Verfahren nach Anspruch 1, bei dem während einer horizontalen Abtastperiode die Länge der Abtasdntervalle in Bezug auf einen Punkt, der einem Zentrum eines Bildes entspricht, im Wesentlichen symmetrisch geändert wird.
  3. Verfahren nach Anspruch 1, bei dem während einer horizontalen Abtastperiode die Länge der Abtastintervalle in Bezug auf einen Punkt, der einem Zentrum eines Bildes entspricht, asymmetrisch geändert wird.
  4. Verfahren nach Anspruch 3, bei dem während einer horizontalen Abtastperiode die Länge der Abtastintervalle wenigstens so geändert wird, dass sie größer wird, oder so geändert wird, dass sie kleiner wird.
  5. Verfahren nach einem der Ansprüche 1 bis 4, bei dem die Länge des ersten Abtastintervalls (T) ein nicht ganzzahliges Vielfaches der Länge des zweiten Abtastintervalls ist.
  6. Verfahren nach einem der Ansprüche 1 bis 4, bei dem die Länge des zweiten Abtastintervalls ein nicht ganzzahliges Vielfaches der Periode des Referenztaktsignals (CKg) ist.
  7. Verfahren nach einem der Ansprüche 1 bis 4, bei dem sich die Länge des ersten Abtastintervalls (T) und die Länge des zweiten Abtastintervalls um einen halben Zyklus des Referenztaktsignals (CKg) unterscheiden.
  8. Matrixartige Anzeigevorrichtung, die Pixelelemente aufweist, die in einer horizontalen Richtung in Zeilen und in einer vertikalen Richtung in Spalten ausgerichtet sind, mit
    Auswahlmitteln (3), die während einer horizontalen Abtastperiode nacheinander eine Pixelelehtroden-Zeile in einer vertikalen Richtung auswählen; und
    Signalversorgungsmitteln (2), die in wenigstens einer horizontalen Abtastperiode ein analoges Anzeigesignal synchron mit einem Referenztaktsignal (CKg) abtasten und das abgetastete analoge Anzeigesignal an die Pixelelektroden-Zeile liefern;
    wobei die Anzeigevorrichtung dadurch gekennzeichnet ist, dass sie ferner enthält:
    Mittel zum Ausführen der Abtastung durch Definieren wenigstens einer ersten und einer zweiten Unterperiode in einer horizontalen Abtastperiode, wobei die erste Unterperiode eine erste durchschnittliche Abtastfrequenz (fs1) besitzt und die zweite Unterperiode eine zweite durchschnittliche Abtastfrequenz (fs2) die von der ersten durchschnittlichen Abtastfrequenz verschieden ist, besitzt;
    wobei sich das Abtastintervall in wenigstens einer Unterperiode ändert, um so wenigstens ein erstes Abtastintervall (T) und ein zweites Abtastintervall in der einen Unterperiode zu schaffen, wobei das erste Abtastintervall eine andere Länge als das zweite Abtastintervall hat;
    und wobei zwischen zwei aufeinander folgenden Auftritten des ersten Abtastintervalls (T) das zweite Abtastintervall wenigstens einmal auftritt.
  9. Matrixartige Vorrichtung nach Anspruch 8, bei der der Referenztakt ein Tastverhältnis von im Wesentlichen 50 Prozent hat.
  10. Matrixartige Anzeigevorrichtung nach Anspruch 8 oder 9, dadurch gekennzeichnet, dass sie eine Flüssigkristallanzeigevorrichtung ist.
  11. Matrixartige Anzeigevorrichtung nach Anspruch 8, 9 oder 10, bei der jede Pixelelektrode mit einem Schaltelement (6) versehen ist.
  12. Matrixartige Anzeigevorrichtung nach einem der Ansprüche 8 bis 11, die ferner einen Anzeigeschirm mit einem Seitenverhältnis im Bereich von 4:3 bis 16:9 besitzt.
EP97301749A 1996-03-22 1997-03-14 Matrixanzeigevorrichtung und Verfahren zu ihrer Ansteuerung Expired - Lifetime EP0797183B1 (de)

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JP06693396A JP3330812B2 (ja) 1996-03-22 1996-03-22 マトリックス型表示装置およびその駆動方法
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DE69736535T2 (de) 2007-09-13
DE69736535D1 (de) 2006-10-05
JP3330812B2 (ja) 2002-09-30

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