EP0775370A1 - Procede de fabrication d'un condensateur au silicium - Google Patents

Procede de fabrication d'un condensateur au silicium

Info

Publication number
EP0775370A1
EP0775370A1 EP95927642A EP95927642A EP0775370A1 EP 0775370 A1 EP0775370 A1 EP 0775370A1 EP 95927642 A EP95927642 A EP 95927642A EP 95927642 A EP95927642 A EP 95927642A EP 0775370 A1 EP0775370 A1 EP 0775370A1
Authority
EP
European Patent Office
Prior art keywords
germanium
layer
doped
silicon
hole openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95927642A
Other languages
German (de)
English (en)
Inventor
Josef Willer
Hermann Wendt
Herbert Schäfer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0775370A1 publication Critical patent/EP0775370A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation

Definitions

  • a silicon capacitor is known from European patent application EP 05 28 281.
  • This comprises an n-doped silicon substrate, the surface of which is structured in a characteristic manner by electrochemical etching in a fluoride-containing, acidic electrolyte in which the substrate is connected as an anode.
  • electrochemical etching hole structures are more or less regularly arranged on the surface of the substrate.
  • the hole structures have an aspect ratio in the range of 1: 1000.
  • the surface of the hole structures is provided with a dielectric layer and a conductive layer.
  • Conductive layer, dielectric layer and silicon substrate form a capacitor in which specific capacities of up to 100 ⁇ FV / mm ⁇ are achieved due to the surface enlargement caused by the hole structures.
  • it is proposed to provide an n + -doped region on the surface of the hole structures.
  • Silicon capacitors are usually manufactured in silicon wafers. A bending of the silicon wafers is ascertained, which is associated with mechanical stresses by the n + -doped region on the surface of the hole structures, which are up to 300 ⁇ m deep. This bending of the silicon wafer leads to problems in further process steps, such as lithography, wafer thinning and separation, which are necessary for installing the silicon capacitor in a housing.
  • the invention is based on the problem of specifying a further method for producing a silicon capacitor, in which bending of the silicon substrate is avoided and which can be used in a production process.
  • a multiplicity of hole openings are produced in a main surface of an n-doped silicon substrate by electrochemical etching.
  • the electrochemical etching is preferably carried out in a fluoride-containing, acidic electrolyte with which the main surface is in contact and between which and the silicon substrate a voltage is applied such that the silicon substrate is connected as an anode. A back of the silicon substrate opposite the main surface is illuminated.
  • a conductive region is created along the surface of the hole openings and is provided with electrically active dopant.
  • This is used as an electrically active dopant Context called dopant, which determines the conductivity of the conductive area.
  • dopant which determines the conductivity of the conductive area.
  • phosphorus, boron or arsenic is used as the electrically active doping substance.
  • a layer doped with germanium is produced on the surface of the hole openings, through which the conductive region is doped with germanium.
  • the conductive region is produced by diffusing germanium out of a layer doped with germanium.
  • germanium diffuses to a depth of 0.2 to 0.5 ⁇ m in 4 to 25 hours.
  • a diffusion length of 0.2 ⁇ m is achieved after 0.56 hours and a diffusion length of 0.5 ⁇ m after 3.5 hours.
  • Such diffusion times are justifiable in a manufacturing process.
  • the germanium-doped layer is preferably formed from silicate glass, which is deposited in a CVD deposition at atmospheric pressure (APCVD) using a process gas containing Ge (OCH3) 4 and Si (0C2H5) 4 .
  • SiO2 a process gas containing Ge (OCH3) 4 and Si (0C2H5) 4 .
  • Silicon glass doped with germanium and produced using these process gases and O3 is known from S. Fisher et al., Solid State Technology, Sept. 1993, pages 55 to 64. It has been proposed as an intermediate oxide. The possibility of using it as a diffusion source for germanium is not known from the literature.
  • O2 or O3 is added during the deposition. The use of O2 means process simplification. When using O3, an improved edge coverage is achieved.
  • germanium and the electrically active dopant are simultaneously diffuse into the surface of the hole openings in order to produce the conductive region.
  • the diffusion length of the electrically active dopant is greater than that of germanium
  • the electrically active dopant can also be introduced by gas phase diffusion.
  • the germanium diffusion and the diffusion of the electrically active dopant several times.
  • the layers used as the dopant source are removed and applied again.
  • the layer doped with germanium is removed before a dielectric layer is applied to the surface of the conductive region and an electrically conductive layer is applied thereon.
  • the conductive layer and the conductive region are each provided with a contact.
  • the contacts can be arranged in the area of the main surface as well as on the main surface and the back.
  • a silicon layer doped with geranium is grown on the surface of the hole openings by epitaxy.
  • a germanium-containing compound in particular GeH4
  • the layer doped with germanium is preferably grown to a thickness between 10 and 100 nm.
  • the electrically active dopant is then by gas phase diffusion or outdiffusion from one with the introduced electrically active dopant layer.
  • the conductive area is formed in the silicon layer grown in the epitaxy and the adjacent surface of the hole openings. The temperature and time for the diffusion of the electrically active dopant are chosen so that the diverging germanium profile is made to coincide with the profile of the electrically active dopant.
  • the electrically active dopant is built into the lattice during the epitaxy.
  • germanium and the electrically active dopant it is advantageous to epitaxially deposit another undoped silicon layer on the germanium-doped silicon layer before the electrically active dopant is driven in.
  • the germanium-doped silicon layer and possibly the further silicon layer, which have been grown by epitaxy remain as part of the conductive region on the surface of the hole openings.
  • the dielectric layer and the conductive layer are then applied to the surface of the conductive region.
  • the germanium doping in the method according to the invention is intended to compensate for the mechanical stress in the conductive region caused by the doping with the electrically active dopant. Since the depth of the hole openings is up to 300 ⁇ m and the total thickness of silicon wafers conventionally used is around 600 ⁇ m, the mechanical bracing in the conductive area is associated with a noticeable bending of the wafer.
  • the mechanical stresses are caused by the fact that the doping an electrically active dopant atom is installed at a substitutional lattice site in the silicon crystal, the covalent bond radius of which differs from that of the silicon atom.
  • a phosphorus atom in the silicon crystal for example, has a 6 percent smaller covalent bond radius than a corresponding silicon atom, so that it causes a contraction of the crystal lattice. The higher the dopant concentration, the stronger this effect.
  • Lattice distortion can lead to a high dislocation density. If a large number of silicon capacitors are produced in a silicon wafer, the wafer is bent. Since commonly used production systems, such as conventional lithography devices, are designed exclusively for flat substrates, it is in the
  • the disruption of the lattice by the electrically active dopants is compensated for by additional doping with germanium.
  • the dopant concentrations are adjusted to one another so that bending is avoided.
  • a germanium concentration of 8 x 10 20 cm” 3 is required.
  • a concentration of germanium of approximately 1.2 x 10 20 cm" 3 is sufficient.
  • Germanium has the advantage that on the one hand it is electrically neutral, on the other hand it has a high solubility in silicon and that it has a larger covalent bond radius in the silicon crystal than the electrically active dopants boron and phosphorus commonly used for the production of silicon components.
  • Figure 1 shows a silicon substrate with hole openings.
  • FIG. 2 shows the silicon substrate after application of a germanium-doped layer and diffusion of germania.
  • FIG. 3 shows the silicon substrate after application of a layer doped with an electrically active dopant and outdiffusion of this dopant.
  • FIG. 4 shows the silicon substrate after deposition of a dielectric layer and a conductive layer and formation of contacts to the conductive layer and the conductive region.
  • FIG. 5 shows a silicon substrate with hole openings, on the surface of which a germanium-doped silicon layer has been grown.
  • FIG. 6 shows the silicon substrate after growth of a further, undoped silicon layer and driving in of electrically active dopant to form a conductive region.
  • FIG. 7 shows the silicon substrate after depositing a dielectric layer and a conductive layer.
  • the main surface 11 is brought into contact with an electrolyte.
  • an electrolyte For example, 6% by weight hydrofluoric acid (HF) is used as the electrolyte.
  • the silicon substrate 1 is acted on as a anode with a potential of 3 volts.
  • the silicon substrate 1 is illuminated from a rear side 12 opposite the main surface 11.
  • a current density of 10 mA / cm 2 is set.
  • minority charge carriers in the n-doped silicon move to the main surface 11 which is in contact with the electrolyte.
  • a space charge zone forms on the main surface 11. Since the field strength in the area of depressions in the main surface 11 is greater than outside of it, the minority charge carriers preferably move to these points. This leads to a structuring of the main surface 11. The deeper an initially small unevenness becomes due to the etching, the more minority charge carriers move there and the stronger the etching attack at this point.
  • the hole openings 2 begin to grow from unevenness in the main surface 11, which are present in each surface with a statistical distribution.
  • These unevenness can be produced, for example, using conventional photolithography.
  • the hole openings 2 After approximately 180 minutes of etching time, the hole openings 2 have a diameter of 2 ⁇ m at a depth of 175 ⁇ m. Then the silicon substrate 1 is rinsed thoroughly with water.
  • a layer 3 doped with germanium is deposited.
  • the layer 3 doped with germanium is produced from a doped silicon glass using a process gas containing Si (0C2H5)., Ge (OCH3) 4 and O3. Atmospheric pressure and a temperature in the range from 300 ° C to 500 ° C are set.
  • the layer 3 doped with germanium is deposited in a thickness of 100 nm to 300 nm (see FIG. 2).
  • a germanium-doped region 4 is generated in a diffusion time of 25 h.
  • a layer 5 doped with an electrically active dopant is subsequently deposited onto the layer 3 doped with germanium in a CVD method (see FIG. 3). Boron or phosphorus, for example, is used as the electrically active dopant.
  • the doped layer 5 is deposited in a thickness of, for example, 100 nm.
  • the electrically active dopant and the germanium are driven in further together. After a diffusion time of 2.5 h, the dopant profiles of germanium and the electrically active dopant overlap and form a conductive region 40. It takes about 9 hours for boron.
  • the conductive region 40 there is a dopant concentration of 1.1 x 10 20 cm “ 3 boron and 8 x 10 20 cm -3 germanium or 1 x 10 20 cm” 3 phosphorus and 1.2 x 10 20 cm “3 germanium
  • Sufficient conductivity of the doped region 40, which forms a capacitor electrode in the silicon capacitor is achieved on the one hand, and bending of the silicon substrate 1 is effectively avoided, on the other hand, and the depth of the conductive region 40 is, for example, 0.5 ⁇ m .
  • the layer 3 doped with germanium and the doped layer 5 are removed with 10% strength hydrofluoric acid.
  • a dielectric layer 6 and a conductive layer 7 are then applied and structured (see FIG. 4).
  • the dielectric layer 6 is preferably formed by combined production of SiO 2 and Si 3 4 as a multiple layer with a layer sequence SiO 2 Si3 4 SiO 2, since this material has a defect density which is sufficiently low for a large-area capacitor.
  • the conductive layer 7 is formed, for example, from n + -doped polysilicon.
  • a first contact 8 is applied to the surface of the conductive layer 7 and a second contact 9 is applied to the surface of the doped region 40 exposed by the structuring of the dielectric layer 6 and conductive layer 7.
  • the first contact 8 and the second contact 9 are formed, for example, from aluminum.
  • hole openings 2 ' are formed in a main surface 11' of a silicon substrate 1 ', as described with reference to FIG. 1 (see FIG. 5).
  • the specific resistance of the silicon substrate 1 'and the dimensions of the hole openings 2' correspond to those described with reference to FIG. 1.
  • a germanium-doped silicon layer 3 ' which has a thickness of 10 to 100 nm, is grown on the surface of the hole openings 2' in an epitaxial reactor.
  • Epitaxy takes place using SiH2Cl2, GeH4 and inert carrier gases at a temperature of 575 ° C and a pressure of 66.7 Pa (0.5 Torr).
  • the mixing ratio of SiH2Cl2 and GeH4 is adjusted so that the germanium-doped layer contains 2 '10 atomic percent germanium.
  • an undoped silicon layer 4 ' is then grown in the epitaxy reactor to a thickness of, for example, 20 nm (see FIG. 6).
  • a temperature of 650 ° C and a pressure of 66.7 Pa (0.5 Torr) are maintained in the epitaxial reactor.
  • electrically active dopant for example boron or phosphorus
  • electrically active dopant for example boron or phosphorus
  • This is done, for example, by gas phase diffusion using phosphine or borane.
  • a temperature of 1400 K is maintained.
  • the diffusion of the electrically active dopant causes the germanium profile to diverge in the germanium-doped silicon layer 3 '.
  • Germanium diffuses both into the undoped silicon layer 4 'and into the adjacent surface of the silicon substrate 1'.
  • the diffusion temperature and time are set so that the electrically active dopant diffuses into the silicon substrate 1 'just as far as the germanium.
  • a doped region 5 ' is formed on the surface of the hole openings.
  • the dopant profiles of the germanium and the electrically active dopant extend over the undoped silicon layer 4 ', the germanium-doped silicon layer 3' and the doped region 5 ', which together form a conductive region 40'.
  • the electrically active dopant can also be diffused in by separating an appropriately doped silicate glass layer and diffusing it out of the silicate glass layer, which has to be removed again after the diffusion out.
  • the silicon capacitor is finished by depositing a dielectric layer 6 ', for example of SiO 2 / Si 3 4 / SiO 2, and a conductive layer 7' of, for example, n + -doped polysilicon (see FIG. 7).
  • the conductive Layer 7 'and the conductive region 40' are then provided with metallic contacts (not shown).
  • the contacts can both be arranged in the area of the main surface 11 ', a corresponding structuring of the dielectric layer 6' and the conductive layer 7 'being necessary.
  • a contact can be arranged in the region of the main surface on the conductive layer and a contact on a rear side opposite the main surface 11 '.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un condensateur au silicium consistant à réaliser des trous dans un substrat de silicium dopé n (1), puis à créer une zone conductrice (40) par dopage à la surface des trous, cette surface étant ensuite pourvue d'une couche diélectrique (6) et d'une couche conductrice (7). Afin de compenser les contraintes mécaniques dans le substrat de silicium, dues au dopage de la zone conductrice (40), la zone conductrice (40) est dopée en outre au germanium qui diffuse d'une couche dopée au germanium.
EP95927642A 1994-08-09 1995-08-07 Procede de fabrication d'un condensateur au silicium Withdrawn EP0775370A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4428195 1994-08-09
DE4428195A DE4428195C1 (de) 1994-08-09 1994-08-09 Verfahren zur Herstellung eines Siliziumkondensators
PCT/DE1995/001036 WO1996005620A1 (fr) 1994-08-09 1995-08-07 Procede de fabrication d'un condensateur au silicium

Publications (1)

Publication Number Publication Date
EP0775370A1 true EP0775370A1 (fr) 1997-05-28

Family

ID=6525268

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95927642A Withdrawn EP0775370A1 (fr) 1994-08-09 1995-08-07 Procede de fabrication d'un condensateur au silicium

Country Status (7)

Country Link
US (1) US5866452A (fr)
EP (1) EP0775370A1 (fr)
JP (1) JPH10503886A (fr)
KR (1) KR970705174A (fr)
DE (1) DE4428195C1 (fr)
FI (1) FI970543A0 (fr)
WO (1) WO1996005620A1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19701935C1 (de) * 1997-01-21 1997-12-11 Siemens Ag Verfahren zur Herstellung eines Siliziumkondensators
DE19713052A1 (de) * 1997-03-27 1998-10-01 Siemens Ag Kondensatorstruktur
US6100132A (en) * 1997-06-30 2000-08-08 Kabushiki Kaisha Toshiba Method of deforming a trench by a thermal treatment
US6384466B1 (en) * 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
DE10120053A1 (de) 2001-04-24 2002-11-14 Infineon Technologies Ag Stressreduziertes Schichtsystem
US6797992B2 (en) * 2001-08-07 2004-09-28 Fabtech, Inc. Apparatus and method for fabricating a high reverse voltage semiconductor device
DE10158798A1 (de) 2001-11-30 2003-06-18 Infineon Technologies Ag Kondensator und Verfahren zum Herstellen eines Kondensators
DE10162900C1 (de) * 2001-12-20 2003-07-31 Infineon Technologies Ag Verfahren zur Herstellung niederohmiger Elektroden in Grabenkondensatoren
US6984860B2 (en) * 2002-11-27 2006-01-10 Semiconductor Components Industries, L.L.C. Semiconductor device with high frequency parallel plate trench capacitor structure
DE102005030638A1 (de) * 2005-06-30 2007-01-11 Infineon Technologies Ag Halbleiterschaltungsanordnung und Verfahren zu deren Herstellung
US8558964B2 (en) * 2007-02-15 2013-10-15 Baxter International Inc. Dialysis system having display with electromagnetic compliance (“EMC”) seal
US7670931B2 (en) * 2007-05-15 2010-03-02 Novellus Systems, Inc. Methods for fabricating semiconductor structures with backside stress layers
US8742541B2 (en) * 2010-12-09 2014-06-03 Tessera, Inc. High density three-dimensional integrated capacitors
US8502340B2 (en) 2010-12-09 2013-08-06 Tessera, Inc. High density three-dimensional integrated capacitors
US8487405B2 (en) 2011-02-17 2013-07-16 Maxim Integrated Products, Inc. Deep trench capacitor with conformally-deposited conductive layers having compressive stress
US8592883B2 (en) * 2011-09-15 2013-11-26 Infineon Technologies Ag Semiconductor structure and method for making same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4889492A (en) * 1986-05-07 1989-12-26 Motorola, Inc. High capacitance trench capacitor and well extension process
US4782036A (en) * 1986-08-29 1988-11-01 Siemens Aktiengesellschaft Process for producing a predetermined doping in side walls and bases of trenches etched into semiconductor substrates
US5354710A (en) * 1988-01-14 1994-10-11 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices using an adsorption enhancement layer
RU2082258C1 (ru) * 1991-08-14 1997-06-20 Сименс АГ Схемная структура с по меньшей мере одним конденсатором и способ ее изготовления
DE4418430C1 (de) * 1994-05-26 1995-05-11 Siemens Ag Verfahren zur Herstellung eines Siliziumkondensators

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9605620A1 *

Also Published As

Publication number Publication date
KR970705174A (ko) 1997-09-06
WO1996005620A1 (fr) 1996-02-22
FI970543A (fi) 1997-02-07
FI970543A0 (fi) 1997-02-07
JPH10503886A (ja) 1998-04-07
US5866452A (en) 1999-02-02
DE4428195C1 (de) 1995-04-20

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