EP0756371A2 - Dispositif convertisseur avec pilotage de courant par modulation de largeur d'impulsion générant des signaux de pilotage périodiques - Google Patents

Dispositif convertisseur avec pilotage de courant par modulation de largeur d'impulsion générant des signaux de pilotage périodiques Download PDF

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Publication number
EP0756371A2
EP0756371A2 EP96111425A EP96111425A EP0756371A2 EP 0756371 A2 EP0756371 A2 EP 0756371A2 EP 96111425 A EP96111425 A EP 96111425A EP 96111425 A EP96111425 A EP 96111425A EP 0756371 A2 EP0756371 A2 EP 0756371A2
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EP
European Patent Office
Prior art keywords
level
line current
main circuit
outputs
timing
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EP96111425A
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German (de)
English (en)
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EP0756371B1 (fr
EP0756371A3 (fr
Inventor
Kazuyuki Takada
Yoshinori Isomura
Toshiki Tsubouchi
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P2205/00—Indexing scheme relating to controlling arrangements characterised by the control loops
    • H02P2205/01—Current loop, i.e. comparison of the motor current with a current reference
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • the present invention relates to a current command type PWM (Pulse Width Modulation) inverter apparatus for driving and controlling a three-phase motor, and in particular, to a current command type PWM (Pulse Width Modulation) inverter apparatus comprising a logic circuit for generating switching command signals at periodical timings.
  • PWM Pulse Width Modulation
  • the current command type PWM inverter which commands a current to be flown into a motor and compulsorily flows the current conforming to the command through the motor, is advantageous in responsibility and controllability.
  • the current command type PWM inverter is adopted in almost all the cases.
  • a fundamental frequency f and an effective current value ip of a three-phase AC (Alternating Current) current waveform to be supplied to a three-phase motor 1 are set in a current command generator 7, and based on these information, the current command generator 7 internally generates current command signals to be flown into the three-phase motor 1, and the generated command signals as a first line current command signal iTU, a second line current command signal iTV and a third line current command signal iTW.
  • a motor current detector circuit 9 detects two line currents of the three-phase motor 1, obtains the remaining one line current by obtaining the sum of the detected two line currents and inverting the sign of the sum value, and outputs the resulting detected currents as a first detected line current iFU, a second detected line current iFV and a third detected line current iFW. It is to be noted that the motor current detector circuit 9 may detect the three line currents of the three-phase motor 1, and then output the first detected line current iFU, the second detected line current iFV and the third detected line current iFW.
  • a current controller 106 receives the first line current command signal iTU, the second line current command signal iTV, the third line current command signal iTW, the first detected line current iFU, the second detected line current iFV and the third detected line current iFW, and generates a first switching command signal PU, a second switching command signal PV and a third switching command signal PW so that the first line current command signal iTU, the second line current command signal iTV and the third line current command signal iTW are made to respectively coincide with the first detected line current iFU, the second detected line current iFV and the third detected line current iFW as far as possible.
  • a main circuit power controller 8 comprises:
  • the main circuit power device circuit 2 operates to turn on either the first main circuit switching power device Q1 or the fourth main circuit switching power device Q4 in accordance with the first switching command signal PU, turn on either the second main circuit switching power device Q2 or the fifth main circuit switching power device Q5 in accordance with the second switching command signal PV, and turn on either the third main circuit switching power device Q3 or the sixth main circuit switching power device Q6 in accordance with the third switching command signal PW.
  • the first switching command signal PU becomes a High level (referred to as an H-level hereinafter)
  • the first main circuit switching power device Q1 is turned on.
  • the first switching command signal PU becomes a Low level (referred to as an L-level hereinafter)
  • the fourth main circuit switching power device Q4 is turned on.
  • the second switching command signal PV becomes the H-level
  • the second main circuit switching power device Q2 is turned on.
  • the fifth main circuit switching power device Q5 is turned on.
  • the third switching command signal PW becomes the H-level
  • the third main circuit switching power device Q3 is turned on.
  • the sixth main circuit switching power device Q6 is turned on.
  • Fig. 12 shows a structure of the prior art current controller 106 of the current command type PWM inverter system shown in Fig. 11.
  • Figs. 13A through 13E show an operation of the inverter system shown in Fig. 12.
  • first, second and third line current command signals iTU, iTV and iTW and the first, second and third detected line currents iFU, iFV and iFW are subjected to a subtraction process respectively in subtracters 117, 118 and 119 to obtain the first, second and third line current error signals iEU, iEV and iEW.
  • first, second and third current error amplifiers 120, 121 and 122 receive the respective first, second and third line current error signals iEU, iEV and iEW, respectively, and then, output amplified voltage command signals VU, VV and VW, respectively.
  • Each of the current error amplifiers 120, 121 and 122 is generally implemented by a proportion and integration type amplifier as shown in Fig.
  • G(s) R2 ⁇ (R3 ⁇ C1 ⁇ s) / [R1 ⁇ ⁇ (R2 + R3) ⁇ C1 ⁇ s + 1]
  • s j ⁇ is a variable of Laplacian conversion.
  • the reference numeral 139 denotes a three-phase PWM signal generator comprised of first, second and third comparators 123, 124 and 125 and a triangular wave generator 126.
  • the first, second and third comparators 123, 124 and 125 compare a triangular wave signal SC outputted from the triangular wave generator 126 with the respective voltage command signals VU, VV and VW, respectively, and then, output the first, second and third switching command signals PU, PV and PW, respectively.
  • each of the first, second and third comparators 123, 124 and 125 outputs the H-level when each of the voltage command signals VU, VV and VW is greater than the triangular wave signal SC, while each of the first, second and third comparators 123, 124 and 125 outputs the L-level when each of the voltage command signals VU, VV and VW is smaller than the triangular wave signal SC.
  • Figs. 13A through 13E show an operation of the current controller 106 shown in Fig. 12, when the first, second and third line current command signals iTU, iTV and iTW are three-phase sine waves, respectively.
  • each line current error can be reduced by increasing the gains of the current error amplifiers 120, 121 and 122 as a consequence of approach of the detected line currents to the respective line current command signals, and the responsibility of the detected line currents to the respective line current command signals is improved.
  • the gain of each of the current error amplifiers 120, 121 and 122 is generally set to a value which is as great as possible and falls within a range in which no oscillation occurs.
  • each of the current error amplifiers 120, 121 and 122 is determined in the designing stage by examining a loop transfer function of the current control loop from the characteristics of the three-phase motor 1, the motor current detector circuit 9, the current controller 106, and the main circuit power controller 8. In the present case, considering the manufacturing-dependent variation of the characteristics and temperature characteristics, it is required to reduce the gain to a level at which no oscillation phenomenon occurs at worst.
  • the work for determining the gain requires much labor of the operators engaging in the designing, and even a current command type PWM inverter having the same structure requires gain adjustment depending on different motors to which the inverter is to be connected, incurring such a problem that much labor is required for the control of the manufacturing process.
  • the specifications of the three-phase motor 1 to be connected to the current command type PWM inverter have not yet determined in the designing stage (e.g., in the case of a general use inverter, a general use AC servo driver or the like), it is required to adjust the gain in accordance with the specifications of the three-phase motor 1 upon determining and installing the three-phase motor 1 to which the inverter is to be connected, and there is such a problem that this gain adjustment work is a bottleneck.
  • the offset and drift of the triangular wave generator and the current error amplifiers 120, 121 and 122 themselves deteriorate the current control error and narrow the dynamic ranges of the amplified error signals. Therefore, an operational amplifier having a small offset and drift is required as a component of them, and depending on the cases, an offset adjusting work is required in the manufacturing stage, incurring the problem of cost increase.
  • Fig. 12 shows a prior art example of the current controller 106 implemented by an analog circuit
  • a current controller implementing a similar structure by a digital circuit such as a microcomputer which subjects the first, second and third detected line currents iFU, iFV and iFW to an analog to digital conversion process by means of an A/D converter.
  • the gain of the current error amplifier is required to be determined by examining the loop transfer function of the current control loop from the characteristics of the three-phase motor 1, the motor current detector circuit 9, the current controller 106, and the main circuit power controller 8, and their problems are the same as those of the current controller implemented by the analog circuit.
  • the current error amplifier when the current error amplifier is implemented by a digital circuit such as a microcomputer or the like, the offset and drift of the current error amplifier itself can be eliminated because they are achieved by digital calculation.
  • the phase delay increases and the circuit tends to oscillate. This consequently means that the gain cannot be increased unless the processing time is reduced, and therefore, a microcomputer having a very high speed calculation processing capability or the like must be used, incurring the problem of cost increase.
  • phase delay of the A/D converter for converting the first, second and third detected line currents iFU, iFV and iFW into digital data becomes greater as the time for conversion increases and tends to oscillate. This consequently means that the gain cannot be increased unless the conversion time is reduced, and therefore, an A/D converter having a very high speed conversion capability must be used, incurring the problem of cost increase. Furthermore, the offset and drift of the A/D converter consequently deteriorate the current control error and narrow its dynamic range. Therefore, it is required to select an A/D converter having smaller offset and drift, incurring the problem of cost increase.
  • the three-phase PWM command signal generator implemented by a digital circuit has such problems that the three-phase PWM command signal generator has a complicated structure and costs much as shown in the digital three-phase PWM wave generating apparatus disclosed in the Japanese Patent Laid-Open Publication No. 4-312360.
  • An essential object of the present invention is therefore to provide a current command type PWM inverter apparatus which costs less and requires no gain adjustment.
  • Another object of the present invention is to provide a current command type PWM inverter apparatus capable of exhibiting a more excellent responsibility of driving line currents for line current command signals, as compared with the prior art apparatus.
  • a current command type PWM inverter apparatus comprising:
  • said logic circuit preferably generates and outputs the first, second, third, fourth, fifth and sixth switching commend signals so as to minimize an error between the first line current command signal and the first detected line current, an error between the second line current command signal and the second detected line current, and an error between the third line current command signal and the third detected line current.
  • said logic circuit when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, third and fourth switching command signals for respectively turning off the second, third and fourth main circuit switching power devices, and further generates and outputs the first, fifth and sixth switching command signals for respectively turning on the first, fifth and sixth main circuit switching power devices,
  • said logic circuit when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, third and fourth switching command signals for respectively turning off the second, third and fourth main circuit switching power devices, and further generates and outputs the first, fifth and sixth switching command signals for respectively turning on the first, fifth and sixth main circuit switching power devices,
  • said first comparing means periodically compares the first line current command signal with the first detected line current, generates and outputs the first line current comparison signal having the first level when the first detected line current is equal to or greater than the first line current command signal at least two consecutive times, and generates and outputs the first line current comparison signal having the second level when the first detected line current is smaller than the first line current command signal at least two consecutive times,
  • the above-mentioned current command type PWM inverter apparatus further comprises:
  • a current command type PWM inverter apparatus comprising:
  • said logic circuit generates and outputs the first, second, third, fourth, fifth and sixth switching commend signals so as to minimize an error between the first line current command signal and the first detected line current, an error between the second line current command signal and the second detected line current, and an error between the third line current command signal and the third detected line current.
  • said logic circuit when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, third and fourth switching command signals for respectively turning off the second, third and fourth main circuit switching power devices, and further generates and outputs the first, fifth and sixth switching command signals for respectively turning on the first, fifth and sixth main circuit switching power devices,
  • said logic circuit when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, third and fourth switching command signals for respectively turning off the second, third and fourth main circuit switching power devices, and further generates and outputs the first, fifth and sixth switching command signals for respectively turning on the first, fifth and sixth main circuit switching power devices,
  • said first comparing means periodically compares the first line current command signal with the first detected line current, generates and outputs the first line current comparison signal having the first level when the first detected line current is greater than the first line current command signal at least two consecutive times, and generates and outputs the first line current comparison signal having the second level when the first detected line current is equal to or smaller than the first line current command signal at least two consecutive times,
  • the above-mentioned current command type PWM inverter apparatus preferably further comprises:
  • the simple operation of deciding whether each of the first, second, third, fourth, fifth and sixth main circuit switching power devices is turned on or off in a direction in which the difference between the line current command signal and the detected line current is reduced in accordance with a state updating timing and a timing at which the first, second and third line current comparison signals or comparison result signals change is repeated, so that the line currents of the three-phase motor approach the respective line current command signals, proving the fact that each line current error can be reduced.
  • the current command type PWM inverter apparatus of the present invention has no current error amplifier, and therefore, the problems concerning the gain adjustment of the current error amplifier can be substantially solved, consequently requiring no gain adjustment.
  • the inverter apparatus operates so as to consistently minimize each line current error.
  • the inverter apparatus operates to consistently minimize each line current error even when a manufacturing-dependent variation of characteristics, temperature characteristics and the like exist, and therefore, it has a more excellent current control responsibility as compared with the prior art apparatus, and causes no oscillation phenomenon.
  • the current controller of the current command type PWM inverter apparatus of the present invention can be implemented by a simple digital circuit except for the first, second and third comparing means. Therefore, the part implemented by the digital circuit causes neither offset nor drift and costs less.
  • Fig. 7 shows a structure of a current command type PWM inverter system of the first preferred embodiment according to the present invention.
  • a fundamental frequency f and an effective current value ip of a three-phase AC current waveform to be supplied to a three-phase motor 1 are set in a current command generator 7, and based on the information, the current command generator 7 internally generates current command signals to be flown into the three-phase motor 1, and then outputs a first line current command signal iTU, a second line current command signal iTV and a third line current command signal iTW.
  • a motor current detector circuit 9 detects two line currents of the three-phase motor 1, obtains the remaining one line current by obtaining the sum of the detected two line currents and inverting the sign of the sum value, and outputs the resulting three line currents as a first detected line current iFU, a second detected line current iFV and a third detected line current iFW. It is to be noted that the motor current detector circuit 9 may detect the three line currents of the three-phase motor 1 and then output the first detected line current iFU, the second detected line current iFV and the third detected line current iFW.
  • a current controller 6 receives the first line current command signal iTU, the second line current command signal iTV, the third line current command signal iTW, the first detected line current iFU, the second detected line current iFV and the third detected line current iFW, and then, generates a first switching command signal PU, a second switching command signal PV and a third switching command signal PW.
  • a main circuit power controller 8 comprises a logic inverter circuit 5 comprising three inverters, a base driving circuit 4 comprising six base drivers, a main circuit DC power source 3, and a main circuit power device circuit 2 having a three-phase bridge connection.
  • the main circuit power device circuit 2 comprises:
  • the circuit comprised of the logic inverter circuit 5 and the base driving circuit 4 operates to turn on either the first main circuit switching power device Q1 or the fourth main circuit switching power device Q4 in accordance with the first switching command signal PU, to turn on either the second main circuit switching power device Q2 or the fifth main circuit switching power device Q5 in accordance with the second switching command signal PV, and to turn on either the third main circuit switching power device Q3 or the sixth main circuit switching power device Q6 in accordance with the third switching command signal PW.
  • the first switching command signal PU when the first switching command signal PU becomes the H-level, the first main circuit switching power device Q1 is turned on. On the other hand, when the first switching command signal PU becomes the L-level, the fourth main circuit switching power device Q4 is turned on.
  • the second switching command signal PV becomes the H-level
  • the second main circuit switching power device Q2 is turned on.
  • the fifth main circuit switching power device Q5 when the second switching command signal PV becomes the L-level, the fifth main circuit switching power device Q5 is turned on.
  • the third switching command signal PW becomes the H-level, the third main circuit switching power device Q3 is turned on.
  • the sixth main circuit switching power device Q6 is turned on.
  • the current controller 6 of the current command type PWM inverter system of the first preferred embodiment according to the present invention shown in Fig. 7 has a construction as shown in Fig. 1.
  • first, second and third comparators 17, 18 and 19 receive the command signals iTU, iTV and iTW at their respective inverted input terminals, respectively, and receive the first, second and third detected line currents iFU, iFV and iFW at their respective non-inverted input terminals, respectively. Then, the comparators 17, 18 and 19 output first, second and third line current comparison signals or comparison result signals HU, HV and HW, respectively.
  • each of the comparison signals HU, HV and HW becomes the H-level when the detected line current is equal to or greater than the value of the line current command signal, while each of the comparison signals HU, HV and HW becomes the L-level when the detected line current is smaller than the value of the line current command signal.
  • the present invention is not limited to this.
  • each of the comparison signals HU, HV and HW may become the H-level when the detected line current is greater than the value of the line current command signal, while each of the comparison signals HU, HV and HW may become the L-level when the detected line current is equal to or smaller than the value of the line current command signal.
  • a logic circuit 10 receives the first, second and third line current comparison signals HU, HV and HW as well as a periodical state updating timing signal CLK10 periodically generated by a timing generator 11, and then, outputs first, second and third switching command signals PU, PV and PW for commanding the turning-on and turning-off of the main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6.
  • the logic circuit 10 effects state switching based on the signal levels of the first, second and third line current comparison signals HU, HV and HW in accordance with the timing of the leading edge of the state updating timing signal CLK10, outputs the first, second and third switching command signals PU, PV and PW, and then updates the first, second and third switching command signals PU, PV and PW based on the switching of the signal levels of the first, second and third line current comparison signals HU, HV and HW.
  • the state No. (A00, AX1, AX2, A00, AY1, AY2, B00, BX1, etc.) represents the input and output state of the logic circuit 10
  • the symbol ⁇ of the state updating timing signal represents the leading edge of the state updating timing signal CLK10
  • the symbol ⁇ represents the stable state off the H-level or the L-level.
  • the symbol * of the line current comparison signal represents "DON'T CARE", i.e., the operation does not depend on whether the state is at the H-level or the L-level.
  • H represents the H-level
  • L represents the L-level.
  • a reset signal RESET is an input signal for initializing the logic circuit 10, and the reset signal RESET normally has the L-level.
  • the logic circuit 10 is immediately initialized when the reset signal becomes the H-level.
  • the system state shifts to the state No. AX1 when the second line current comparison signal HV changes first or shifts to the state No. AY1 when the third line current comparison signal HW changes first.
  • the logic circuit 10 reads the signal levels of the first, second and third line current comparison signals HU, HV and HW at the timing of the leading edge of the state updating timing signal CLK10, and the signal levels of the output signals PU, PV and PW of the logic circuit 10 are determined so that changes are made in a direction in which the first, second and third detected line currents iFU, iFV and iFW at the timing are made to approach the first, second and third line current command signals iTU, iTV and iTW, i.e., the detected line currents iFU, iFV and iFW are made to correspond to the respective line current command signals.
  • the output signals PU, PV and PW become signal levels obtained by inverting those of the comparison signals HU, HV and HW, respectively.
  • the comparison signal HU is the H-level
  • the output signal PU is determined to have the L-level.
  • the output signal PU is determined to have the H-level.
  • the output signals PV and PW are determined in a manner similar to the above-mentioned manner.
  • the operation for the time interval depends on the levels of the three comparison signals HU, HV and HW at the timing of each leading edge of the state updating timing signal CLK10.
  • the logic circuit 10 of the first preferred embodiment according to the present invention paying attention to two signals having an identical level out of the three comparison signals HU, HV and HW at the timing of the leading edge of the state updating timing signal CLK10, the levels of the switching command signals PU, PV and PW are determined so as to control the turning-on and turning-off of the main circuit switching power devices which supply the line currents relevant to the two signals.
  • the level of the corresponding switching command signal is inverted in such a manner that, in the case of the on-state it is switched from the on-state to off-state, while in the case of off-state it is switched from off-state to the on-state.
  • the level of the remaining one signal out of the two signals having the identical level is inverted, the level of the corresponding switching command signal is inverted so that the main circuit switching power device which supplies the line current relevant to the signal whose level is inverted is switched between the on-state and off-state in a similar manner.
  • the three signals of the first, second and third switching command signals PU, PV and PW outputted from the logic circuit 10 have an identical level, so that the signal levels coincide with the level of the signal having the level different from the others of the three comparison signals HU, HV and HW at the timing of the leading edge of the state updating timing signal CLK10.
  • the output signals PU, PV and PW are maintained to have their levels, respectively. After the timing of the next leading edge of the state updating timing signal CLK10, a similar operation will be repetitively executed.
  • each of first, second, third, fourth, fifth and sixth data selectors 36, 37, 38, 39, 40 and 41 operates to output the level of an input terminal B at an output terminal Y when an input terminal SEL is at the H-level, and output the level of an input terminal A at the output terminal Y when the input terminal SEL is at the L-level.
  • the reference numerals 26, 27 and 28 respectively denote first, second and third reset-preferential RS flip-flops, each of which is reset when an input terminal R is at the H-level and an input terminal S is at the L-level so that the level at an output terminal Q is changed to the L-level, each of which is set when the input terminal R is at the L-level and the input terminal S is at the H-level so that the level at the output terminal Q is changed to the H-level, and each of which is reset when the input terminal R is at the H-level and the input terminal S is at the H-level with the priority given to the reset so that the level at the output terminal Q is switched to the L-level.
  • the reference numerals 29, 30, 31, 12, 13 and 14 respectively denote first, second, third, fourth, fifth and sixth delay type latches (referred to as D-latches hereinafter), each of which latches the level of an input terminal D at the timing of the leading edge of the signal inputted to an input terminal CK, and then outputs the latched level to an output terminal Q.
  • D-latches delay type latches
  • an input terminal PR is a terminal for receiving a preset signal
  • each of the D-latches is preset with the most priority when the H-level is inputted thereto, and then outputs the H-level at the output terminal Q.
  • the reference numerals 23, 24, 25, 127, 128, 129, 130, 131 and 132 respectively denote first, second, third, fourth, fifth, sixth, seventh, eighth and ninth invertor gates, each of which operates to output the L-level at its output terminal when the H-level is inputted to its input terminal, and operates to output the H-level at its output terminal when the L-level is inputted to the input terminal.
  • the reference numeral 22 denotes a data decoder having input terminals A, B and C and an output terminal Y, and the truth table thereof is shown in Table 2. It is to be noted that the truth table of Table 2 can be easily implemented by AND gates, OR gates and inverter gates.
  • Table 2 INPUT OUTPUT A B C Y A ⁇ B ⁇ C + A ⁇ ⁇ B ⁇ ⁇ C + A ⁇ ⁇ B ⁇ C ⁇ + A ⁇ B ⁇ ⁇ C
  • a timing signal generator 35 receives a periodical system clock CLK1, which is periodically generated in synchronization with the system clock CLK10 with a frequency being a plurality of times the frequency of the state updating timing signal CLK10, and the state updating timing signal CLK10, and then, outputs a state updating timing delay signal CLK11.
  • the cycle of the state updating timing signal CLK10 is sufficiently greater than the cycle of the system clock CLK1, and the state updating timing signal CLK10 changes in synchronization with a trailing edge of the system clock CLK1.
  • the state updating timing delay signal CLK11 is a signal obtained by delaying the state updating timing signal CLK10 by about half the time interval between the leading edge and the trailing edge of the system clock CLK1.
  • the first, second and third data selectors 36, 37 and 38 are collectively referred to as a first data selector circuit 20, while the fourth, fifth and sixth data selectors 39, 40 and 41 are collectively referred to as a second data selector 21.
  • the fourth, fifth and sixth D-latches 12, 13 and 14 are collectively referred to as a first data latch circuit 34, while the first, second and third D-latches 29, 30 and 31 are collectively referred to as a second data latch circuit 15.
  • the input terminals A of the first, second and third data selectors 36, 37 and 38 are made to serve respectively as input terminals 1A, 2A and 3A of the first data selector circuit 20, and their input terminals B are made to serve respectively as input terminals 1B, 2B and 3B of the first data selector circuit 20.
  • Their input terminals SEL are commonly connected with each other to serve as an input terminal SEL of the first data selector circuit 20.
  • the input terminals A of the fourth, fifth and sixth data selectors 39, 40 and 41 are made to serve respectively as input terminals 1A, 2A and 3A of the second data selector circuit 21, and their input terminals B are made to serve respectively as input terminals 1B, 2B and 3B of the second data selector circuit 21.
  • Their input terminals SEL are commonly connected with each other to serve as an input terminal SEL of the second data selector circuit 21.
  • the input terminals D of the fourth, fifth and sixth D-latches 12, 13 and 14 are made to serve as input terminals 1D, 2D and 3D of the first data latch circuit 34, and their input terminals CK are commonly connected with each other to serve as an input terminal CK of the first data latch circuit 34.
  • Their input terminals PR are commonly connected with each other to serve as an input terminal PR of the first data latch circuit 34, and their output terminals Q are made to serve respectively as output terminals 1Q, 2Q and 3Q of the first data latch circuit 34.
  • the input terminals D of the first, second and third D-latches 29, 30 and 31 are made to serve as input terminals 1D, 2D and 3D of the second data latch circuit 15, and their input terminals CK are commonly connected with each other to serve as an input terminal CK of the second data latch circuit 15.
  • Their input terminals PR are commonly connected with each other to serve as an input terminal PR of the second data Latch circuit 15, and their output terminals Q are made to serve respectively as output terminals 1Q, 2Q and 3Q of the second data latch circuit 15.
  • the output signals of the first data selector circuit 20 are referred to as first selection output signals Y1U, Y1V and Y1W, while the output signals of the second data selector circuit 21 are referred to as second selection output signals Y2U, Y2V and Y2W.
  • the first, second and third line current comparison signals HU, HV and HW are inputted to the input terminals 1D, 2D and 3D of the first data latch circuit 34, are inputted to the input terminals 1B, 2B and 3B of the first data selector circuit 20, and are further inputted to the input terminals 1A, 2A and 3A via the first, second and third invertor gates 23, 24 and 25.
  • the output signals outputted from the output terminals 1Q, 2Q and 3Q of the first data latch circuit 34 are inputted to the data decoder 22, so that the output terminal Y is made to have the H-level or the L-level according to the truth table shown in Table 2.
  • the signal outputted from the output terminal Y is referred to as a mode signal YM.
  • the mode signal YM is inputted to the input terminals SEL of the first data selector circuit 20, and the first data selector circuit 20 outputs the first selection output signals Y1U, Y1V and Y1W in accordance with the mode signal YM.
  • the state updating timing delay signal CLK11 changes from the L-Level to the H-level, i.e., its leading edge is inputted.
  • a state just after the above-mentioned timing T2 shown in Fig. 4 will be described.
  • the state updating timing delay signal CLK11 is inputted to the input terminals S of the first, second and third RS flip-flops 26, 27 and 28, and the flip-flops are set when the signal CLK11 is at the H-level.
  • each of the first, second and third RS flip-flops 26, 27 and 28 is a reset-preferential RS flip-flop, and therefore, the priority is given to the reset when the input terminal R is at the H-level. Therefore, among the first, second and third RS flip-flops 26, 27 and 28, any RS flip-flop having the L-level at the input terminal R is only set consequently when the state updating timing delay signal CLK11 is at the H-level.
  • the output signals of the first, second and third RS flip-flops 26, 27 and 28 are inputted to the input terminals 1A, 2A and 3A of the second data selector circuit 21, and are inputted to their input terminals 1B, 2B and 3B via the fourth, fifth and sixth inverter gates 127, 128 and 129.
  • To the input terminals SEL of the second data selector circuit 21 is inputted the mode signal YM. Therefore, in accordance with the mode signal YM, the second data selector circuit 21 outputs the second selection output signals Y2U, Y2V and Y2W.
  • the second data latch circuit 15 receives the second selection output signals Y2U, Y2V and Y2W from its input terminals 1D, 2D and 3D and latches the same.
  • the second data latch circuit 15 outputs at its output terminals 1Q, 2Q and 3Q the latched input signals obtained from the input terminals 1D, 2D and 3D. Each of the output signals is maintained until the timing of the next leading edge of the state updating timing signal CLK10.
  • the output signals outputted from the output terminals 1Q, 2Q and 3Q of the second data latch circuit 15 are made to serve as the first, second and third switching command signals PU, PV and PW via the seventh, eighth and ninth inverter gates 130, 131 and 132.
  • the first, second and third switching command signals PU, PV and PW are updated in accordance with the timing at which the leading edge of the system clock CLK1 is inputted to the input terminals CK of the second data latch circuit 15. Therefore, the first, second and third switching command signals PU, PV and PW do not change at the timing T1 and the timing T2.
  • the line current comparison signal HU is at the L-level
  • the line current signal HV is at the H-level
  • the line current signal HW is at the H-level
  • the mode signal YM is at the L-level
  • the output signals Y1U, Y1V and Y1W from the first data selector circuit 20 are respectively at the H-level, the L-level and the L-level
  • the first RS flip-flop 26 is in reset state
  • the second RS flip-flop 27 is in set state
  • the third RS flip-flop 28 is in set state.
  • the output signals Y2U, Y2V and Y2W from the second data selector circuit 21 are respectively at the L-level, the H-level and the H-level.
  • the second line current comparison signal HV changes from the H-Level to the L-level
  • the level of the first selection output signal Y1V changes from the L-level to the H-Level, thereby resetting the second RS flip-flop 27. Therefore, the second selection output signal Y2V is changed from the H-level to the L-level.
  • the main circuit power controller 8 at the next stage operates.
  • the level of the first selection output signal Y1W changes from the L-level to the H-level, thereby resetting the third RS flip-flop 28. Therefore, the second selection output signal Y2W is changed from the H-level to the L-level.
  • the main circuit power controller 8 at the next stage operates.
  • the line current comparison signal HU is at the H-level
  • the line current comparison signal HV is at the H-level
  • the line current comparison signal HW is at the H-level
  • the mode signal YM is at the H-level
  • the output signals Y1U, Y1V and Y1W from the first data selector circuit 20 are respectively at the H-level, the H-level and the H-level
  • all the first, second and third RS flip-flops 26, 27 and 28 are in the reset state.
  • the output signals Y2U, Y2V and Y2W from the second data selector circuit 21 are respectively at the H-level, the H-level and the H-level. Therefore, the switching command signals PU, PV and PW become the L-level, the L-level and the L-level, respectively, at the timing of the next leading edge of the system clock CLK1. In accordance with these switching command signals PU, PV and PW, the main circuit power controller 8 at the next stage operates.
  • Fig. 3A is a timing chart of the first, second and third line current command signals iTU, iTV and iTW and the first, second and third detected line currents iFU, iFV and iFW.
  • Fig. 3B is an enlarged timing chart showing the operation of the logic circuit 10 in the region enclosed by dotted lines of Fig. 3A.
  • Fig. 3C is a timing chart showing the turning-on and turning-off operations of the first, second, third, fourth, fifth and sixth main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 based on the output levels of the first, second and third switching command signals PU, PV and PW outputted from the logic circuit 10.
  • the main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 are respectively turned on, off, off, off, on and on, so that the detected line currents iFU, iFV and iFW approach the line current command signals iTU, iTV and iTW according to the electric time constant of the three-phase motor 1.
  • comparison signal HU * means DON'T CARE for the convenience of explanation, and the symbol "*" means DON'T CARE hereinafter.
  • the line currents of the three-phase motor 1 are controlled so that the line currents thereof conform to the first, second and third line current command signals iTU, iTV and iTW.
  • the first, second and third comparators 17, 18 and 19 can be made to have hysteresis, when noises superimposed on the first, second and third line current command signals iTU, iTV and iTW as well as the first, second and third detected line currents iFU, iFV and iFW can be of course reduced.
  • the base driving circuit 4 which controls the main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 based on the output levels of the outputs PU, PV and PW of the current controller 6, it may be acceptable to provide a delay for a predetermined timing when each of the main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 shifts from the off-state to the on-state to assure speedy shift from the on-state to the off-state.
  • This arrangement means as follows.
  • the state when the power device Q1 is in the on-state and the power device Q4 is in the off-state is shifted to the state when the power device Q1 is in the off-state and the power device Q4 is in the on-state, first of all, the power device Q1 is turned off, and after the power device Q1 is surely turned off, the power device Q4 is turned on.
  • the power devices Q1 and Q4 are momentarily turned on simultaneously in accordance with the timing at which the power devices Q1 and Q4 are switched, so that a great current can be prevented from flowing through the main circuit switching power devices Q1 to Q6.
  • the output levels of the base drivers of the base driving circuit 4 may be made to the L-levels, respectively, so that all the power devices are turned off, for example, when it is desired to effect a current cutoff for protecting the current command type PWM inverter in the case of overload, a free-run operation of the motor or the like.
  • the problems concerning the gain control of the current error amplifiers can be substantially solved, thereby totally obviating the need of the gain control.
  • the inverter system of the present preferred embodiment operates so that each line current error is consistently minimized. Furthermore, even when there are manufacturing-dependent variation of characteristics, temperature characteristics and the like, the inverter system of the present preferred embodiment operates so that each line current error is consistently minimized, thereby assuring a better current control responsibility and preventing the possible occurrence of an oscillation phenomenon.
  • the current controller 6 of the current command type PWM inverter system can be implemented by a simple digital circuit except for the first, second and third comparators, and therefore, the part constituted by the digital circuit does not cause any offset and drift and costs less.
  • the present invention is made free from the gain adjustment work and the offset adjustment work of the current error amplifiers 120, 121 and 122, so that a better current control responsibility can be assured to allow an inexpensive current command type PWM inverter system to be provided.
  • the internal structure of the logic circuit 10a provided for the current controller 6 having the structure shown in Fig. 1 is made to be different from that of the first preferred embodiment as shown in Fig. 5.
  • the structure of the other part except for the internal structure of the logic circuit 10a are quite the same as those of the first preferred embodiment. Therefore, no detailed explanation is provided for the structure of the current controller 6 shown in Fig. 1 provided with the logic circuit 10a of the second preferred embodiment and the structure of the current command type PWM inverter system as shown in Fig. 7 provided with the current controller 6. The structure and operation of the logic circuit 10a will be described below.
  • the logic circuit 10a receives the first, second and third line current comparison signals HU, HV and HW at the timing of the leading edge of the state updating timing signal CLK10, and based on these comparison signals HU, HV and HW, the signal levels of the switching command signals PU, PV and PW are determined quite in the same manner as in the logic circuit 10a of the first preferred embodiment.
  • the level of the corresponding switching command signal is inverted so that the main circuit switching power device which supplies the line current relevant to the signal that has been inverted before out of the two signals having an identical level is controlled to be turned on when the power device is in the off-state, and is controlled to be turned off when the power device is in the on-state quite in the same manner as in the operation of the logic circuit 10 of the first preferred embodiment.
  • the logic circuit of the present preferred embodiment operates in a manner different from that of the logic circuit 10 of the first preferred embodiment in that, when the level of the other one of the two signals that have had the identical level is inverted, the on-state or the off-state of the main circuit switching power device which supplies the line current relevant to the signal that has been inverted is not switched subsequently, and the level of only one signal of the other two switching command signals is inverted again.
  • the three switching command signals PU, PV and PW outputted from the logic circuit 10a have an identical level.
  • the levels of the three switching command signals PU, PV and PW become such a relationship that their signal levels are inverted from the signal levels in the first preferred embodiment, respectively, i.e., the levels of the three switching command signals PU, PV and PW become the levels obtained by inverting the level of one signal having the level different from those of the others among the three comparison signals HU, HV and HW at the timing of the leading edge of the state updating timing signal CLK10.
  • the levels of the switching command signals PU, PV and PW are maintained until the timing of the next leading edge of the state updating timing signal CLK10. Then, after the timing of the next leading edge of the state updating timing signal CLK10, the similar operation will be repeated.
  • the reference numerals 135 and 136 denote first and second AND circuits.
  • the H-level is inputted to all the three input terminals of the first AND circuit 135 or to all the two input terminals of the second AND circuit 136, the signal having the H-level is outputted from each output terminal thereof.
  • the signal having the L-Level is outputted from each output terminal thereof.
  • the output terminal Y of the data decoder 22 is connected to the input terminal A of the seventh data selector 42 via the tenth inverter gate 133, and is directly connected to the input terminal B.
  • the output terminal Y of the seventh data selector 42 is connected to the input terminal SEL of the second data selector circuit 21.
  • the input terminal SEL of the seventh data selector 42 is connected to the output terminal Q of the seventh D-latch 16.
  • the input terminal D of the seventh D-latch 16 is grounded to always have the L-level.
  • the input terminal CK of the seventh D-latch 16 is connected to the output terminal of the first AND circuit 135, while the input terminal PR of the seventh D-latch 16 is connected to the output terminal of the second AND circuit 136.
  • the three input terminals of the first AND circuit 135 are connected to the output terminals Q of the first, second and third RS flip-flops 26, 27 and 28 via the fourth, fifth and sixth inverter gates 127, 128 and 129, respectively.
  • To one of the two input terminals of the second AND circuit 136 is inputted the state updating timing delay signal CLK11 via the eleventh inverter gate 134, while the state updating timing signal CLK10 is inputted to the other input terminal.
  • the level inputted to the input terminal B is outputted to the output terminal Y when the seventh D-latch 16 is preset to yield the H-level at the output terminal Q, and when the input terminal CK of the seventh D-latch 16 is switched from the L-level to the H-level, the output terminal Q becomes the L-level, so that the level inputted to the input terminal A is outputted to the output terminal Y of the seventh data selector 42.
  • the seventh D-latch 16 is preset when the state updating timing delay signal CLK11 is at the L-level and the state updating timing signal CLK10 is at the H-level.
  • the input terminal CK switches from the L-level to the H-level when all the first, second and third RS flip-flops 26, 27 and 28 are reset.
  • the state updating timing signal CLK10 has the H-level and the state updating timing delay signal CLK11 has the L-level before the leading edge of the state updating timing delay signal CLK11, so that the seventh D-latch 16 is preset. Therefore, a signal having a level identical to the mode signal YM of the data decoder 22 is inputted to the input terminal SEL of the second data selector circuit 21.
  • the input terminal SEL of the second data selector circuit 21 is not inverted until all the first, second and third RS flip-flops 26, 27 and 28 are reset.
  • the output terminal Q thereof becomes the L-level
  • the output level of the AND gate 135 becomes the H-level
  • the output terminal Q of the D-latch 16 becomes the L-level
  • the input terminal SEL of the second data selector circuit 21 is inverted.
  • Each switched level is maintained until the timing of the leading edge of the system clock CLK1 subsequent to the timing of the next leading edge of the state updating timing signal CLK10 in a manner similar to that of the first preferred embodiment.
  • the present preferred embodiment differs only in the point that the levels of the switching command signals PU, PV and PW at an identical level obtained as a consequence of the final shift of the second preferred embodiment are reverse to the levels of the switching command signals PU, PV and PW of the first preferred embodiment only when the level of one signal out of the three comparison signals HU, HV and HW is different from the others at the timing of the leading edge of the state updating timing signal CLK10.
  • the line voltage of each phase of the three-phase motor 1 becomes zero when the switching command signals PU, PV and PW are identical to each other. Therefore, when the switching command signals PU, PV and PW have either the levels of H, H and H or the levels of L, L and L, there is no change in the line voltage of each phase until the timing of the next leading edge of the state updating timing signal CLK10. Therefore, the second preferred embodiment can control the line currents of the three-phase motor 1 equivalently in a manner similar to that of the first preferred embodiment.
  • switching command signals PU, PV and PW have the levels of H, H and H in the state No. G00 and make the switching command signals PU, PV and PW have the levels of L, L and L in the state No. H00 in Table 3.
  • the internal structure of the current controller 6 of the current command type PWM inverter system shown in Fig. 7 is made to be different from that of the first preferred embodiment or the second preferred embodiment.
  • Fig. 6 shows the internal structure of the current controller 6 of the third preferred embodiment according to the present invention.
  • the third preferred embodiment according to the present invention has quite the same structure as that of the first preferred embodiment or the second preferred embodiment except for first, second and third twice-read logic circuits 48, 49 and 50 provided as constituent components of the current controller 6 shown in Fig. 6.
  • first, second and third twice-read logic circuits 48, 49 and 50 have quite the same structures, the structure of the first twice-read logic circuit 48 will be described below with reference to Fig. 8.
  • first of all, eighth and ninth D-latches 51 and 52 latch the levels at their input terminals D at the timing of the leading edge of the signal inputted to their input terminals CK, and then, output the levels at the input terminals D to their output terminals Q.
  • their input terminals PR are terminals for receiving the input of a preset signal
  • the D-latches 51 and 52 are preset with first priority when the H-level is inputted thereto, when the output terminals Q thereof become the H-level.
  • the input terminals CK and the input terminals PR of the eighth and ninth D-latches 51 and 52 are commonly connected to each other.
  • the reference numerals 137 and 138 denote twelfth and thirteenth inverter gates, each of which outputs the L-level at their output terminals when the H-Level is inputted to their input terminals, and each of which outputs the H-level at the output terminals when the L-level is inputted to the input terminals.
  • the reference numeral 53 denotes a fourth RS flip-flop which is reset when its input terminal R is at the H-level and its input terminal S is at the L-Level so as to switch the level at its output terminal Q to the L-level, and is set when the input terminal R is at the L-level and the input terminal S is at the H-level so as to switch the level at the output terminal Q to the H-level.
  • the reference numerals 54 and 55 denote third and fourth AND-circuits 54 and 55, each of which outputs the H-level output signals when an the H-level signal is inputted to all input terminals, and each of which outputs the L-level output signals in any other case.
  • the level of the first line current comparison signal HU inputted to an input terminal SI of the first twice-read logic circuit 48 is latched and held in the eighth D-latch 51 and is outputted at its output terminal Q.
  • the system clock CLK2 is synchronization with the system clock CLK1, and has a frequency which is a plurality of times the frequency of the system clock CLK1.
  • the level at the output terminal Q of the eighth D-latch 51 is latched and held in the ninth D-latch 52 and is outputted at its output terminal Q.
  • the level of the comparison signal HU at this timing is latched and held in the eighth D-latch 51 and is outputted at its output terminal Q.
  • the output levels at the output terminals Q of the eighth and ninth D-latches 51 and 52 are transmitted to the fourth AND-circuit 55, and are transmitted to the third AND-circuit 54 via the twelfth and thirteenth inverter gates 137 and 138. Then, the output signal from the third AND-circuit 54 is transmitted to the input terminal R of the fourth RS flip-flop 53, while the output signal from the fourth AND-circuit 55 is transmitted to the input terminal S of the fourth RS flip-flop 53. Then, the output terminal Q of the fourth RS flip-flop 53 outputs the signal HU1 as an output signal of the first twice-read logic circuit 48.
  • the first twice-read logic circuit 48 checks or detected the input signal HU at the timing of every leading edge of the system clock CLK2, then operates to switch the output signal HU1 to the H-level when two consecutive H-Levels are detected, and operates to switch the output signal HU1 to the L-level when two consecutive L-levels are detected.
  • the first, second and third twice-read logic circuits 48, 49 and 50 can generate the comparison signals HU1, HV1 and HW1 freed from the signals attributed to very short-term noises included in the comparison signals HU, HV and HW, i.e., freed from the following signal change: the H-level ⁇ the L-level ⁇ the H-level or the L-level ⁇ the H-level ⁇ the L-level.
  • the number of times for reading the timing of the leading edge of the system clock CLK2 can be set to be equal to or greater than three by providing three or more D-latches and ANDing the output levels of the D-latches.
  • the noises superimposed on the output signals from the first, second and third comparators 17, 18 and 19 can be removed.
  • the line currents of the three-phase motor 1 can be controlled so that the line currents thereof correctly coincide with the first, second and third line current command signals iTU, iTV and iTW.
  • the first, second and third twice-read logic circuits 48, 49 and 50 may be incorporated into each of the first preferred embodiment and the second preferred embodiment. It is to be noted that the same effect can be of course obtained when the first, second and third twice-read logic circuits 48, 49 and 50 are incorporated into each of the first preferred embodiment and the second preferred embodiment.
  • Fig. 9 shows an internal structure of the logic circuit 10b of the current controller 6 of the current command type PWM inverter system shown in Fig. 7 according to the fourth preferred embodiment of the present invention.
  • the logic circuit 10b of the present preferred embodiment has quite the same structure except that the output signals PU1, PV1 and PW1 from the seventh, eighth and ninth inverter gates 130, 131 and 132 are inputted to first, second and third switching command signal delay circuits 56, 57 and 58, and the output signals from the delay circuits 56, 57 and 58 are transmitted as the first, second and third switching command signals PU, PV and PW to the main circuit power controller 8.
  • the first, second and third switching command signal delay circuits 56, 57 and 58 respectively receive the output signals PU1, PV1 and PW1 of the seventh, eighth and ninth inverter gates 130, 131 and 132, and transmit signals obtained by delaying the input signals by a predetermined timing according to a predetermined rule as the first, second and third switching command signals PU, PV and PW to the main circuit power controller 8. That is, in Table 1 and Table 3, the delay time is made to be zero only when the system state shifts to any one of the state Nos. A00, B00, C00, D00, E00, F00, G00 and H00, namely, at the leading edge of the system clock CLK10. When the system states shifts to any other state, the first, second and third switching command signals PU, PV and PW are outputted by being delayed by the predetermined time such as several micro seconds.
  • Fig. 10A is a timing chart of the first, second and third line current command signals iTU, iTV and iTW and the first, second and third detected line currents iFU, iFV and iFW.
  • Fig. 10B is an enlarged timing chart showing an operation of the logic circuit 10b provided with the first, second and third switching command signal delay circuits 56, 57 and 58 in the region enclosed by dotted lines of Fig. 10A.
  • 10C is a timing chart showing turning-on and turning-off operations of the main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 based on the output levels of the first, second and third switching command signals PU, PV and PW outputted from the first, second and third switching command signal delay circuits 56, 57 and 58.
  • the first, second and third switching command signal delay circuits 56, 57 and 58 output the switched signal levels of the signals PU1, PV1 and PW1 as PU, PV and PW without any level change, and the signals PU, PV and PW are transmitted to the main circuit power controller 8.
  • the main circuit switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 are respectively turned on, off, off, off, on and on, so that the first, second and third detected line currents iFU, iFV and iFW approach the first, second and third line current command signals iTU, iTV and iTW according to the electric time constant of the three-phase motor 1.
  • the reduction of the second detected line current iFV is suppressed after the elapse of a predetermined time TD from the timing when the second detected line current iFV crosses the second line current command signal iTV, and then, the system state shifts to the state No. AX1.
  • the reduction of the third detected line current iFW is suppressed after the elapse of a predetermined time TD from the timing when the third detected line current iFW crosses the third line current command signal iTW, and then, the system state shifts to the state No. AX2.
  • the line currents of the three-phase motor 1 are controlled so that the line currents thereof conform to the first, second and third line current command signals iTU, iTV and iTW.
  • the logic circuit 10b is provided with the first, second and third switching command signal delay circuits 56, 57 and 58, and the output signals from the seventh, eighth and ninth inverter gates 130, 131 and 132 are transmitted to the main circuit power controller 8 via the first, second and third switching command signal delay circuit 56, 57 and 58.
  • the first, second and third switching command signal delay circuit 56, 57 and 58 make the delay time zero only when the system state shifts to any one of the state Nos. A00, B00, C00, D00, E00, F00, G00 and H00 in Table 1 and Table 3, namely, at the leading edge of the system clock CLK10.
  • the first, second and third switching command signals PU, PV and PW are transmitted to the main circuit power controller 8 by being delayed by the predetermined time by the first, second and third switching command signal delay circuit 56, 57 and 58.
  • the line currents of the three-phase motor 1 can be made to very successfully coincide with the line current command signals.
  • the present preferred embodiment is provided by incorporating the first, second and third switching command signal delay circuits 56, 57 and 58 into the first preferred embodiment.
  • the first, second and third switching command signal delay circuits 56, 57 and 58 may be incorporated into the second preferred embodiment.
  • the same effect can be of course obtained by incorporating the first, second and third switching command signal delay circuits 56, 57 and 58 into the second preferred embodiment.
  • the current command type PWM inverter system has a structure including no current error amplifier, and therefore, the problems of the gain adjustment of the current error amplifiers can be substantially solved, requiring no gain adjustment.
  • the inverter system operates so that each line current error is consistently minimized. Furthermore, even when there are manufacturing-dependent variation of characteristics, temperature characteristics and the like, the inverter system operates so that each line current error is consistently minimized, thereby assuring a better current control responsibility and preventing the possible occurrence of an oscillation phenomenon.
  • the current controller 6 of the current command type PWM inverter system according to the present invention can be entirely implemented by simple digital circuits except for the first, second and third comparators 17, 18 and 19, so that the part constituted by the digital circuits are free from offset and drift and inexpensive.
  • the present invention is free from the gain adjustment work and the offset adjustment work of the current error amplifiers while assuring a better current control responsibility and allowing an inexpensive current command type PWM inverter system to be provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Control Of Ac Motors In General (AREA)
EP96111425A 1995-07-19 1996-07-16 Dispositif convertisseur avec pilotage de courant par modulation de largeur d'impulsion générant des signaux de pilotage périodiques Expired - Lifetime EP0756371B1 (fr)

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JP182484/95 1995-07-19
JP18248495A JP3271478B2 (ja) 1995-07-19 1995-07-19 電流指令型ｐｗｍインバータ
JP18248495 1995-07-19

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EP0756371A2 true EP0756371A2 (fr) 1997-01-29
EP0756371A3 EP0756371A3 (fr) 1998-05-06
EP0756371B1 EP0756371B1 (fr) 2003-08-27

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EP (1) EP0756371B1 (fr)
JP (1) JP3271478B2 (fr)
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DE (1) DE69629635T2 (fr)
SG (1) SG87746A1 (fr)

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DE69629635D1 (de) 2003-10-02
DE69629635T2 (de) 2004-06-24
EP0756371B1 (fr) 2003-08-27
CN1055579C (zh) 2000-08-16
EP0756371A3 (fr) 1998-05-06
US5729449A (en) 1998-03-17
SG87746A1 (en) 2002-04-16
CN1165426A (zh) 1997-11-19
JPH0937561A (ja) 1997-02-07
JP3271478B2 (ja) 2002-04-02
CN1142136A (zh) 1997-02-05

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