EP0738456A1 - Method of producing a feedthrough on a circuit board - Google Patents

Method of producing a feedthrough on a circuit board

Info

Publication number
EP0738456A1
EP0738456A1 EP95935814A EP95935814A EP0738456A1 EP 0738456 A1 EP0738456 A1 EP 0738456A1 EP 95935814 A EP95935814 A EP 95935814A EP 95935814 A EP95935814 A EP 95935814A EP 0738456 A1 EP0738456 A1 EP 0738456A1
Authority
EP
European Patent Office
Prior art keywords
circuit board
bores
copper
printed circuit
metallization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP95935814A
Other languages
German (de)
French (fr)
Inventor
Wolf Backasch
Rolf Hohmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Blaupunkt Werke GmbH
Original Assignee
Blaupunkt Werke GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Blaupunkt Werke GmbH filed Critical Blaupunkt Werke GmbH
Publication of EP0738456A1 publication Critical patent/EP0738456A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1423—Applying catalyst before etching, e.g. plating catalyst in holes before etching circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the invention is based on a method for producing a plated-through hole on a printed circuit board or on a printed circuit board according to the independent claims 1 and 9.
  • the copper-clad printed circuit board is initially at the intended locations to drill through holes and to metallize the inner wall of the hole by copper plating using a galvanic process.
  • the copper is deposited not only on the wall of the hole, but on the entire copper surface.
  • the metallized bores and the locations which later form the conductor tracks are then covered by means of an etching protective lacquer or resist film.
  • the method according to the invention or the printed circuit board with the characterizing features of the independent claims 1 and 9 has the advantage over the fact that no additional metal is deposited on the copper-ceramic plate which then has to be etched away again. Furthermore, there is the advantage that the plated-through holes can be used for the push-through installation of the connecting wires of the components, so that additional holes are omitted and space on the circuit board is thus saved. Furthermore, the workflow in the manufacture of such a printed circuit board is simplified, so that it also saves costs.
  • the measures listed in the dependent claims provide advantageous developments and improvements to the method according to the invention and the printed circuit board. It is particularly advantageous that the catalyst is applied either after drilling or after structuring the circuit board. As a result, during the subsequent electrochemical metallization, the metal can be applied directly to the catalytic converter. sator are applied without this having to be reactivated.
  • Part of the bore still remains continuous so that it can still accommodate the connecting wires of the components.
  • Nickel or nickel compounds are used for the electrochemical metallization. Nickel layers are resistant to corrosion, so that the surface of the circuit board does not have to be protected by an additional passivation layer.
  • the conductor tracks can preferably be coated with palladium or connecting lands with a gold layer.
  • thin bonding wires can advantageously also be used by the usual bonding methods, for example nailhead or thermo-compression. These bond wires can then be bonded directly to corresponding lands of an integrated circuit that is applied as a chip.
  • FIGS. 1a to 1g show sectional images of a first exemplary embodiment
  • FIGS. 2a to 2c show sectional images of a second exemplary embodiment
  • FIG. 3 shows a circuit board with components in the cutout.
  • FIG. 1 a shows a section of a printed circuit board 1, into which a vertical bore 3 has been made.
  • the circuit board is laminated on its top and bottom with a layer of copper 2.
  • the bores 3 are made at predetermined locations with a certain diameter.
  • the wall of the hole 3 is provided with an oat mediator according to FIG. 1b.
  • a chemically or galvanically applied thin copper layer of approx. 3 to 10 is used as an adhesion promoter
  • the wall of the bore 3 is covered with a catalyst 4, which causes the later metallization of the printed circuit board and the bores.
  • the catalyst is stabilized by an annealing process.
  • Palladium is preferably used as the catalyst.
  • an etching protective layer 5 is applied with a suitable masking step, for example by printing or lithographic masking, in such a way that a partial area, preferably in the form of a ring, is covered around the bore.
  • the etch protection layer or the etch protection lacquer 5 simultaneously covers the holes 3 on the printed circuit board 1 and also all the locations which are later to form the conductor tracks 2b.
  • the protective etching varnish 5 After the application of the protective etching varnish 5, the free copper surfaces according to the Figure ld etched free and then the etching protective lacquer 5 removed. As a result, the solder pads 2a formed, the catalyst 4 in the bore 3 and the conductor tracks 2b remain.
  • the locations of the printed circuit board 1 are covered according to the figure le, which should not be wetted by the subsequent metallization.
  • the solder pads 2a and the conductor tracks 2b to be wetted are left free.
  • conductor tracks for example on the underside according to the figure le, can also be completely covered so that they cannot be metallized.
  • the free areas are electrochemically metallized, in particular in the case of the holes 3, the metal connects continuously around the soldering eyes 2a, via the catalyst 4.
  • the metallized bore 8 is sleeve-shaped *, so that legs of a component to be assembled can still be inserted into the opening.
  • Nickel or nickel compounds are advantageously used for the metallization 7, so that the metallized ones
  • a further masking step can now be carried out, in which the non-metallized conductor track or parts of the conductor track 2b at position 9 are covered, for example, with a protective layer made of palladium or gold.
  • a thin bonding wire can then be bonded to these areas according to the known bonding methods, the second end of the bonding wire being bonded to the chip 23 of the integrated circuit with a corresponding land.
  • FIGS. 2a to 2c show modified working steps of the manufacturing method according to the invention as a second exemplary embodiment.
  • a double-sided laminated circuit board 1 is assumed, into which one or more holes 3 have been made.
  • the hole 3 is now covered with the protective etching lacquer 5.
  • the soldering eyes 2a at the holes 3 and the conductor tracks 2b then remain in accordance with FIG. 2c.
  • the catalyst 4 is now applied to the inner wall of the bore 3.
  • the further process steps then take place as in the first exemplary embodiment in accordance with FIGS. 1e, 1f and 1g.
  • the second exemplary embodiment therefore differs essentially in that the catalyst 4 is introduced into the bores 3 only after the application of the solder eyes and the conductor tracks. This results in the advantage that reactivation of the catalyst 4 is not necessary, since the subsequent process steps can be used without a great time delay and the catalyst 4 thus remains effective.
  • FIG. 3 shows a section of the invention
  • Printed circuit board 1 in which a component 20 is inserted with its two connecting wires 21 into the metallized bore 8.
  • the connecting wires 21 are wetted with solder 22 in a soldering process in such a way that they connect to the metallization 7.
  • a chip 23 with an integrated circuit is applied to the circuit board 1 on part of a conductor track 2b, a country. Between a connection point of the chip 23, a bonding wire 24 is guided to a further conductor track 2b, which was previously covered with a metallic protective layer 19, for example a gold layer. was covered.
  • the bonding wire 24 can be bonded to this gold layer using known manufacturing processes.

Abstract

The invention proposes a method of producing a feedthrough on a circuit board, the method calling for the circuit board first to be drilled, catalysed and the surface structured. The feedthrough is then built up by electro-deposition in such a way that electrical components can be mounted in the feedthrough. The metallization (7) is preferably carried out using nickel or nickel compounds so that no additional corrosion-protection measures are necessary. By coating connecting lands (2b) with gold or palladium, bonding can be carried out directly on the lands.

Description

Verfahren zur Herstellung einer Durchkontaktierung auf einer Leiterplatte Method for producing a via on a printed circuit board
Stand der TechnikState of the art
Die Erfindung geht aus von einem Verfahren zur Herstellung einer Durchkontaktierung auf einer Leiterplatte bzw. von ei¬ ner Leiterplatte nach den nebengeordneten Ansprüchen 1 und 9. Bei der Herstellung einer Durchkontaktierung auf einer mehrlagigen Leiterplatte ist schon bekannt, zunächst die kupferkaschierte Leiterplatte an den vorgesehenen Stellen für die Durchkontaktierung zu durchbohren und mittels eines galvanischen Prozesses die Innenwandung der Bohrung durch Kupferabscheidung zu metallisieren. Dabei wird das Kupfer nicht nur auf die Wandung der Bohrung, sondern auf die ganze Kupferfläche abgeschieden. Anschließend werden die metalli¬ sierten Bohrungen und die Stellen, die später die Leiterbah¬ nen bilden, mittels eines Ätzschutzlackes oder Resistfilmes abgedeckt. Die nicht abgedeckten Kupferflächen werden her¬ ausgeätzt, so daß nach dem Ablösen des Ätzschutzlackes die gewünschten Leiterbahnen sowie die metallisierten Durchkon- taktierungen bestehen bleiben. Bei der Metallisierung der Wandung wird dabei zwangsläufig zusätzlich Kupfer auf die Kupferflächen der Leiterplatte abgeschieden. Dieses zusätz¬ liche Kupfer muß später beim Ätzen jedoch wieder abgelöst werden, wodurch der Herstellprozeß für die Leiterplatte ver¬ teuert wird. Bekannt ist weiter, auf einer nicht kaschierten Leiterplatte im Siebdruckverfahren eine leitfähige Paste aufzudrucken, die gleichzeitig die Bohrungen ausfüllt und somit eine Durchkontaktierung bildet. Dieses Verfahren hat jedoch den Nachteil, daß die Durchkontaktierung zur Aufnahme eines Anschlußdrahtes eines elektrischen Bauelementes bei dem Verfahren der Durchsteckmontage nicht mehr verwendet werden kann, da die Bohrungen mit der Leitpaste verschlossen sind. Es müssen dann zusätzliche Bohrungen vorgesehen wer¬ den, durch die die Anschlußdrähte der Bauelemente gesteckt werden. Diese zusätzlichen Bohrungen benötigen jedoch einen zusätzlichen Platz, der insbesondere bei einer Mehrlagenver¬ drahtung auf der Leiterplatte nicht immer vorhanden ist.The invention is based on a method for producing a plated-through hole on a printed circuit board or on a printed circuit board according to the independent claims 1 and 9. When producing a plated-through hole on a multilayer printed circuit board, it is already known that the copper-clad printed circuit board is initially at the intended locations to drill through holes and to metallize the inner wall of the hole by copper plating using a galvanic process. The copper is deposited not only on the wall of the hole, but on the entire copper surface. The metallized bores and the locations which later form the conductor tracks are then covered by means of an etching protective lacquer or resist film. The copper surfaces that are not covered are etched out, so that the desired conductor tracks and the metallized vias remain after the etching protective lacquer has been removed. When metallizing the wall, copper is inevitably additionally deposited on the copper surfaces of the circuit board. However, this additional copper later has to be removed again during the etching, as a result of which the manufacturing process for the printed circuit board is made more expensive. It is also known on a non-laminated Printed on the printed circuit board using a conductive paste that simultaneously fills the holes and thus forms a via. However, this method has the disadvantage that the plated-through hole for receiving a connecting wire of an electrical component can no longer be used in the push-through assembly method, since the holes are sealed with the conductive paste. Additional bores must then be provided through which the connecting wires of the components are inserted. However, these additional bores require additional space, which is not always available, in particular in the case of multi-layer wiring on the printed circuit board.
Vorteile der ErfindungAdvantages of the invention
Das erfindungsgemäße Verfahren bzw. die Leiterplatte mit den kennzeichnenden Merkmalen der nebengeordneten Ansprüche 1 und 9 hat demgegenüber den Vorteil, daß auf der kupferka- εchierten Leiterplatte kein zusätzliches Metall abgeschieden wird, das anschließend wieder weggeätzt werden muß. Des wei¬ teren ergibt sich der Vorteil, daß die Durchkontaktierungen für die Durchsteckmontage der Anschlußdrähte der Bauelemente benutzt werden können, so daß zusätzliche Bohrungen entfal¬ len und damit Platz auf der Leiterplatte eingespart wird. Weiterhin vereinfacht sich der Arbeitsablauf bei der Her¬ stellung einer derartigen Leiterplatte, so daß dadurch auch Kosten eingespart werden.The method according to the invention or the printed circuit board with the characterizing features of the independent claims 1 and 9 has the advantage over the fact that no additional metal is deposited on the copper-ceramic plate which then has to be etched away again. Furthermore, there is the advantage that the plated-through holes can be used for the push-through installation of the connecting wires of the components, so that additional holes are omitted and space on the circuit board is thus saved. Furthermore, the workflow in the manufacture of such a printed circuit board is simplified, so that it also saves costs.
Durch die in den abhängigen Ansprüchen aufgeführten Maßnah- men sind vorteilhafte Weiterbildungen und Verbesserungen des erfindungsgemäßen Verfahrens bzw. der Leiterplatte gegeben. Besonders vorteilhaft ist, daß der Katalysator entweder nach dem Bohren oder nach dem Strukturieren der Leiterplatte auf¬ gebracht wird. Dadurch kann bei der anschließenden elektro- chemischen Metallisierung das Metall direkt auf den Kataly- sator aufgebracht werden, ohne daß dieser erneut aktiviert werden muß.The measures listed in the dependent claims provide advantageous developments and improvements to the method according to the invention and the printed circuit board. It is particularly advantageous that the catalyst is applied either after drilling or after structuring the circuit board. As a result, during the subsequent electrochemical metallization, the metal can be applied directly to the catalytic converter. sator are applied without this having to be reactivated.
Besonders vorteilhaft ist, daß die elektrochemische Metalli- sierung so dünnwandig aufgebracht wird, daß der restlicheIt is particularly advantageous that the electrochemical metallization is applied so thinly that the rest
Bohrungsteil noch durchgängig bleibt, so daß er noch die An¬ schlußdrähte der Bauelemente aufnehmen kann.Part of the bore still remains continuous so that it can still accommodate the connecting wires of the components.
Ein weiterer Vorteil besteht auch darin, daß für die elek- trochemische Metallisierung Nickel oder Nickelverbindungen verwendet werden. Nickelschichten sind gegen Korrosion be¬ ständig, so daß die Oberfläche der Leiterplatte nicht durch eine zusätzliche Passivierungsschicht geschützt werden muß.Another advantage is that nickel or nickel compounds are used for the electrochemical metallization. Nickel layers are resistant to corrosion, so that the surface of the circuit board does not have to be protected by an additional passivation layer.
Günstig ist weiterhin, daß nicht nur die Lötaugen um dieIt is also favorable that not only the soldering eyes around the
Bohrungen, sondern auch Teile der Leiterbahnen mit der Me¬ tallisierung abgedeckt werden. Dadurch sind auch diese Teile gegen Korrosionseinflüsse weitgehend geschützt.Bores, but also parts of the conductor tracks are covered with the metalization. As a result, these parts are largely protected against the effects of corrosion.
Um den Lδtvorgang oder das Bonden der Leiterplatte zu ver¬ bessern, können die Leiterbahnen vorzugsweise mit Palladium bzw. Anschlußlands mit einer Goldschicht überzogen sein. Da¬ durch können vorteilhaft auch dünne Bonddrähte durch die üb¬ lichen Bondverfahren, beispielsweise Nailhead bzw. Thermo- kompression verwendet werden. Diese Bonddrähte können dann direkt auf entsprechende Lands einer integierten Schaltung, die als Chip aufgebracht ist, gebondet werden.In order to improve the soldering process or the bonding of the printed circuit board, the conductor tracks can preferably be coated with palladium or connecting lands with a gold layer. As a result, thin bonding wires can advantageously also be used by the usual bonding methods, for example nailhead or thermo-compression. These bond wires can then be bonded directly to corresponding lands of an integrated circuit that is applied as a chip.
Zeichnungdrawing
Zwei Ausführungsbeispiele der Erfindung sind in der Zeich¬ nung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen die Figuren la bis lg Schnittbilder ei¬ nes ersten Ausführungsbeispiels, die Figuren 2a bis 2c zei- gen Schnittbilder eines zweiten Ausführungsbeispiels, und Figur 3 zeigt eine Leiterplatte mit Bauelementen im Aus¬ schnitt.Two exemplary embodiments of the invention are shown in the drawing and are explained in more detail in the description below. FIGS. 1a to 1g show sectional images of a first exemplary embodiment, FIGS. 2a to 2c show sectional images of a second exemplary embodiment, and FIG. 3 shows a circuit board with components in the cutout.
Beschreibung der AusführungsbeispieleDescription of the embodiments
Die Figuren la bis lg zeigen im Querschnitt einzelne Stadien bei der Herstellung der erfindungsgemäßen Leiterplatte eines ersten Ausführungsbeispiels . Die Figuren sind nur schema¬ tisch dargestellt und zeigen insbesondere bezüglich der Schichtdicken oder der Bohrungen keine maßstabsgetreue Wie¬ dergabe. Figur la zeigt einen Ausschnitt aus einer Leiter¬ platte 1, in die eine senkrechte Bohrung 3 eingebracht wurde. Die Leiterplatte ist auf ihrer Ober- und Unterseite mit einer Schicht Kupfer 2 kaschiert. In der kupferkaschier- ten Leiterplatte 1 werden die Bohrungen 3 an vorgegebenen Stellen mit einem bestimmten Durchmesser eingebracht. Nach dem Einbringen der Bohrungen 3 wird gemäß der Figur lb die Wandung der Bohrung 3 mit einem Haf vermittler versehen. Als Haftvermittler ist eine chemisch oder galvanisch aufgebrachte dünne Kupferschicht von ca. 3 bis 10Figures la to lg show in cross section individual stages in the manufacture of the circuit board according to the invention of a first embodiment. The figures are only shown schematically and, in particular with regard to the layer thicknesses or the bores, do not show a scale representation. FIG. 1 a shows a section of a printed circuit board 1, into which a vertical bore 3 has been made. The circuit board is laminated on its top and bottom with a layer of copper 2. In the copper-clad printed circuit board 1, the bores 3 are made at predetermined locations with a certain diameter. After the drilling of the holes 3, the wall of the hole 3 is provided with an oat mediator according to FIG. 1b. A chemically or galvanically applied thin copper layer of approx. 3 to 10 is used as an adhesion promoter
Mikrometern Stärke vorgesehen. In alternativer Ausgestaltung der Erfindung wird die Wandung der Bohrung 3 mit einem Katalysator 4 belegt, der die spätere Metallisierung der Leiterplatte und der Bohrungen bewirkt. Durch einen Temperprozeß wird der Katalysator stabilisiert. AlsMicron thickness provided. In an alternative embodiment of the invention, the wall of the bore 3 is covered with a catalyst 4, which causes the later metallization of the printed circuit board and the bores. The catalyst is stabilized by an annealing process. As
Katalysator wird vorzugsweise Palladium verwendet. Gemäß der Figur lc wird mit einem geeigneten Maskierungsschritt, beispielsweise durch Aufdrucken oder lithographisches Maskieren, eine ÄtzSchutzschicht 5 so aufgebracht, daß um die Bohrung herum noch eine Teilfläche, vorzugsweise ringförmig, abgedeckt ist. Die Ätzschutzschicht bzw. der Ätzschutzlack 5 deckt auf der Leiterplatte 1 gleichzeitig die Bohrungen 3 und auch alle die Stellen ab, die später die Leiterbahnen 2b bilden sollen. Nach dem Aufbringen des Ätzschutzlackes 5 werden die freien Kupferflächen gemäß der Figur ld freigeätzt und anschließend der Ätzschutzlack 5 entfernt. Dadurch bleiben die gebildeten Lötaugen 2a, der Katalysator 4 in der Bohrung 3 sowie die Leiterbahnen 2b bestehen. Mittels einer weiteren Maske 6 werden entsprechend der Figur le die Stellen der Leiterplatte 1 abgedeckt, die durch die nachfolgende Metallisierung nicht benetzt werden sollen. Insbesondere werden die Lötaugen 2a sowie die zu benetzenden Leiterbahnen 2b freigelassen. Es können jedoch auch Leiterbahnen, beispielsweise auf der Unterseite gemäß der Figur le vollständig abgedeckt werden, so daß sie nicht metallisiert werden können.Palladium is preferably used as the catalyst. According to FIG. 1c, an etching protective layer 5 is applied with a suitable masking step, for example by printing or lithographic masking, in such a way that a partial area, preferably in the form of a ring, is covered around the bore. The etch protection layer or the etch protection lacquer 5 simultaneously covers the holes 3 on the printed circuit board 1 and also all the locations which are later to form the conductor tracks 2b. After the application of the protective etching varnish 5, the free copper surfaces according to the Figure ld etched free and then the etching protective lacquer 5 removed. As a result, the solder pads 2a formed, the catalyst 4 in the bore 3 and the conductor tracks 2b remain. By means of a further mask 6, the locations of the printed circuit board 1 are covered according to the figure le, which should not be wetted by the subsequent metallization. In particular, the solder pads 2a and the conductor tracks 2b to be wetted are left free. However, conductor tracks, for example on the underside according to the figure le, can also be completely covered so that they cannot be metallized.
Gemäß der Figur lf erfolgt nun die elektrochemische Metalli¬ sierung der freien Stellen, wobei insbesondere bei den Boh- rungen 3 sich das Metall um die Lötaugen 2a, über den Kata¬ lysator 4 durchgehend verbindet. Die metallisierte Bohrung 8 ist hülsenförmig*, so daß noch Anschlußbeinchen eines zu mon¬ tierenden Bauelementes in die Öffnung gesteckt werden kön¬ nen. Für die Metallisierung 7 werden vorteilhaft Nickel oder Nickelverbindungen verwendet, so daß die metallisiertenAccording to FIG. 1f, the free areas are electrochemically metallized, in particular in the case of the holes 3, the metal connects continuously around the soldering eyes 2a, via the catalyst 4. The metallized bore 8 is sleeve-shaped *, so that legs of a component to be assembled can still be inserted into the opening. Nickel or nickel compounds are advantageously used for the metallization 7, so that the metallized ones
Oberflächen vorteilhaft korrosionsgeschützt sind. Gemäß der Figur lg kann nun ein weiterer Maskierungsschritt vorgenom¬ men werden, bei dem die nicht metallisierte Leiterbahn oder Teile der Leiterbahn 2b an der Position 9 beispielsweise mit einer Schutzschicht aus Palladium oder Gold überzogen wer¬ den. Auf diese Flächen kann dann insbesondere ein dünner Bonddraht nach den bekannten Bondverfahren gebondet werden, wobei das zweite Ende des Bonddrahtes mit einem entsprechen¬ den Land auf den Chip 23 der integrierten Schaltung gebondet wird.Surfaces are advantageously protected against corrosion. According to FIG. 1g, a further masking step can now be carried out, in which the non-metallized conductor track or parts of the conductor track 2b at position 9 are covered, for example, with a protective layer made of palladium or gold. In particular, a thin bonding wire can then be bonded to these areas according to the known bonding methods, the second end of the bonding wire being bonded to the chip 23 of the integrated circuit with a corresponding land.
Aus Übersichtsgründen wurden Arbeitsschritte wie Entfetten der Leiterplattenoberfläche, Reaktivieren des Katalysators, Passivieren oder Aufbringen eines Lötstoplacks bzw. Be- stückungsdrucks weggelassen. Die Figuren 2a bis 2c zeigen modifizierte Arbeitsschritte des erfindungsgemäßen Herstellungsverf hrens als zweites Ausführungsbeispiel. In Figur 2a wird wie bei Figur la von einer doppelseitig kaschierten Leiterplatte 1 ausgegangen, in die eine oder mehrere Bohrungen 3 eingebracht wurde. Ge¬ mäß der Figur 2b wird nun ähnlich wie in Figur lc die Boh¬ rung 3 mit dem Ätzschutzlack 5 abgedeckt. Nach dem Freiätzen bleiben dann entsprechend der Figur 2c die Lötaugen 2a an den Bohrungen 3 sowie die Leiterbahnen 2b stehen. Im näch¬ sten Verfahrensschritt wird nun an die Innenwandung der Boh¬ rung 3 der Katalysator 4 aufgebracht. Die weiteren Verfah¬ rensschritte erfolgen dann wie beim ersten Ausführungsbei- spiel entsprechend den Figuren le, lf und lg.For reasons of clarity, steps such as degreasing the circuit board surface, reactivating the catalyst, passivating or applying a solder resist or mounting pressure have been omitted. FIGS. 2a to 2c show modified working steps of the manufacturing method according to the invention as a second exemplary embodiment. In FIG. 2a, as in FIG. 1a, a double-sided laminated circuit board 1 is assumed, into which one or more holes 3 have been made. According to FIG. 2b, similarly to FIG. 1c, the hole 3 is now covered with the protective etching lacquer 5. After the free etching, the soldering eyes 2a at the holes 3 and the conductor tracks 2b then remain in accordance with FIG. 2c. In the next process step, the catalyst 4 is now applied to the inner wall of the bore 3. The further process steps then take place as in the first exemplary embodiment in accordance with FIGS. 1e, 1f and 1g.
Das zweite Ausführungsbeispiel unterscheidet sich also im wesentlichen dadurch, daß der Katalysator 4 erst nach dem Aufbringen der Lδtaugen und der Leiterbahnen in die Bohrun¬ gen 3 eingebracht wird. Dadurch ergibt sich der Vorteil, daß eine Reaktivierung des Katalysators 4 nicht erforderlich ist, da ohne große Zeitverzögerung die nachfolgenden Verfah¬ rensschritte angewandt werden können und somit der Katalysa¬ tor 4 wirksam bleibt.The second exemplary embodiment therefore differs essentially in that the catalyst 4 is introduced into the bores 3 only after the application of the solder eyes and the conductor tracks. This results in the advantage that reactivation of the catalyst 4 is not necessary, since the subsequent process steps can be used without a great time delay and the catalyst 4 thus remains effective.
Figur 3 zeigt einen Ausschnitt aus der erfindungsgemäßenFigure 3 shows a section of the invention
Leiterplatte 1, bei der ein Bauelement 20 mit seinen beiden Anschlußdrähten 21 in die metallisierte Bohrung 8 gesteckt ist. Die Anschlußdrähte 21 werden in einem Lötvorgang mit Lot 22 derart benetzt, daß sie sich mit der Metallisierung 7 verbinden. Des weiteren ist auf der Leiterplatte 1 ein Chip 23 mit einer integrierten Schaltung auf einem Teil einer Leiterbahn 2b, einem Land, aufgebracht. Zwischen einem An¬ schlußpunkt des Chips 23 ist ein Bonddraht 24 zu einer wei¬ teren Leiterbahn 2b geführt, die zuvor mit einer metalli- sehen Schutzschicht 19, beispielsweise einer Goldschicht, überzogen wurde. Der Bonddraht 24 kann mit bekannten Ferti¬ gungsverfahren auf dieser Goldschicht gebondet werden.Printed circuit board 1, in which a component 20 is inserted with its two connecting wires 21 into the metallized bore 8. The connecting wires 21 are wetted with solder 22 in a soldering process in such a way that they connect to the metallization 7. Furthermore, a chip 23 with an integrated circuit is applied to the circuit board 1 on part of a conductor track 2b, a country. Between a connection point of the chip 23, a bonding wire 24 is guided to a further conductor track 2b, which was previously covered with a metallic protective layer 19, for example a gold layer. was covered. The bonding wire 24 can be bonded to this gold layer using known manufacturing processes.
Die einzelnen Verfahrensschritte zur Herstellung einer Kon- taktierung sind per se bekannt und müssen daher nicht näher erläutert werden. The individual process steps for producing a contact are known per se and therefore do not have to be explained in more detail.

Claims

Ansprüche Expectations
1. Verfahren zur Herstellung einer Durchkontaktierung auf einer Leiterplatte, wobei die Leiterplatte mit wenigstens zwei Schichten aus Kupfer kaschiert ist und an vorgegebenen Stellen Bohrungen für die Durchkontaktierung aufgebracht sind und wobei die Wandung der Bohrungen durch einen elek¬ trochemischen Abscheidungsprozeß metallisiert wird, dadurch gekennzeichnet,1. A method for producing a plated-through hole on a printed circuit board, the printed circuit board being laminated with at least two layers of copper and bores being provided for the plated-through holes at predetermined locations and the wall of the bores being metallized by an electrochemical deposition process, characterized in that
a) daß auf die Wandung der Bohrungen (3) ein Haftvermittler oder ein Katalysator (4) aufgebracht wird,a) that an adhesion promoter or a catalyst (4) is applied to the wall of the bores (3),
b) daß auf dem Kupfer (2) ringförmig um die Bohrungen (3) ein Ätzschutzlack (5) aufgebracht wird, wobei der Ätz¬ schutzlack (5) auch die Bohrungen (3) und die vorgesehe¬ nen Leiterbahnen (2b) abdecken kann,b) that an etching protective lacquer (5) is applied to the copper (2) in a ring around the bores (3), the etching protective lacquer (5) also being able to cover the bores (3) and the provided conductor tracks (2b),
c) daß die nicht abgedeckten Kupferflächen freigeätzt werden und anschließend der Ätzschutzlack (5) wenigstens von den ringförmigen Kupferflächen (Lδtaugen) und den Boh¬ rungen (3) abgelöst wird undc) that the uncovered copper surfaces are etched free and then the etching protective lacquer (5) is at least detached from the ring-shaped copper surfaces (solder eyes) and the holes (3) and
d) daß durch elektrochemische Metallisierung (7) die Lötau¬ gen (2a) mit den Wandungen der Bohrungen (3) über den Katalysator (4) elektrisch leitend verbunden werden. d) that the electrochemical metallization (7) connects the soldering wires (2a) to the walls of the bores (3) via the catalyst (4) in an electrically conductive manner.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß der Katalysator (4) erst nach dem Freiätzen der Lötaugen (2a) auf die Wandung der Bohrungen (3) aufgebracht wird.2. The method according to claim 1, characterized in that the catalyst (4) is only applied to the wall of the bores (3) after the solder eyes (2a) have been etched free.
3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß der Haftvermittler (4) eine chemisch, galvanisch aufgebrachte Kupferschicht < 10 μm ist.3. The method according to claim 1, characterized in that the adhesion promoter (4) is a chemically, galvanically applied copper layer <10 microns.
4. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß die elektrochemische Metallisierung (7) dünnschichtig und hulsenförmig auf die Wandung der Bohrungen (3) aufgebracht wird.4. The method according to any one of claims 1 to 3, characterized in that the electrochemical metallization (7) is applied in thin layers and sleeves to the wall of the bores (3).
5. Verfahren nach einem der vorhergehenden Ansprüche, da- durch gekennzeichnet, daß die elektrochemische Metallisie¬ rung (7) vorzugsweise Nickel oder Nickelverbindungen auf¬ weist.5. The method according to any one of the preceding claims, characterized in that the electrochemical Metallisie¬ tion (7) preferably has nickel or nickel compounds.
6. Verfahren nach einem der vorhergehenden Ansprüche, da- durch gekennzeichnet, daß vorgegebene Teile der Leiterbahnen (2b) mit der elektrochemischen Metallisierung (7) abgedeckt werden.6. The method according to any one of the preceding claims, characterized in that predetermined parts of the conductor tracks (2b) are covered with the electrochemical metallization (7).
7. Verfahren nach einem der Ansprüche 1 bis 5, dadurch ge- kennzeichnet, daß vorgegebene Teile (2b) mit einer7. The method according to any one of claims 1 to 5, characterized in that predetermined parts (2b) with a
Schutzschicht (19) aus Palladium oder Gold abgedeckt werden.Protective layer (19) made of palladium or gold are covered.
8. Verfahren nach Anspruch 7, dadurch gekennzeichnet, daß auf der Schutzschicht (19) Bonddrähte (24) als elektrische Zuleitungen zu einem Halbleiterchip (23) aufgebracht werden.8. The method according to claim 7, characterized in that on the protective layer (19) bonding wires (24) are applied as electrical leads to a semiconductor chip (23).
9. Mehrlagige Leiterplatte (Multilayer) , hergestellt nach dem Verfahren nach einem der vorhergehenden Ansprüche, da¬ durch gekennzeichnet, daß auf der Leiterplatte (1) ein Bau- element (20) angeordnet ist, bei dem wenigstens ein An- schlußdraht (21) durch die metallisierte Bohrung (8) geführt und mit der Metallisierung (7) verlötet ist.9. multilayer printed circuit board (multilayer), produced by the method according to any one of the preceding claims, da¬ characterized in that a component (20) is arranged on the circuit board (1), in which at least one application end wire (21) through the metallized hole (8) and soldered to the metallization (7).
10. Mehrlagige Leiterplatte nach Anspruch 9, dadurch gekenn¬ zeichnet, daß auf der Leiterplatte wenigstens ein Bauelement als Chip (23) angeordnet ist, der über wenigstens einen Bonddraht (24) mit der metallisierten Schutzschicht (19) verbunden ist. 10. Multi-layer circuit board according to claim 9, characterized gekenn¬ characterized in that at least one component is arranged as a chip (23) on the circuit board, which is connected via at least one bonding wire (24) to the metallized protective layer (19).
EP95935814A 1994-11-09 1995-10-27 Method of producing a feedthrough on a circuit board Ceased EP0738456A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4439948 1994-11-09
DE4439948 1994-11-09
PCT/DE1995/001497 WO1996015651A1 (en) 1994-11-09 1995-10-27 Method of producing a feedthrough on a circuit board

Publications (1)

Publication Number Publication Date
EP0738456A1 true EP0738456A1 (en) 1996-10-23

Family

ID=6532834

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95935814A Ceased EP0738456A1 (en) 1994-11-09 1995-10-27 Method of producing a feedthrough on a circuit board

Country Status (6)

Country Link
US (1) US5799393A (en)
EP (1) EP0738456A1 (en)
JP (1) JPH09507969A (en)
DE (1) DE19541495A1 (en)
TW (1) TW310521B (en)
WO (1) WO1996015651A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5620612A (en) * 1995-08-22 1997-04-15 Macdermid, Incorporated Method for the manufacture of printed circuit boards
US6162365A (en) * 1998-03-04 2000-12-19 International Business Machines Corporation Pd etch mask for copper circuitization
SE523150C2 (en) 2000-01-14 2004-03-30 Ericsson Telefon Ab L M Circuit board and method for manufacturing circuit board with thin copper layer
US6600214B2 (en) * 2000-05-15 2003-07-29 Hitachi Aic Inc. Electronic component device and method of manufacturing the same
US6617520B1 (en) 2000-08-30 2003-09-09 Heatron, Inc. Circuit board
US6586683B2 (en) * 2001-04-27 2003-07-01 International Business Machines Corporation Printed circuit board with mixed metallurgy pads and method of fabrication
US6791845B2 (en) * 2002-09-26 2004-09-14 Fci Americas Technology, Inc. Surface mounted electrical components
WO2004099922A2 (en) * 2003-05-02 2004-11-18 Stephanie Menzies A system and method for studying a subject area, such as art
DE102019220458A1 (en) * 2019-12-20 2021-06-24 Vitesco Technologies Germany Gmbh Method of manufacturing a printed circuit board and printed circuit board
DE102019220451A1 (en) * 2019-12-20 2021-06-24 Vitesco Technologies Germany Gmbh Method of manufacturing a printed circuit board and printed circuit board

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3571923A (en) * 1968-12-30 1971-03-23 North American Rockwell Method of making redundant circuit board interconnections
DE1924775B2 (en) * 1969-05-14 1971-06-09 METHOD OF MANUFACTURING A CIRCUIT BOARD
GB1310880A (en) * 1969-06-13 1973-03-21 Microponent Dev Ltd Multi-layer printed circuit board assemblies
GB1303851A (en) * 1970-03-09 1973-01-24
FR2128355A1 (en) * 1971-03-01 1972-10-20 Fernseh Gmbh
GB1396481A (en) * 1973-02-15 1975-06-04 Matsushita Electric Ind Co Ltd Manufacture of printed circuit boards
CA981808A (en) * 1973-02-22 1976-01-13 Hyogo Hirohata Method for making a printed circuit
GB1478341A (en) * 1973-06-07 1977-06-29 Hitachi Chemical Co Ltd Printed circuit board and method of making the same
AU506288B2 (en) * 1975-10-20 1979-12-20 Nippon Electric Co., Ltd Printed circuit board
GB2118369B (en) * 1982-04-06 1986-05-21 Kanto Kasei Company Limited Making printed circuit boards
US4512829A (en) * 1983-04-07 1985-04-23 Satosen Co., Ltd. Process for producing printed circuit boards
DE3860511D1 (en) * 1987-04-24 1990-10-04 Siemens Ag METHOD FOR THE PRODUCTION OF CIRCUIT BOARDS.
US5309632A (en) * 1988-03-28 1994-05-10 Hitachi Chemical Co., Ltd. Process for producing printed wiring board
JPH01264290A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Manufacture of printed wiring board
JP2636537B2 (en) * 1991-04-08 1997-07-30 日本電気株式会社 Manufacturing method of printed wiring board
US5207888A (en) * 1991-06-24 1993-05-04 Shipley Company Inc. Electroplating process and composition
EP0584386A1 (en) * 1992-08-26 1994-03-02 International Business Machines Corporation Printed circuit board and method of producing printed circuit boards
JP2783093B2 (en) * 1992-10-21 1998-08-06 日本電気株式会社 Printed wiring board

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9615651A1 *

Also Published As

Publication number Publication date
WO1996015651A1 (en) 1996-05-23
TW310521B (en) 1997-07-11
DE19541495A1 (en) 1996-05-15
JPH09507969A (en) 1997-08-12
US5799393A (en) 1998-09-01

Similar Documents

Publication Publication Date Title
DE10148042B4 (en) Electronic component with a plastic housing and components of a height-structured metallic system carrier and method for their production
DE112004001727B4 (en) Method of manufacturing an electronic module
DE69830883T2 (en) Semiconductor device and equipped with this device circuit board
CN101690434B (en) Method for manufacturing substrate having built-in components
DE102017220175A1 (en) Board technology for power electronic circuits
EP0738456A1 (en) Method of producing a feedthrough on a circuit board
DE102005003125A1 (en) High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other
DE19509441A1 (en) Hybrid integrated circuit
EP0645953B1 (en) Method of producing a two or multilayer wiring structure and two or multilayer structure made thereof
WO2003067940A2 (en) Circuit carrier and production thereof
DE102020125813A1 (en) METHOD OF MAKING CHIP PACKAGE AND CHIP PACKAGE
EP3152985B1 (en) Method for producing a foil arrangement and corresponding foil arrangement
DE60211628T2 (en) COMPOSITE ELECTRONIC COMPONENTS
EP1980142A1 (en) Printed circuit board with functional elements and selectively filled passage openings of good thermal conductivity and method of production and use
DE102011076773A1 (en) Method for manufacturing integrated circuit e.g. MOSFET, involves attaching strip conductors of power section to strip conductor attachments by cold gas spraying process, and equipping power component space with power components
EP0090820B1 (en) Thin layered electronic circuit and manufacturing method thereof
WO2006000291A1 (en) Process for producing a ceramic printed-circuit board
DE10233607B4 (en) Arrangement comprising a semiconductor chip and a carrier provided with a plated through-hole as well as a wire connecting a connection pad of the semiconductor chip to the plated-through hole, and method for producing such an arrangement
DE3136198A1 (en) &#34;ELECTRONIC THICK FILM CIRCUIT&#34;
DE10320877A1 (en) Semiconductor component and method for producing a semiconductor component
EP1684341A2 (en) Electric circuit and method of manufacturing an electric circuit
DE10065896B4 (en) Electronic component with shielding and method for its production
DE102004012979B4 (en) Coupling substrate for semiconductor devices, arrangements with the coupling substrate, coupling substrate strip, method for producing these objects and method for producing a semiconductor module
DE10330754B4 (en) Method for producing an electrical circuit
DE102007017532A1 (en) Method for producing a printed conductor structure on a metallic base plate

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE ES FR GB IT LI NL SE

17P Request for examination filed

Effective date: 19961125

17Q First examination report despatched

Effective date: 20011213

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20020728