WO1996015651A1 - Verfahren zur herstellung einer durchkontaktierung auf einer leiterplatte - Google Patents
Verfahren zur herstellung einer durchkontaktierung auf einer leiterplatte Download PDFInfo
- Publication number
- WO1996015651A1 WO1996015651A1 PCT/DE1995/001497 DE9501497W WO9615651A1 WO 1996015651 A1 WO1996015651 A1 WO 1996015651A1 DE 9501497 W DE9501497 W DE 9501497W WO 9615651 A1 WO9615651 A1 WO 9615651A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit board
- bores
- copper
- printed circuit
- metallization
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1423—Applying catalyst before etching, e.g. plating catalyst in holes before etching circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the invention is based on a method for producing a plated-through hole on a printed circuit board or on a printed circuit board according to the independent claims 1 and 9.
- the copper-clad printed circuit board is initially at the intended locations to drill through holes and to metallize the inner wall of the hole by copper plating using a galvanic process.
- the copper is deposited not only on the wall of the hole, but on the entire copper surface.
- the metallized bores and the locations which later form the conductor tracks are then covered by means of an etching protective lacquer or resist film.
- the method according to the invention or the printed circuit board with the characterizing features of the independent claims 1 and 9 has the advantage over the fact that no additional metal is deposited on the copper-ceramic plate which then has to be etched away again. Furthermore, there is the advantage that the plated-through holes can be used for the push-through installation of the connecting wires of the components, so that additional holes are omitted and space on the circuit board is thus saved. Furthermore, the workflow in the manufacture of such a printed circuit board is simplified, so that it also saves costs.
- the measures listed in the dependent claims provide advantageous developments and improvements to the method according to the invention and the printed circuit board. It is particularly advantageous that the catalyst is applied either after drilling or after structuring the circuit board. As a result, during the subsequent electrochemical metallization, the metal can be applied directly to the catalytic converter. sator are applied without this having to be reactivated.
- Part of the bore still remains continuous so that it can still accommodate the connecting wires of the components.
- Nickel or nickel compounds are used for the electrochemical metallization. Nickel layers are resistant to corrosion, so that the surface of the circuit board does not have to be protected by an additional passivation layer.
- the conductor tracks can preferably be coated with palladium or connecting lands with a gold layer.
- thin bonding wires can advantageously also be used by the usual bonding methods, for example nailhead or thermo-compression. These bond wires can then be bonded directly to corresponding lands of an integrated circuit that is applied as a chip.
- FIGS. 1a to 1g show sectional images of a first exemplary embodiment
- FIGS. 2a to 2c show sectional images of a second exemplary embodiment
- FIG. 3 shows a circuit board with components in the cutout.
- FIG. 1 a shows a section of a printed circuit board 1, into which a vertical bore 3 has been made.
- the circuit board is laminated on its top and bottom with a layer of copper 2.
- the bores 3 are made at predetermined locations with a certain diameter.
- the wall of the hole 3 is provided with an oat mediator according to FIG. 1b.
- a chemically or galvanically applied thin copper layer of approx. 3 to 10 is used as an adhesion promoter
- the wall of the bore 3 is covered with a catalyst 4, which causes the later metallization of the printed circuit board and the bores.
- the catalyst is stabilized by an annealing process.
- Palladium is preferably used as the catalyst.
- an etching protective layer 5 is applied with a suitable masking step, for example by printing or lithographic masking, in such a way that a partial area, preferably in the form of a ring, is covered around the bore.
- the etch protection layer or the etch protection lacquer 5 simultaneously covers the holes 3 on the printed circuit board 1 and also all the locations which are later to form the conductor tracks 2b.
- the protective etching varnish 5 After the application of the protective etching varnish 5, the free copper surfaces according to the Figure ld etched free and then the etching protective lacquer 5 removed. As a result, the solder pads 2a formed, the catalyst 4 in the bore 3 and the conductor tracks 2b remain.
- the locations of the printed circuit board 1 are covered according to the figure le, which should not be wetted by the subsequent metallization.
- the solder pads 2a and the conductor tracks 2b to be wetted are left free.
- conductor tracks for example on the underside according to the figure le, can also be completely covered so that they cannot be metallized.
- the free areas are electrochemically metallized, in particular in the case of the holes 3, the metal connects continuously around the soldering eyes 2a, via the catalyst 4.
- the metallized bore 8 is sleeve-shaped *, so that legs of a component to be assembled can still be inserted into the opening.
- Nickel or nickel compounds are advantageously used for the metallization 7, so that the metallized ones
- a further masking step can now be carried out, in which the non-metallized conductor track or parts of the conductor track 2b at position 9 are covered, for example, with a protective layer made of palladium or gold.
- a thin bonding wire can then be bonded to these areas according to the known bonding methods, the second end of the bonding wire being bonded to the chip 23 of the integrated circuit with a corresponding land.
- FIGS. 2a to 2c show modified working steps of the manufacturing method according to the invention as a second exemplary embodiment.
- a double-sided laminated circuit board 1 is assumed, into which one or more holes 3 have been made.
- the hole 3 is now covered with the protective etching lacquer 5.
- the soldering eyes 2a at the holes 3 and the conductor tracks 2b then remain in accordance with FIG. 2c.
- the catalyst 4 is now applied to the inner wall of the bore 3.
- the further process steps then take place as in the first exemplary embodiment in accordance with FIGS. 1e, 1f and 1g.
- the second exemplary embodiment therefore differs essentially in that the catalyst 4 is introduced into the bores 3 only after the application of the solder eyes and the conductor tracks. This results in the advantage that reactivation of the catalyst 4 is not necessary, since the subsequent process steps can be used without a great time delay and the catalyst 4 thus remains effective.
- FIG. 3 shows a section of the invention
- Printed circuit board 1 in which a component 20 is inserted with its two connecting wires 21 into the metallized bore 8.
- the connecting wires 21 are wetted with solder 22 in a soldering process in such a way that they connect to the metallization 7.
- a chip 23 with an integrated circuit is applied to the circuit board 1 on part of a conductor track 2b, a country. Between a connection point of the chip 23, a bonding wire 24 is guided to a further conductor track 2b, which was previously covered with a metallic protective layer 19, for example a gold layer. was covered.
- the bonding wire 24 can be bonded to this gold layer using known manufacturing processes.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8515629A JPH09507969A (ja) | 1994-11-09 | 1995-10-27 | 導体板上の貫通接続部の製法 |
EP95935814A EP0738456A1 (de) | 1994-11-09 | 1995-10-27 | Verfahren zur herstellung einer durchkontaktierung auf einer leiterplatte |
US08/669,330 US5799393A (en) | 1994-11-09 | 1995-10-27 | Method for producing a plated-through hole on a printed-circuit board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEP4439948.0 | 1994-11-09 | ||
DE4439948 | 1994-11-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996015651A1 true WO1996015651A1 (de) | 1996-05-23 |
Family
ID=6532834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1995/001497 WO1996015651A1 (de) | 1994-11-09 | 1995-10-27 | Verfahren zur herstellung einer durchkontaktierung auf einer leiterplatte |
Country Status (6)
Country | Link |
---|---|
US (1) | US5799393A (de) |
EP (1) | EP0738456A1 (de) |
JP (1) | JPH09507969A (de) |
DE (1) | DE19541495A1 (de) |
TW (1) | TW310521B (de) |
WO (1) | WO1996015651A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100412155B1 (ko) * | 2000-05-15 | 2003-12-24 | 히다찌 에이아이시 가부시키가이샤 | 전자 부품 장치 및 그의 제조방법 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5620612A (en) * | 1995-08-22 | 1997-04-15 | Macdermid, Incorporated | Method for the manufacture of printed circuit boards |
US6162365A (en) * | 1998-03-04 | 2000-12-19 | International Business Machines Corporation | Pd etch mask for copper circuitization |
SE523150C2 (sv) | 2000-01-14 | 2004-03-30 | Ericsson Telefon Ab L M | Kretsmönsterkort och metod för tillverkning av kretsmönsterkort med tunt kopparskikt |
US6617520B1 (en) | 2000-08-30 | 2003-09-09 | Heatron, Inc. | Circuit board |
US6586683B2 (en) | 2001-04-27 | 2003-07-01 | International Business Machines Corporation | Printed circuit board with mixed metallurgy pads and method of fabrication |
US6791845B2 (en) * | 2002-09-26 | 2004-09-14 | Fci Americas Technology, Inc. | Surface mounted electrical components |
WO2004099922A2 (en) * | 2003-05-02 | 2004-11-18 | Stephanie Menzies | A system and method for studying a subject area, such as art |
DE102019220458A1 (de) * | 2019-12-20 | 2021-06-24 | Vitesco Technologies Germany Gmbh | Verfahren zur Herstellung einer Leiterplatte und Leiterplatte |
DE102019220451A1 (de) * | 2019-12-20 | 2021-06-24 | Vitesco Technologies Germany Gmbh | Verfahren zur Herstellung einer Leiterplatte und Leiterplatte |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3675318A (en) * | 1969-05-14 | 1972-07-11 | Siemens Ag | Process for the production of a circuit board |
FR2128355A1 (de) * | 1971-03-01 | 1972-10-20 | Fernseh Gmbh | |
FR2232908A1 (de) * | 1973-06-07 | 1975-01-03 | Hitachi Chemical Co Ltd | |
GB1396481A (en) * | 1973-02-15 | 1975-06-04 | Matsushita Electric Ind Co Ltd | Manufacture of printed circuit boards |
GB2118369A (en) * | 1982-04-06 | 1983-10-26 | Kanto Kasei Company Limited | Making printed circuit boards |
US4512829A (en) * | 1983-04-07 | 1985-04-23 | Satosen Co., Ltd. | Process for producing printed circuit boards |
JPH01264290A (ja) * | 1988-04-15 | 1989-10-20 | Hitachi Ltd | プリント配線板の製造方法 |
EP0594427A2 (de) * | 1992-10-21 | 1994-04-27 | Nec Corporation | Leiterplatte mit darauf montierten elektrischen Bauelementen |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3571923A (en) * | 1968-12-30 | 1971-03-23 | North American Rockwell | Method of making redundant circuit board interconnections |
GB1310880A (en) * | 1969-06-13 | 1973-03-21 | Microponent Dev Ltd | Multi-layer printed circuit board assemblies |
GB1303851A (de) * | 1970-03-09 | 1973-01-24 | ||
CA981808A (en) * | 1973-02-22 | 1976-01-13 | Hyogo Hirohata | Method for making a printed circuit |
AU506288B2 (en) * | 1975-10-20 | 1979-12-20 | Nippon Electric Co., Ltd | Printed circuit board |
ATE56050T1 (de) * | 1987-04-24 | 1990-09-15 | Siemens Ag | Verfahren zur herstellung von leiterplatten. |
US5309632A (en) * | 1988-03-28 | 1994-05-10 | Hitachi Chemical Co., Ltd. | Process for producing printed wiring board |
JP2636537B2 (ja) * | 1991-04-08 | 1997-07-30 | 日本電気株式会社 | プリント配線板の製造方法 |
US5207888A (en) * | 1991-06-24 | 1993-05-04 | Shipley Company Inc. | Electroplating process and composition |
EP0584386A1 (de) * | 1992-08-26 | 1994-03-02 | International Business Machines Corporation | Leiterplatte und Herstellungsverfahren für Leiterplatten |
-
1995
- 1995-10-27 WO PCT/DE1995/001497 patent/WO1996015651A1/de not_active Application Discontinuation
- 1995-10-27 JP JP8515629A patent/JPH09507969A/ja active Pending
- 1995-10-27 US US08/669,330 patent/US5799393A/en not_active Expired - Fee Related
- 1995-10-27 EP EP95935814A patent/EP0738456A1/de not_active Ceased
- 1995-11-01 TW TW084111514A patent/TW310521B/zh active
- 1995-11-08 DE DE19541495A patent/DE19541495A1/de not_active Withdrawn
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3675318A (en) * | 1969-05-14 | 1972-07-11 | Siemens Ag | Process for the production of a circuit board |
FR2128355A1 (de) * | 1971-03-01 | 1972-10-20 | Fernseh Gmbh | |
GB1396481A (en) * | 1973-02-15 | 1975-06-04 | Matsushita Electric Ind Co Ltd | Manufacture of printed circuit boards |
FR2232908A1 (de) * | 1973-06-07 | 1975-01-03 | Hitachi Chemical Co Ltd | |
GB2118369A (en) * | 1982-04-06 | 1983-10-26 | Kanto Kasei Company Limited | Making printed circuit boards |
US4512829A (en) * | 1983-04-07 | 1985-04-23 | Satosen Co., Ltd. | Process for producing printed circuit boards |
JPH01264290A (ja) * | 1988-04-15 | 1989-10-20 | Hitachi Ltd | プリント配線板の製造方法 |
EP0594427A2 (de) * | 1992-10-21 | 1994-04-27 | Nec Corporation | Leiterplatte mit darauf montierten elektrischen Bauelementen |
Non-Patent Citations (2)
Title |
---|
B.T. PATTERSON: "Additive and subtractive processes join forces", ELECTRONIC PACKAGING AND PRODUCTION, vol. 32, no. 3, MASSACHUSETTS US, pages 40 - 42, XP000263010 * |
PATENT ABSTRACTS OF JAPAN vol. 14, no. 22 (E - 874)<3965> 17 January 1990 (1990-01-17) * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100412155B1 (ko) * | 2000-05-15 | 2003-12-24 | 히다찌 에이아이시 가부시키가이샤 | 전자 부품 장치 및 그의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
JPH09507969A (ja) | 1997-08-12 |
DE19541495A1 (de) | 1996-05-15 |
EP0738456A1 (de) | 1996-10-23 |
TW310521B (de) | 1997-07-11 |
US5799393A (en) | 1998-09-01 |
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