EP0731375B1 - Flüssigkristall-Anzeigevorrichtung - Google Patents

Flüssigkristall-Anzeigevorrichtung Download PDF

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Publication number
EP0731375B1
EP0731375B1 EP96301495A EP96301495A EP0731375B1 EP 0731375 B1 EP0731375 B1 EP 0731375B1 EP 96301495 A EP96301495 A EP 96301495A EP 96301495 A EP96301495 A EP 96301495A EP 0731375 B1 EP0731375 B1 EP 0731375B1
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EP
European Patent Office
Prior art keywords
liquid crystal
display apparatus
crystal display
substrate
picture element
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EP96301495A
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English (en)
French (fr)
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EP0731375A2 (de
EP0731375A3 (de
Inventor
Takanori c/o Canon K.K. Watanabe
Mamoru C/O Canon K.K. Miyawaki
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G02F1/136281—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon having a transmissive semiconductor substrate

Definitions

  • the present invention relates to a liquid crystal display apparatus, particularly to an active matrix type of liquid crystal display apparatus having a switching element for each picture element.
  • Fig. 1 shows an equivalent circuit of a picture element cell of an active matrix type of liquid crystal display.
  • the numeral 1001 denotes a signal wiring; 1002, a picture element transistor; and 1003, a gate line for controlling on/off of the transistor 1002.
  • An image signal given to the signal wiring 1001 is written into the picture element electrode through the picture element transistor 1002, and is applied as a voltage to the liquid crystal 1004.
  • the signal written once on the element electrode will change owing to a leakage current to the liquid crystal and the leakage to the picture element. Therefore, for retaining the potential of the picture element until the subsequent writing, a retention capacitance 1005 is provided parallel to the picture element electrode.
  • Fig. 2A illustrates a sectional view of a structure of a conventional picture element cell (Japanese Patent Publication No. 1-33833), and Fig. 2B illustrates a plan view of the structure thereof.
  • the numeral 1101 denotes a transparent insulating substrate; 1102, a signal wiring; 1103, a gate line formed from polysilicon; 1104, an insulating film formed by oxidation of the polysilicon 1103; 1105, a source for the picture element transistor; 1106, a drain of the picture element transistor; 1107, an electrode for forming the retention capacitance which forms capacitance with the extended region of the drain 1106, namely the picture element electrode 1109, with interposition of an insulating film 1108.
  • the retention capacitance of 30 fF is required for controlling the potential variation to be within 10 mV for the retention time of 1/30 second.
  • the insulating film 1108 to be an SiO 2 film 60nm (600 ⁇ ) thick, an area of about 50 ⁇ m 2 is required for obtaining the capacitance of 30 pF. This is a great barrier in achieving fineness of the display apparatus.
  • the area for one picture element is about 700 ⁇ m 2 , and aperture loss caused by the capacitance formation is about 7%
  • the area for one picture element is about 230 ⁇ m 2
  • the aperture loss by the capacitance formation amounts to about 20% of the area.
  • the increase of the number of the picture elements results in decrease of the area for one picture element to cause loss of the necessary capacitance disadvantageously.
  • the common electrode 1107 which is formed simultaneously with the gate line 1103, is wired in one direction so as not to cross over the gate line 1103. Therefore the resistance of the wiring for the common electrode becomes higher, which causes variation of the potential of the common electrode on writing of signals into the picture element electrode.
  • the insulating film which is formed by oxidation of polysilicon, is not so reliable as an oxidation film of a monocrystalline silicon, and is liable to cause leakage or dielectric breakdown at a decreased film thickness.
  • FIG. 3 illustrates schematically the liquid display apparatus disclosed by the above WO 89/02095.
  • the liquid crystal display apparatus shown in Fig. 3 comprises a silicon wafer 11, an insulating layer 13 formed thereon by ion implantation, a transistor formed further thereon having a source 21, a drain 17, a gate oxidation film 27, and a gate 29, a picture element electrode 33 connected to the source 21, and a constituting member 36 on the picture element electrode 33.
  • the source/capacitor region 21 serves as the one plate
  • the substrate 11 serves as the other plate.
  • the capacitance formed by the source/capacitor region 21 and the substrate 11 retains the voltage applied through the picture element electrode to the liquid crystal.
  • the inventors of the present invention studied the liquid display apparatus disclosed in WO 89/02095, and found that the parasitic capacitance becomes larger between a signal wiring (not shown in the drawing) connected to the drain 17 and the substrate 11 owing to formation of a transistor on the uniform thin insulating layer 13 on the substrate 11.
  • the larger parasitic capacitance results in a larger time constant, which can hinder normal driving of the liquid crystal in a display apparatus having a large number of picture elements.
  • the pre-characterising part of claim 1 is based on the disclosure of WO89/02095.
  • An object of the present invention is to provide a liquid crystal display apparatus in which the above problems are solved.
  • Another object of the present invention is to provide a liquid crystal display apparatus in which the retention capacitance for holding the voltage to be applied to the liquid crystal is formed efficiently and the parasitic capacitance of the wiring signal is decreased.
  • a liquid crystal display apparatus comprising a liquid crystal layer disposed between a first substrate and an opposite substrate, said first substrate comprising:
  • the above constitution of the liquid crystal display apparatus solves the aforementioned problems and achieves the above objects.
  • a capacitance is formed between the drain and the semiconductor layer by placing the semiconductor layer under the drain with interposition of an insulating layer.
  • the insulating layer is made thicker at the portion under the source than that at the portion under the drain, whereby the parasitic capacitance of the signal wiring connected to the source is reduced.
  • Fig. 1 illustrates an equivalent circuit of a picture element cell of a conventional active matrix type of liquid crystal display apparatus.
  • Figs. 2A and 2B illustrate a sectional view of a structure and a plan view of a picture cell of a conventional liquid crystal display apparatus.
  • Fig. 3 is a schematic drawing of an example of conventional liquid crystal display apparatuses.
  • Fig. 4 is a schematic partial sectional view of an example of the matrix substrate of the liquid crystal display apparatus of the present invention.
  • Fig. 5 is a schematic partial sectional view of another example of the matrix substrate of the liquid crystal display apparatus of the present invention.
  • Fig. 6 is a schematic partial sectional view of still another example of the matrix substrate of the liquid crystal display apparatus of the present invention.
  • Figs. 7A to 7C are schematic partial sectional views of the matrix substrate of the liquid crystal display apparatus of a reference example.
  • Figs. 8A to 8C are schematic partial sectional views of the matrix substrate of the liquid crystal display apparatus of another reference example.
  • Fig. 9 is a schematic partial sectional view of the matrix substrate of the liquid crystal display apparatus of still another reference example.
  • Fig. 10 is a schematic sectional view of a liquid crystal cell of the liquid crystal display apparatus of a reference example.
  • Fig. 11 is a partial equivalent circuit of a liquid crystal display apparatus.
  • Fig. 12 is an example of the drive pulse timing chart of the liquid crystal display apparatus.
  • Fig. 13 is another example of the drive pulse timing chart of the liquid crystal display apparatus.
  • Fig. 14 shows relation between the signal voltage of the liquid crystal display apparatus and the transmittance.
  • Fig. 15 is a diagram for explaining the operation of the liquid crystal display apparatus.
  • Embodiments of the liquid crystal display apparatus of the present invention may include modifications obtained by partially substituting or employing the constitution disclosed in the reference examples, provided that such modifications fall under the scope of the claims.
  • a transmission type panel in which an element substrate (or matrix substrate) is formed by providing switching elements (transistors) and other devices on a transparent insulating substrate.
  • a conductive film 102 is deposited on a transparent insulating substrate 101, and patterning is conducted by etching. A part of the etched portion of the conductive film 102 serves later as the aperture of the display apparatus. Then an insulating layer 103 is formed on the conductive film 102. (Fig. 7A)
  • Polysilicon 104 is deposited thereon for formation of a transistor. Then, gate oxidation is conducted to form a gate-insulating film 105. Gate polysilicon 106 is formed further thereon. Source-drain regions 107, 108 are formed by ion implantation. A signal wiring 109 is connected to the source 107 through a contact hole. (Fig. 7B)
  • a light-intercepting conductive film 110 is formed, and then a transparent picture element electrode 111 is formed from a material such as ITO to come to contact with the drain 108 via a through-hole.
  • a transparent picture element electrode 111 is formed from a material such as ITO to come to contact with the drain 108 via a through-hole.
  • the resulting element substrate is placed in opposition to a transparent substrate having a counter electrode etc. formed thereon, and a liquid crystal is sealed therebetween to produce a light-transmissive panel.
  • the retention capacitance for retaining the potential of the picture element electrode 111 comprises the capacitance between the drain region 108 and the conductive film 102 and the capacitance between the transparent picture element electrode 111 and the conductive light-intercepting film 110. Accordingly, a large retention capacitance is obtained without decreasing the aperture ratio, and the produced liquid crystal display apparatus is improved in brightness, fineness, and gradation.
  • the conductive film 102 as the common electrode for forming the retention capacitance is formed throughout the entire face except the aperture portion. Therefore, the parasitic resistance is remarkably reduced, and the potential of the picture element electrode 111 is stabilized in comparison with the conventional transmissive panel. Further, the drop of the aperture ratio is avoided which will be caused by wiring of the common electrode.
  • the conductive light-intercepting film 110 in the above explanation may be omitted.
  • the gradation is improved by providing a black matrix on the side of the counter electrode.
  • the conductive film 102 can be formed from ion-implanted polysilicon, monocrystalline silicon, ITO, or the like. When ITO is employed, the ITO film may be formed by a low-temperature polysilicon film formation process.
  • the insulating film 103 can also be formed by patterning of the conductive film 102 and subsequent oxidation of the surface of the film.
  • the leakage current can be reduced and the breakdown voltage can be raised by employing the source 107 and the drain 108 of an electric field relaxation structure like a mask offset structure or a DDD structure.
  • the capacitance formation shown above is effective for a reflective panel which is constructed by employing a reflective electrode as the picture element electrode 111.
  • the substrate 101 need not be transparent, and may be a silicon substrate, a metal substrate, or the like.
  • the conductive light-intercepting film 110 for capacitance formation need not be light-intercepting provided that it is conductive.
  • the conductive film may be modified to be suitable for the reflection type panel such that the film may be placed above the picture element electrodes or on the opposing substrate, or the reflection of the film itself is reduced, and apertures are not necessary, thereby obtaining a larger capacitance.
  • the regions to be made transparent are formed by etching of the conductive film 102.
  • the film is made transparent by selective oxidation.
  • a conductive film 202 is formed on a transparent insulating substrate 201.
  • the conductive film 202 is made conductive, for example, by impurity implantation into silicon.
  • the crystallinity may be polycrystalline, amorphous, or monocrystalline.
  • the transparent region 203 is formed by selective oxidation of a part of the conductive film 202.
  • an insulating film 204 is formed by oxidation on the conductive film 202.
  • polysilicon 205 is deposited thereon for formation of a transistor.
  • gate oxidation is conducted to form a gate insulating film 206.
  • Gate polysilicon 207 is formed further thereon.
  • Source-drain regions 208, 209 of the transistor are formed by ion implantation.
  • a signal wiring 210 is connected to the source 208 through a contact hole.
  • a conductive light-intercepting film 211 is formed, and then a transparent picture element electrode 212 is formed so as to come into contact with the drain 209 through a through-hole.
  • the resulting element substrate is placed in opposition to a transparent substrate having a counter electrode formed thereon, and a liquid crystal is sealed therebetween to produce a light-transmissive panel.
  • an orientation film (not shown in the drawing) of polyimide or the like is formed on the picture image electrodes or on the insulating film on the picture element electrodes, and the surface of the film is rubbed to control the orientation of the liquid crystal.
  • rubbing is liable to be insufficient in some regions owing to the surface roughness, which may cause insufficient control of orientation of the liquid crystal to give rise to defects in orientation.
  • Such an orientation defect causes a white spot, for example, in the display of black color at the point of the roughness, thereby impairing the panel contrast, disadvantageously.
  • the aperture portions bulge out since the aperture portions are formed by selective oxidation. Therefore, at least the peripheral portions of the apertures are uniformly rubbed to realize high controllability of the liquid crystal and high contrast of the liquid crystal panel.
  • the above description is made regarding a transmission type panel.
  • a reflection type panel In the construction of a reflection type panel, the same effects are obtained.
  • the bulging of the aperture portions is also effective for improving the contrast of the panel in liquid crystal display apparatuses employing no rubbing treatment.
  • polymer scattering type liquid crystal does not require the rubbing treatment.
  • the potential of the portion other than the aperture affects greatly the electric field to cause application of an abnormal electric field to the liquid crystal to impair the contrast and gradation of the panel.
  • the bulging of the aperture portions prevents the influence of the potential in other regions to improve the contrast and the gradation.
  • a peripheral driving circuit for driving a switching element comprising a thin film transistor is formed on a monocrystalline semiconductor substrate.
  • the numeral 401 denotes a monocrystalline semiconductor substrate which is made, for example, from a silicon wafer.
  • the numeral 415 denotes a display portion.
  • the numeral 416 denotes a driving circuit portion.
  • the numeral 402 denotes a LOCOS oxidation film for separation of elements of transistors in a driving circuit.
  • the numeral 403 denotes a thin insulating film which may be formed by oxidation of the surface of the wafer 401. This insulating film 403 serves as a gate insulating film, and also serves as an insulating film for forming the retention capacitance of the display picture element portion.
  • the numeral 404 denotes a well region of a transistor constituting the drive circuit.
  • the well region 404 may be omitted when the substrate 401 serves as the well.
  • the numeral 405 denotes a gate electrode for the drive circuit, and can be formed in the_same step as a transistor gate electrode 409.
  • the numerals 406 and 407 denote a source and a drain of the drive circuit.
  • a low concentration layer 408 is provided for electric field relaxation in order to increase the breakdown voltage of the source 406 and the drain 407.
  • the numerals 410 and 411 denote respectively a source and a drain of a picture element transistor.
  • a low concentration layer 412 is provided for electric field relaxation in order to increase the breakdown voltage of the source 410 and the drain 411.
  • the drain 411 and the substrate 401 form a capacitance with interposition of the thin insulating film 403 as the retention capacitance of the picture element electrode potential.
  • the drain 411 is connected to a picture element electrode 413.
  • the source 410 is connected to a signal line 414.
  • the parasitic capacitance can be reduced by forming the source 410 and the signal line 414 on the LOCOS oxidation film 402 by employing the construction shown in Example 1 described later.
  • the driving circuit may be formed by a single type transistor, or may be of a CMOS structure.
  • the driving force is strong, and leakage current is weak in comparison with the one employing polysilicon or amorphous silicon, which enables production of a miniaturized fine panel with high productivity.
  • the resulting element substrate is placed in opposition to an opposing substrate having a counter electrode, etc. thereon, and a liquid crystal is sealed therebetween to produce a reflection type panel.
  • the picture element electrode 413 is a reflective electrode.
  • a transmission type panel can be constructed by employing a transparent electrode as the picture element electrode 413.
  • the display portion has to be transparent. This is described in detail in Reference Example 4.
  • the picture element electrode is in direct contact with the drain.
  • the contact resistance can be reduced by connecting the picture electrode and the drain through aluminum or the like.
  • a transmission type of liquid crystal display apparatus is explained which is constructed by forming a peripheral driving circuit for a switching element of a thin film transistor on a monocrystalline semiconductor substrate in this Reference Example.
  • Fig. 10 is a partial sectional view of the panel of this Reference Example.
  • the numeral 501 denotes a monocrystalline semiconductor substrate; 502, an insulating layer typified by SiO 2 ; and 503, a conductive layer provided under a drain 511 of a picture element TFT with interposition of an insulating layer.
  • This conductive layer 503 is made, for example, of a polysilicon layer, provided in a form of a network on the picture element portion, and connected to a power source on the periphery of the substrate.
  • the numeral 504 denotes a well of MOSFET formed on the substrate 501; 505, a source/drain diffusion layer of the MOSFET; 506, a metal wiring connected to the source/drain; 507, a gate electrode of the MOSFET; 508, a signal wiring connected to the source region of the picture element FET; 509, a source region of the picture element TFT; 510, a gate of the picture element FET; 511, a drain of the picture element FET; 512, a channel of the picture element FET; 513, a transparent picture element electrode; 514, an insulating interlayer; 515, an orientation film; 516, a liquid crystal layer; 517, an opposing substrate; and 518, a layer of a transparent counter electrode, a color filter, a black matrix, or the like provided on the opposing substrate 517.
  • the picture element-displaying portions of the substrate 501 are etched off for transparency in this Reference Example.
  • an etching solution such as TMAH is employed which etches more rapidly silicon than the oxide film.
  • An insulating film 502 such as a LOCOS film can be used as the etching stopper in the etching.
  • a silicon nitride film may be used as the etching stopper by depositing a silicon nitride film onto the insulating film 502 before construction of the picture element transistor.
  • the peripheral circuit for driving the liquid crystal in this Reference Example is formed on a bulk monocrystalline semiconductor substrate, having advantages of high speed and high reliability.
  • the picture element display portion is formed from thin film transistor resistant to light leakage, and is less irregular in orientation owing to the small thickness of about 300 and flatness of the picture image region, whereby high contrast of the image display is accomplished.
  • a conductive layer 503 made of polysilicon is provided for forming the retention capacitance under the drain region 511 connected to the transparent picture element electrode 513 of the image element displaying portion, which makes lower the height of the through-hole for connecting the picture element electrode 513 and the drain region 511. Thereby, the connection is facilitated advantageously in production.
  • Fig. 11 is an equivalent circuit of an active matrix type of liquid crystal display apparatus of this Reference Example.
  • the numeral 601 denotes a picture element TFT; 602, a scanning line; 603, a signal line; 604, a picture element electrode; 605 a horizontal shift resistor; 606, a vertical shift resistor; 607, an image signal transmitting switch driven by the horizontal shift resister; 608, a capacitance for temporarily retaining the image signal; and 609, a second image signal transmitting switch for collectively transmitting the temporarily retained image signal from the retention capacitance to the picture element electrode.
  • the image signals are successively transmitted from the image signal input terminal 610 at time intervals.
  • the numeral 611 is a reset switch for the signal line 603.
  • Fig. 12 and Fig. 13 are respectively a driving pulse timing chart of an active matrix type of liquid crystal display apparatus.
  • the image signals are transmitted in such a manner that the signals corresponding the odd number lines, and signals corresponding to even number lines are transmitted alternately for each one field period. Therefore, in operation of the liquid crystal display apparatus, a scanning signal is firstly transmitted from the vertical shift resister 606 to a odd number scanning line (ODD1) in an odd number field to switch on the picture element TFT 601 of the odd number line.
  • ODD1 odd number scanning line
  • the image signal to be recorded in the liquid crystal is recorded in the picture element electrode 604(2), 604(4) of respective picture elements through the transmitting switch 607 successively driven by the horizontal shift resister 605 (ODD) generating horizontal scanning pulses synchronously with the image signal.
  • the image signals are transmitted to the capacitance 608 through the transmitting switch 607 successively driven by a horizontal sift resister 605 (EVEN) generating horizontal scanning pulses synchronously with the image signal.
  • the reset switch 611 is switched on to reset once the signal line 603, and a scanning signal is transmitted to an even number scanning line (EVEN1) to switch on the even line number of picture element TFT 601, the second image signal transmitting switch 609 is switched on to record image signals in the respective picture element electrodes 604(1), 604(3).
  • the image signals are recorded successively in picture element electrodes.
  • the liquid crystal molecules changes its states in correspondence with the transmitted signal voltage, and changes light transmissivity depending on the direction of a polarizing plate separately provided in a relation of a cross polarizer.
  • Fig. 14 shows the change of the transmittance of the liquid crystal cell.
  • the definition of the signal voltage V SIG of the abscissa in Fig. 14 depends on the kind of liquid crystal employed.
  • TN twisted nematic liquid crystal
  • the value is defined as the effective voltage (V rms ). This value is explained qualitatively by Fig. 15.
  • the polarity of the signal voltage is changed alternately for each frame to prevent permanent immobilization of the liquid crystal caused by DC voltage component applied to the liquid crystal.
  • the liquid crystal itself behaves in accordance with the AC voltage component as indicated by the shadow in Fig. 15.
  • the effective voltage V rms is defined by the equation below: where tF is the time for two frames, V LC (t) is the signal voltage transmitted to the liquid crystal, and V COM is the voltage applied to the counter electrode.
  • V rms is equivalent to V SIG , and the liquid crystal cell changes its light transmittance in accordance with V rms to display an intended image.
  • the picture elements are displaced, for example, by 0.5 picture element size.
  • the horizontal intervals between the picture elements adjacent to each other in an odd number line are filled by picture elements of even number line, and the horizontal resolution is improved seemingly.
  • the timings of the horizontal scanning pulses have to be shifted between the odd number lines and the even number lines as shown in the timing chart in Fig. 13.
  • This example is readily made practicable owing to the effects of the small capacitance of the signal lines, and the low time constant of writing. Further, the shift registers and the switches are decreased in number, enabling miniaturization of the panel; miniaturization, weight reduction, and cost reduction of the product; and high yield of production to lower the production cost advantageously.
  • the signal voltage is applied by alternately changing the voltage polarity to prevent permanent immobilization of the liquid crystal which will be caused by applied of DC voltage component.
  • the light transmittance will change slightly.
  • this change is perceived by human eye to be recognized as variation of brightness or flickering.
  • the flickering can be prevented by the above-mentioned simultaneous two-line driving method in which the same image signals are written in on the odd number lines and the even number lines and decreasing the polarity reversal cycle time by half to 1/60 second.
  • the apparatus is characterized by the thickness of the insulating layer which has a larger thickness at the portion under the source than at the portion under the drain.
  • this characteristic structure is mainly explained.
  • the present invention includes modifications obtained by partially substituting, employing, or supplementing the constitution disclosed in Reference Examples, such as process for producing the element substrate, the driving circuit, and the materials for constituting the liquid crystal display apparatus.
  • the element substrate is a silicon substrate containing an impurity and having electroconductivity.
  • the element substrate is explained by reference to a schematic sectional view of Fig. 4.
  • Fig. 4 and the description below, the insulating interlayer and the step of formation thereof are omitted.
  • the numeral 301 denotes an impurity-containing conductive silicon substrate; 302, SiO 2 formed by selective oxidation (hereinafter referred to as "LOCOS oxidation film"); 303, an oxidation film thinner than the LOCOS oxidation film 302; 304, a polysilicon or an amorphous silicon to be converted to a transistor; 306, a gate electrode formed on the surface thereof with interposition of a gate oxidation film 305; 307, a source; and 308, a drain.
  • the source 307 and the drain 308 are formed by diffusion of an impurity.
  • the source region and the drain region may be formed by implantation of two kinds of ions having respectively a diffusion coefficient different from each other, or application of offset through a mask to have an LDD structure in which the impurity concentrations change stepwise to improve the breakdown voltage.
  • the source 307 is connected to a signal wiring 309 through a contact hole.
  • the drain 308 is connected to a picture element 310 via a through-hole.
  • a conductive layer 311 and the picture element 310 form capacitance therebetween. Interception of light to the transistor portion by the conductive layer 311 makes practicable the decrease of light leakage of the transistor.
  • the element substrate of the above construction is placed in opposition to an opposing substrate having a counter electrode and the like formed thereon, and a liquid crystal is sealed between them to provide a reflection type panel.
  • the picture element electrode 310 may be formed from aluminum or a like metal in the reflection type of liquid crystal display apparatus in this Example.
  • a liquid crystal display apparatus can be constructed without the conductive layer 311.
  • the contrast and gradation of the display apparatus can be improved by interception of light by a thin film transistor to decrease light leakage current.
  • the retention capacitance for retaining the potential of the picture element electrode 310 is also formed between the drain 308 and the substrate 301 with interposition of thin oxidation film 303.
  • the potential of the substrate is kept constant at at least a portion of the substrate.
  • the retention capacitance comprises the parallel capacitances between the drain 308 and the substrate 301, and the picture element electrode 310 and the conductive layer 311.
  • the characteristics of this Example is that the insulating film 303 between the substrate 301 and the drain 308 is thin, and the insulating film 302 between the 301 and the source 307 is thick to provide a display apparatus having a large retention capacitance and a small parasitic capacitance of the signal line.
  • the thin insulating film 303 constructed by thermal oxidation of the silicon substrate suppresses insulation breakdown and leakage even at application of a high electric field intensity, enabling decrease of the thickness thereof to increase further the retention capacities.
  • the thin insulating film 303 has a thickness ranging from 5 to 200nm (50 to 2000 ⁇ ) preferably from 50 to 150 nm (500 to 1500 ⁇ ), more preferably 70 to 100nm (700 to 1000 ⁇ ) and the thick insulating film 302 has a thickness ranging from 200 to 1500nm (2000 to 15000 ⁇ ), preferably from 200 to 1000nm (2000 to 10000 ⁇ ), more preferably 400 to 800 nm (4000 to 8000 ⁇ ).
  • a large parasitic capacitance of the signal line results in a large time constant. This causes the problem that driving of a display apparatus is not feasible when the number of the picture elements is increased or the display apparatus is made larger in size.
  • the parasitic capacitance of the signal line becomes larger, and the memory capacitance has to be increased, resulting in increase of the chip size, decrease of the number of the chips producible from one piece of wafer.
  • the source 307 and the signal line 309 are placed on the LOCOS oxidation film 302, thereby the parasitic capacitance of the signal line is made smaller.
  • a light-intercepting layer 311 is provided.
  • the light-intercepting layer 311 is not necessary when the capacitance formed between the drain 308 and the substrate 301 is sufficiently large.
  • the light can be intercepted by a black matrix on the side of the opposing substrate having a color filter or the like.
  • a high-brightness reflection type panel without a polarizer plate can be produced by arranging the picture element electrodes 310 in an oblique direction to the substrate 301 and using a polymer dispersion type liquid crystal layer between the picture element electrode and the opposing substrate.
  • An impurity diffusion layer 312 is provided to stabilize the retention capacitance between the drain 308 and the substrate 301.
  • the impurity diffusion layer 312 is of the same conduction type as that of the substrate 301, and inhibits expansion of the depletion layer under the drain 308 to avoid variation of the capacitance value.
  • a reversed capacitance can be formed by setting the potential of the substrate 301 to form reversion region under the drain 308. With the reversed capacitance, the capacitance is further stabilized by providing the impurity diffusion region of the conduction type opposite to the substrate in adjacent to the reversion region in order to supply the charges of the reversion region.
  • the wiring 313 can be formed to form a capacitance between the drain 308 and the wiring.
  • the wiring 313 is provided in one direction or in a checker pattern on the display portion to apply a potential at the periphery of the display portion.
  • the high concentration layer is formed by ion-implantation prior to formation of the wiring 313 and low concentration layer is formed after formation of the wiring 313 and the gate electrode 306 with high conformity with the process of a gate self aligning transistor.
  • This capacitance is connected to the capacitance between the drain 308 and the substrate 301 or the picture element 310 and the light-intercepting film 311 in parallel to increase further the retention capacitance.
  • a larger thickness of source-drain regions and smaller thickness of a channel region are effective for decreasing leakage current.
  • parasitic resistances between the channel and the source, and the channel and the drain may cause problems.
  • the parasitic resistance can be lowered by increasing the film thickness.
  • larger thickness of the source and drain portions is advantageous in that the contact resistance is lowered and the etching of the contact is facilitated.
  • Fig. 6 is a schematic partial sectional view of an example of an active matrix substrate of the liquid crystal display apparatus.
  • the same number as in Fig. 5 denotes the same thing, and explanation thereof is omitted.
  • a semiconductor region 412 is provided in the active matrix substrate in Fig. 6, .
  • the semiconductor layer constituting the source and drain is formed thicker than the semiconductor layer 304 constituting the channel region.
  • Such a construction as shown in Fig. 6 can be formed by patterning the semiconductor region 412 and then depositing the semiconductor layer 307.
  • the region 412 may be formed in the same conduction type as the source and drain by ion implantation before forming the semiconductor layer 307.
  • the impurity may be implanted at the same time as the ion implantation and diffusion in the source and the drain.
  • a transistor can be formed in which the leakage current is less and the driving force is stronger.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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Claims (10)

  1. Flüssigkristall-Anzeigevorrichtung mit einer Flüssigkristallschicht zwischen einem ersten Substrat und einem gegenüberliegenden Substrat, wobei das erste Substrat ausgerüstet ist mit:
    einem Halbleitersubstrat (301) ;
    einer Vielzahl von auf dem Halbleitersubstrat (301) gebildeten Transistoren, die alle ein Gate (306), eine Source (307) und ein Drain (308) haben;
    einer Vielzahl von mit den Sources (307) der Transistoren verbundenen Datensignalleitungen (309);
    einer Vielzahl von mit den Gates (306) der Transistoren verbundenen Abtastsignalleitungen;
    einer Vielzahl von jeweils mit dem Drain (308) eines jeweiligen Transistors verbundenen Bildelementelektroden (310), wobei das gegenüberliegende Substrat eine gegenüberliegende Elektrode enthält, die gegenüber den Bildelementelektroden (310) angeordnet ist;
    und mit einer Isolationsschicht (302, 303), die sich zwischen den Transistoren und dem Halbleitersubstrat (301) befindet,
       dadurch gekennzeichnet, daß
    die Dicke der Isolationsschicht (302) zwischen den Sources (307) der Transistoren und dem Halbleitersubstrat (301) größer ist als die Dicke der Isolationsschicht (303) zwischen den Drains (308) der Transistoren und dem Halbleitersubstrat (301), und daß eine Kapazität zwischen den Drains (308) der Transistoren und dem Halbleitersubstrat (301) gebildet ist.
  2. Flüssigkristall-Anzeigevorrichtung nach Anspruch 1, die des weiteren über eine elektrisch leitende Schicht (311) verfügt, um eine Kapazität mit den Bildelementelektroden (310) zu bilden, und über ein Mittel zum Anlegen eines vorgeschriebenen Potentials an die elektrisch leitende Schicht.
  3. Flüssigkristall-Anzeigevorrichtung nach Anspruch 1 oder 2, die des weiteren über eine periphere Schaltung zum Ansteuern der Transistoren verfügt, wobei wenigstens ein Abschnitt der peripheren Schaltung auf einem monokristallinen Substrat gebildet ist.
  4. Flüssigkristall-Anzeigevorrichtung nach einem der vorstehenden Ansprüche, deren Isolationsschicht (302) zwischen den Sources (307) und dem Halbleitersubstrat (301) eine Dicke im Bereich von 200 bis 1 500 nm (2 000 bis 15 000 Å) hat.
  5. Flüssigkristall-Anzeigevorrichtung nach Anspruch 4, deren Isolationsschicht (302) zwischen den Sources (307) und dem Halbleitersubstrat (301) eine Dicke im Bereich von 200 bis 1 000 nm (2 000 bis 10 000 Å) hat.
  6. Flüssigkristall-Anzeigevorrichtung nach Anspruch 5, deren Isolationsschicht (302) zwischen den Sources (307) und dem Halbleitersubstrat (301) eine Dicke im Bereich von 400 bis 800 nm (4 000 bis 8 000 Å) hat.
  7. Flüssigkristall-Anzeigevorrichtung nach einem der vorstehenden Ansprüche, deren Isolationsschicht (303) zwischen den Drains (308) und dem Halbleitersubstrat (301) eine Dicke im Bereich von 5 bis 200 nm (50 bis 2 000 Å) hat.
  8. Flüssigkristall-Anzeigevorrichtung nach Anspruch 7, deren Isolationsschicht (303) zwischen den Drains (308) und dem Halbleitersubstrat (301) eine Dicke im Bereich von 50 bis 150 nm (500 bis 1 500 Å) hat.
  9. Flüssigkristall-Anzeigevorrichtung nach Anspruch 8, deren Isolationsschicht (303) zwischen den Drains (308) und dem Halbleitersubstrat (301) eine Dicke im Bereich von 70 bis 100 nm (700 bis 1 000 Å) hat.
  10. Flüssigkristall-Anzeigevorrichtung nach einem der vorstehenden Ansprüche, bei der jeder Transistor eine Kanalzone (304) enthält, und ein Halbleiterschichtabschnitt, der die Sources (307) oder die Drains (308) bildet, eine größer Dicke hat als der Halbleiterschichtabschnitt, der die Kanalzonen (304) der Transistoren bildet.
EP96301495A 1995-03-06 1996-03-05 Flüssigkristall-Anzeigevorrichtung Expired - Lifetime EP0731375B1 (de)

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JP7044995 1995-03-06
JP70449/95 1995-03-06
JP7044995 1995-03-06

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EP0731375A3 EP0731375A3 (de) 1997-07-23
EP0731375B1 true EP0731375B1 (de) 2002-09-11

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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100386203B1 (ko) * 1996-02-29 2003-12-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 전기광학장치및그제조방법
US6288764B1 (en) 1996-06-25 2001-09-11 Semiconductor Energy Laboratory Co., Ltd. Display device or electronic device having liquid crystal display panel
JP3249077B2 (ja) * 1996-10-18 2002-01-21 キヤノン株式会社 マトリクス基板と液晶装置
US6262438B1 (en) 1996-11-04 2001-07-17 Semiconductor Energy Laboratory Co., Ltd. Active matrix type display circuit and method of manufacturing the same
GB9827901D0 (en) * 1998-12-19 1999-02-10 Secr Defence Active semiconductor
US7821065B2 (en) 1999-03-02 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a thin film transistor comprising a semiconductor thin film and method of manufacturing the same
US6346730B1 (en) * 1999-04-06 2002-02-12 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device having a pixel TFT formed in a display region and a drive circuit formed in the periphery of the display region on the same substrate
JP2001175198A (ja) 1999-12-14 2001-06-29 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US7525165B2 (en) 2000-04-17 2009-04-28 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
KR100815900B1 (ko) * 2001-12-20 2008-03-21 엘지.필립스 엘시디 주식회사 액정표시소자 및 그 제조방법
JP2003302649A (ja) * 2002-04-12 2003-10-24 Nec Lcd Technologies Ltd 液晶表示装置
TWI244060B (en) * 2003-06-12 2005-11-21 Ind Tech Res Inst A scan driving circuit with single-type transistors
JP2006330130A (ja) * 2005-05-24 2006-12-07 Mitsubishi Electric Corp 液晶表示装置およびその製造方法
TWI400785B (zh) * 2007-07-12 2013-07-01 Chunghwa Picture Tubes Ltd 主動元件陣列基板
KR101247092B1 (ko) * 2008-12-10 2013-03-25 샤프 가부시키가이샤 액티브 매트릭스 기판, 액티브 매트릭스 기판의 제조 방법, 액정 패널, 액정 패널의 제조 방법, 액정 표시 장치, 액정 표시 유닛, 텔레비전 수상기

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132191A (en) * 1981-02-10 1982-08-16 Suwa Seikosha Kk Active matrix substrate
WO1989002095A1 (en) * 1987-08-27 1989-03-09 Hughes Aircraft Company Lcmos displays fabricated with implant treated silicon wafers
JPH01134426A (ja) * 1987-11-20 1989-05-26 Hitachi Ltd 液晶デイスプレイ駆動用薄膜トランジスタ
JPH02198428A (ja) * 1989-01-27 1990-08-06 Nec Corp 液晶表示装置用アクティブマトリクス基板
JPH04226079A (ja) * 1990-04-17 1992-08-14 Canon Inc 半導体装置及びその製造方法及びそれを有する電子回路装置
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
US5372958A (en) * 1990-11-16 1994-12-13 Seiko Epson Corporation Process for fabricating a thin film semiconductor device
DE69332960T2 (de) * 1992-01-28 2004-05-13 Canon K.K. Halbleiteranordnung
JP3191061B2 (ja) * 1992-01-31 2001-07-23 キヤノン株式会社 半導体装置及び液晶表示装置
US5434441A (en) * 1992-01-31 1995-07-18 Canon Kabushiki Kaisha Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness
JP3526058B2 (ja) * 1992-08-19 2004-05-10 セイコーインスツルメンツ株式会社 光弁用半導体装置

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KR100205207B1 (ko) 1999-07-01
EP0731375A2 (de) 1996-09-11
DE69623518D1 (de) 2002-10-17
KR960035118A (ko) 1996-10-24
DE69623518T2 (de) 2003-05-22
US5726720A (en) 1998-03-10
EP0731375A3 (de) 1997-07-23

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