EP0656690B1 - Circuit à transistors - Google Patents

Circuit à transistors Download PDF

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Publication number
EP0656690B1
EP0656690B1 EP94118991A EP94118991A EP0656690B1 EP 0656690 B1 EP0656690 B1 EP 0656690B1 EP 94118991 A EP94118991 A EP 94118991A EP 94118991 A EP94118991 A EP 94118991A EP 0656690 B1 EP0656690 B1 EP 0656690B1
Authority
EP
European Patent Office
Prior art keywords
transistor
mos transistor
voltage
surge
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP94118991A
Other languages
German (de)
English (en)
Other versions
EP0656690A3 (fr
EP0656690A2 (fr
Inventor
Hiroshi C/O Intellectual Property Div. Shigehara
Masanori C/O Intellectual Property Div. Kinugasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0656690A2 publication Critical patent/EP0656690A2/fr
Publication of EP0656690A3 publication Critical patent/EP0656690A3/fr
Application granted granted Critical
Publication of EP0656690B1 publication Critical patent/EP0656690B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Definitions

  • the present invention relates to a circuit including an MOS transistor and, more particularly, to control of the drain-source breakdown voltage of an MOS transistor.
  • US-A-5 086 365 describes an electrostatic discharge protection circuit comprising an MOS transistor with an open back gate in which a parasitic bipolar transistor switches on to divert negative electrostatic discharge pulses to ground.
  • the avalanche breakdown voltage depends on the manufacturing process of semiconductor devices, such as the impurity concentration of the base, and cannot be changed once the device manufacturing process is determined.
  • a transistor circuit according to this invention comprises a MOS transistor with an open back gate, and control means for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor.
  • the present inventors discovered that the avalanche breakdown voltage of a parasitic bipolar transistor formed by the source, back gate (substrate) and drain of a MOS transistor is controllable by changing the gate voltage of this MOS transistor, and the present invention has been devised in view of this discovery. If the avalanche breakdown voltage is controllable, it is possible to prevent the avalanche breakdown of the parasitic bipolar transistor of the MOS transistor from occurring, permit the avalanche breakdown to occur at an early stage, or delay the occurrence of the avalanche breakdown as much as possible. This invention can therefore accomplish a promising transistor circuit which can be used in a variety of applications and is very advantageous.
  • the present inventors studies the avalanche breakdown voltage of a parasitic bipolar transistor constituted by the drain, back gate and source of a MOS transistor in a MOS-transistor based semiconductor circuit and discovered that if a voltage is applied between the drain and source of the transistor with its back gate (substrate) open and a gate voltage is further applied, the avalanche breakdown voltage of the parasitic bipolar transistor decreases.
  • Vds v.s. Ids characteristics are shown in FIG. 2.
  • B1 is an npn bipolar transistor, which parasitizes the NMOS transistor 1 and is constituted by the drain, back gate and source thereof.
  • FIG. 3 shows the characteristic curves of the breakdown voltage v.s. the gate potential as obtained from the characteristic curves in FIG. 2.
  • the possible reason why the avalanche breakdown has occurred at a low gate voltage as shown in FIGS. 2 and 3 is that the application of a positive gate voltage to the gate of the transistor N1 changes the energy band mode of the semiconductor surface directly under the gate and the charge distribution, and the sub threshold current flows directly below the gate, triggering the avalanche breakdown.
  • the breakdown voltage is controllable as in the case of the NMOS transistor by setting the gate potential lower than the source potential.
  • FIG. 4 is a circuit diagram of one embodiment of the present invention as adapted for a signal limiter.
  • the NMOS transistor N1 has a source connected to the ground potential (V SS ), a drain connected to a signal line 12 (e.g., the output line) and an open back gate (base of a parasitic bipolar transistor (not shown) constituted by the drain, back gate and source of the NMOS transistor N1), and a control signal is applied to the gate (control gate).
  • the output of a D/A (Digital-to-Analog) converter 11 is connected as the control signal to this control gate to digitally control the gate potential.
  • the D/A converter 11 may be replaced with some bias generator or the like.
  • the gate-source voltage Vgs is changed to permit the drain-source breakdown voltage to be controllable as shown in FIG. 3.
  • the circuit in FIG. 4 can therefore serve as a Zener diode which has a breakdown-voltage changing function. Even if the manufacturing process for the transistor N1 is fixed, therefore, the transistor N1 can have the desired avalanche breakdown voltage by controlling the gate input voltage. That is, the manufacturing process for the transistor N1 need not be altered to change the breakdown voltage.
  • FIG. 5 shows the case where the present invention is used in a protection circuit for the internal circuitry of a semiconductor device against the electrostatic discharge (ESD).
  • the present invention is applied only to the V SS side.
  • the NMOS transistor N1 has a source connected to the ground potential V SS , an open back gate (P well and the base of the parasitic bipolar transistor), and a gate connected to the base of an NPN transistor BP1.
  • the collector of the NPN transistor BP1 is connected to the drain of the NMOS transistor N1.
  • the base of the transistor BP1 is connected to the ground V SS via its own resistor component Rp (e.g., the resistor component up to the V SS -biasing portion of the P well).
  • the drain of the transistor N1 is connected to an external terminal 21 of an integrated circuit which constitutes the present circuit, and further to the gate of a MOS transistor T5, an element in the internal circuit.
  • FIG. 6 shows the case where the present invention is applied to the power supply V CC side as well as the V SS side. Even if V SS is open and only the supply voltage V CC is applied, a positive surge can be allowed to escape toward V CC . More specifically, when a transistor BP2 is turned on by the input positive surge, the gate potential of an NMOS transistor N2 rises and the avalanche breakdown voltage of the parasitic bipolar transistor of the transistor N2 drops, allowing the positive surge to escape toward V CC via the parasitic bipolar transistor the transistor BP2 and NMOS transistor N2.
  • the bipolar transistor BP1 may be accomplished by arranging N diffusion layers on a P substrate (well).
  • the bipolar transistors BP1 and BP2 may be accomplished by arranging N diffusion layers on P substrates (wells).
  • the structure of the NMOS transistor N1 and the bipolar transistor BP1 in FIG. 5 is as shown in FIG. 9.
  • the embodiment shown in FIG. 5 requires a P well structure on an N substrate 31 since it is necessary to separate the P substrate (well) 32 in which the NMOS transistor N1 is formed and the P substrate (well) 33 in which the bipolar transistor BP1 is formed from each other. Substantially the same is true to the embodiment shown in FIG. 6, though not shown.
  • the transistors BP1 and BP2 in FIGS. 5 and 6 may respectively be replaced with NMOS transistors N3 and N4 formed on a P well different from the P well of the NMOS transistors N1 and N2, as shown in FIGS. 7 and 8.
  • the sources and drains of those MOS transistors N3 and N4 correspond to the emitters and collectors of the bipolar transistors BP1 and BP2 in FIGS. 5 and 6, and the back gate (substrate) corresponds to the base.
  • the gates of the transistors N3 and N4 are connected to V SS to increase the breakdown voltages of the transistors, so that the transistors are set off.
  • the interval between the source and drain can be made narrower than that in the case where the N diffusion layers of the source and drain are simply set close to each other on the P substrate as shown in FIGS. 5 and 6, i.e., the base length can be shortened.
  • the surge escaping performance can therefore be improved.
  • the present invention is not limited to the above-described embodiments, but may be embodied in various other applications.
  • this invention is adapted for an NMOS transistor in the embodiments, this invention can also be adapted for a PMOS transistor in principle.
  • the avalanche breakdown voltage of a MOS transistor is controllable, it is possible to prevent the avalanche breakdown of the MOS transistor from occurring, permit the avalanche breakdown to occur at an early stage, or delay the occurrence of the avalanche breakdown as much as possible. This widens the fields of the application of MOS transistors, and can accomplish a transistor circuit which is very advantageous.
  • the avalanche breakdown between the drain and source of a MOS transistor with an open back gate is controllable so that the MOS transistor is permitted to function like a Zener diode having a breakdown-voltage changing function. By the utilization of this function, a lower breakdown voltage than the conventional one can be obtained so that a transistor circuit having a high electrostatic breakdown can be provided.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)

Claims (8)

  1. Circuit à transistors, comprenant :
    un transistor MOS (N1) ayant une contre-grille en circuit ouvert ; et
    un moyen de commande (11) permettant de commander la tension à appliquer à une grille de commande dudit transistor MOS, si bien que ledit moyen de commande commande la tension de claquage par avalanche d'un transistor bipolaire parasite formé par un drain, ladite contre-grille et une source dudit transistor MOS.
  2. Circuit à transistors selon la revendication 1, où le passage formant le canal dudit transistor MOS (N1) possède une extrémité connectée à une électrode d'alimentation électrique (VCC, VSS), son autre extrémité étant connectée à une ligne de signal.
  3. Circuit à transistors selon la revendication 1 ou 2, où ladite tension devant être appliquée à ladite grille de commande par ledit moyen de commande (11) est variable.
  4. Circuit à transistors selon la revendication 1, où ledit moyen de commande (11) comprend un moyen de détection de surtension (BP1, RP) connecté à une grille de commande dudit transistor MOS, afin de détecter une tension de surtension et d'appliquer à ladite grille de commande dudit transistor MOS une tension en fonction du résultat de la détection de ladite tension de surtension.
  5. Circuit à transistors selon la revendication 4, où ledit moyen de détection de surtension (BP1, RP) comprend un transistor bipolaire (BP1) et une résistance (RP) se trouvant entre une base dudit transistor bipolaire et l'une des électrodes d'alimentation électrique (VCC, VSS), un élément parmi le collecteur et l'émetteur dudit transistor bipolaire et une extrémité du passage de canal dudit transistor MOS (N1) sont connectés au moins à une borne externe (21) d'un circuit intégré constituant ledit transistor MOS (N1) et ledit moyen de détection de surtension, et l'autrc élément parmi ledit collecteur et ledit émetteur dudit transistor bipolaire et l'autre extrémité dudit passage de canal dudit transistor MOS sont connectés à l'une desdites électrodes d'alimentation électrique (VCC, VSS).
  6. Circuit à transistors selon la revendication 5, comprenant en outre :
    un deuxième transistor MOS (N2) ayant une contre-grille en circuit ouvert ; et
    un deuxième moyen de détection de surtension (BP2, RP2), connecté à une grille de commande dudit deuxième transistor MOS, afin de détecter une tension de surtension et d'appliquer à ladite grille de commande dudit deuxième transistor MOS une tension en fonction du résultat de la détection de ladite tension de surtension, ledit deuxième moyen de détection de surtension (BP2, RP2) comportant un deuxième transistor bipolaire (BP2) et une deuxième résistance (RP2) se trouvant entre une base dudit transistor bipolaire et l'une des électrodes d'alimentation électrique (VCC, VSS), un élément parmi le collecteur et l'émetteur dudit deuxième transistor bipolaire et une extrémité d'un passage de canal dudit deuxième transistor MOS (N2) étant connectés au moins à une borne externe dudit circuit intégré, et l'autre élément parmi ledit collecteur et ledit émetteur dudit deuxième transistor bipolaire et l'autre extrémité dudit passage de canal dudit deuxième transistor MOS étant connectés à l'autre desdites électrodes d'alimentation électrique (VCC, VSS),
    si bien que chacun desdits moyens de détection de surtension commande respectivement les tensions de claquage par avalanche d'un transistor bipolaire parasite formé par un drain, ladite contre-grille et la source dudit transistor MOS respectif.
  7. Circuit à transistors selon la revendication 5, où ledit moyen de détection de surtension (BP1, RP) est constitué par un transistor bipolaire parasite d'un transistor MOS, et ledit transistor bipolaire parasite est utilisé au titre dudit transistor bipolaire (BP1) dudit moyen de détection de surtension.
  8. Circuit à transistors selon la revendication 6, où chacun desdits moyens de détection de surtension (BP1, RP1 ; BP2, RP2) est constitué par un transistor bipolaire parasite respectif d'un transistor MOS (N1, N2), et lesdits transistors parasites bipolaires sont respectivement utilisés au titre du transistor bipolaire mentionné en premier (BP1) et du deuxième transistor bipolaire (BP2).
EP94118991A 1993-12-02 1994-12-01 Circuit à transistors Expired - Lifetime EP0656690B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP302820/93 1993-12-02
JP5302820A JP2965840B2 (ja) 1993-12-02 1993-12-02 トランジスタ回路

Publications (3)

Publication Number Publication Date
EP0656690A2 EP0656690A2 (fr) 1995-06-07
EP0656690A3 EP0656690A3 (fr) 1996-03-20
EP0656690B1 true EP0656690B1 (fr) 1998-05-06

Family

ID=17913492

Family Applications (1)

Application Number Title Priority Date Filing Date
EP94118991A Expired - Lifetime EP0656690B1 (fr) 1993-12-02 1994-12-01 Circuit à transistors

Country Status (5)

Country Link
US (1) US5539327A (fr)
EP (1) EP0656690B1 (fr)
JP (1) JP2965840B2 (fr)
KR (1) KR0137415B1 (fr)
DE (1) DE69410067T2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MD3946G2 (ro) * 2003-06-16 2010-02-28 Techcom Import Export Gmbh Dispozitiv al gurii de vânt pentru introducerea mediilor gazoase sub un strat de metal lichid

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789785A (en) * 1995-02-28 1998-08-04 Sgs-Thomson Microelectronics S.R.L. Device for the protection of an integrated circuit against electrostatic discharges
JPH08274184A (ja) * 1995-03-31 1996-10-18 Toshiba Microelectron Corp 半導体集積回路の保護回路装置
US6108181A (en) * 1996-04-23 2000-08-22 Motorola Inc. Electrostatic discharge (ESD) circuit
SE512494C2 (sv) * 1997-09-02 2000-03-27 Ericsson Telefon Ab L M Skyddskrets
EP0903828A1 (fr) * 1997-09-23 1999-03-24 STMicroelectronics S.r.l. Dispositif perfectionné pour la protection d'un circuit intégré contre des décharges électrostatiques
US5917336A (en) * 1997-09-29 1999-06-29 Motorola, Inc. Circuit for electrostatic discharge (ESD) protection
US5903419A (en) * 1997-09-29 1999-05-11 Motorola, Inc. Circuit for electrostatic discharge (ESD) protection
US6046897A (en) * 1997-09-29 2000-04-04 Motorola, Inc. Segmented bus architecture (SBA) for electrostatic discharge (ESD) protection
US6049119A (en) * 1998-05-01 2000-04-11 Motorola, Inc. Protection circuit for a semiconductor device
US6653669B2 (en) * 1999-06-28 2003-11-25 Stmicroelectronics Sa Device for the adjustment of circuits after packaging
FR2795557B1 (fr) * 1999-06-28 2001-09-21 St Microelectronics Sa Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant
FR2799885B1 (fr) * 1999-10-05 2002-01-11 St Microelectronics Sa Potentiometre integre et procede de fabrication correspondant
US7629210B2 (en) * 2000-05-15 2009-12-08 Nec Corporation Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction
US20010043449A1 (en) * 2000-05-15 2001-11-22 Nec Corporation ESD protection apparatus and method for fabricating the same
US6815775B2 (en) * 2001-02-02 2004-11-09 Industrial Technology Research Institute ESD protection design with turn-on restraining method and structures
JP4199476B2 (ja) * 2002-04-12 2008-12-17 株式会社ルネサステクノロジ 半導体装置の保護回路
US7244992B2 (en) * 2003-07-17 2007-07-17 Ming-Dou Ker Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection
US20060132187A1 (en) * 2004-12-20 2006-06-22 Tschanz James W Body biasing for dynamic circuit
TWI329965B (en) * 2006-06-20 2010-09-01 Via Tech Inc Voltage pull-up device
US11303116B2 (en) * 2018-08-29 2022-04-12 Allegro Microsystems, Llc Methods and apparatus for electrical overstress protection

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577969A (en) * 1980-06-18 1982-01-16 Toshiba Corp Semiconductor integrated circuit
JPS6150358A (ja) * 1984-08-20 1986-03-12 Toshiba Corp 半導体集積回路
US4789917A (en) * 1987-08-31 1988-12-06 National Semiconductor Corp. MOS I/O protection using switched body circuit design
JPH07105446B2 (ja) * 1988-01-11 1995-11-13 株式会社東芝 Ｍｏｓ型半導体装置の入力保護回路
US4829350A (en) * 1988-05-05 1989-05-09 National Semiconductor Corporation Electrostatic discharge integrated circuit protection
US5086365A (en) * 1990-05-08 1992-02-04 Integrated Device Technology, Inc. Electostatic discharge protection circuit
JP3321188B2 (ja) * 1991-07-26 2002-09-03 株式会社東芝 出力回路
JPH05167427A (ja) * 1991-12-13 1993-07-02 Toshiba Corp レベルシフト回路
US5389811A (en) * 1994-04-14 1995-02-14 Analog Devices, Incorporated Fault-protected overvoltage switch employing isolated transistor tubs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MD3946G2 (ro) * 2003-06-16 2010-02-28 Techcom Import Export Gmbh Dispozitiv al gurii de vânt pentru introducerea mediilor gazoase sub un strat de metal lichid

Also Published As

Publication number Publication date
DE69410067D1 (de) 1998-06-10
DE69410067T2 (de) 1998-10-01
JPH07161973A (ja) 1995-06-23
KR0137415B1 (ko) 1998-06-15
KR950022127A (ko) 1995-07-26
JP2965840B2 (ja) 1999-10-18
US5539327A (en) 1996-07-23
EP0656690A3 (fr) 1996-03-20
EP0656690A2 (fr) 1995-06-07

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