FR2795557B1 - Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant - Google Patents

Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant

Info

Publication number
FR2795557B1
FR2795557B1 FR9908240A FR9908240A FR2795557B1 FR 2795557 B1 FR2795557 B1 FR 2795557B1 FR 9908240 A FR9908240 A FR 9908240A FR 9908240 A FR9908240 A FR 9908240A FR 2795557 B1 FR2795557 B1 FR 2795557B1
Authority
FR
France
Prior art keywords
packaging
manufacturing
adjustment device
circuit adjustment
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9908240A
Other languages
English (en)
Other versions
FR2795557A1 (fr
Inventor
Christophe Forel
Sebastien Laville
Serge Pontarollo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR9908240A priority Critical patent/FR2795557B1/fr
Priority to US09/604,989 priority patent/US6410398B1/en
Publication of FR2795557A1 publication Critical patent/FR2795557A1/fr
Application granted granted Critical
Publication of FR2795557B1 publication Critical patent/FR2795557B1/fr
Priority to US10/121,427 priority patent/US6653669B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66166—Resistors with PN junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605—Resistors with PN junctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR9908240A 1999-06-28 1999-06-28 Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant Expired - Fee Related FR2795557B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9908240A FR2795557B1 (fr) 1999-06-28 1999-06-28 Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant
US09/604,989 US6410398B1 (en) 1999-06-28 2000-06-28 Device for the adjustment of circuits after packaging, corresponding fabrication process and induction device
US10/121,427 US6653669B2 (en) 1999-06-28 2002-04-12 Device for the adjustment of circuits after packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9908240A FR2795557B1 (fr) 1999-06-28 1999-06-28 Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant

Publications (2)

Publication Number Publication Date
FR2795557A1 FR2795557A1 (fr) 2000-12-29
FR2795557B1 true FR2795557B1 (fr) 2001-09-21

Family

ID=9547382

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9908240A Expired - Fee Related FR2795557B1 (fr) 1999-06-28 1999-06-28 Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant

Country Status (2)

Country Link
US (1) US6410398B1 (fr)
FR (1) FR2795557B1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653669B2 (en) * 1999-06-28 2003-11-25 Stmicroelectronics Sa Device for the adjustment of circuits after packaging
FR2820881B1 (fr) * 2001-02-12 2004-06-04 St Microelectronics Sa Dispositif d'ajustement des circuits avant mise en boitier
US6882214B2 (en) * 2003-05-16 2005-04-19 O2Micro International Limited Circuit and method for trimming locking of integrated circuits
EP1482554B1 (fr) * 2003-05-28 2006-03-01 Interuniversitair Microelektronica Centrum ( Imec) Dispositif de protection contre les décharges électrostatiques
FR2879814A1 (fr) * 2004-12-17 2006-06-23 St Microelectronics Sa Circuit ajustable apres encapsulation et comprenant un limiteur de tension, et procede d'ajustement d'un tel circuit
US20080157291A1 (en) * 2006-12-27 2008-07-03 Texas Instruments Inc. Packaging implementation while mitigating threshold voltage shifting
US7715219B2 (en) * 2008-06-30 2010-05-11 Allegro Microsystems, Inc. Non-volatile programmable memory cell and memory array
TW201013925A (en) * 2008-09-17 2010-04-01 Grand Gem Semiconductor Co Ltd MOS transistor having reverse current limiting and a voltage converter applied with the MOS transistor
US20170085078A1 (en) * 2015-09-18 2017-03-23 Texas Instruments Incorporated Hot plug immunity for circuit protecting against electrostatic discharge events

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542348A (en) * 1978-09-19 1980-03-25 Sharp Corp Junction destructive type programmable rom
US5065132A (en) * 1990-11-16 1991-11-12 Texas Instruments Incorporated Programmable resistor and an array of the same
JP2965840B2 (ja) * 1993-12-02 1999-10-18 株式会社東芝 トランジスタ回路
US6169309B1 (en) * 1997-09-30 2001-01-02 Texas Instruments Incorporated High breakdown-voltage transistor with transient protection

Also Published As

Publication number Publication date
FR2795557A1 (fr) 2000-12-29
US6410398B1 (en) 2002-06-25

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090228