EP0602197B1 - Integrierter cmos-halbleiterschaltkreis - Google Patents
Integrierter cmos-halbleiterschaltkreis Download PDFInfo
- Publication number
- EP0602197B1 EP0602197B1 EP93909782A EP93909782A EP0602197B1 EP 0602197 B1 EP0602197 B1 EP 0602197B1 EP 93909782 A EP93909782 A EP 93909782A EP 93909782 A EP93909782 A EP 93909782A EP 0602197 B1 EP0602197 B1 EP 0602197B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- supply voltage
- voltage
- semiconductor circuit
- integrated semiconductor
- accordance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005516 engineering process Methods 0.000 claims description 4
- 230000001419 dependent effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 22
- 238000005265 energy consumption Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000036316 preload Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 108010076282 Factor IX Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
- H01L27/0222—Charge pumping, substrate bias generation structures
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/205—Substrate bias-voltage generators
Definitions
- the invention relates to an integrated semiconductor circuit in CMOS technology and a data processing system, which are characterized by low energy consumption.
- the present invention addresses the problem an integrated semiconductor circuit and a data processing system to create that in addition to the already known measures further energy savings and thus an even longer off-grid Operation enables.
- CMOS transistor pairs As possible a semiconductor chip be designed such that they are stable to operate, i.e. at certain predetermined supply voltages work the Transistors with different speeds, however in the range of the circuit arrangement given working points. This is accomplished by any supply voltage necessary for the operation of the Transistors is selected, an associated threshold voltage has that over the tub bias and the substrate bias is adjustable. Usually two supply voltages are selected, the become clear in terms of energy consumption for the circuits and the clock frequency differ, and between which is switched back and forth. But it is also conceivable, additional tension values in between to select.
- the setting is made using a substrate bias generator circuit, the one with the substrate and one Pan bias generator circuit that matches the pan each transistor pair is connected.
- These generator circuits depending on an input signal, that represents the level of the supply voltage, the respective, the level of the supply voltage appropriate bias to the threshold voltage adjust accordingly.
- the input signal can preferably by means of a voltage detector be generated. This ensures that as soon as the supply voltage changes as quickly as possible the new operating point with a corresponding threshold voltage is set. This can be done on the one hand Switching from supply voltage to battery voltage or to an internal voltage because of the current operation no higher voltage required is done.
- the supply voltages should be approximately 3.6 V for high power and 1.2 V for low power, at least when it comes to integrated semiconductor circuits for portable PCs.
- the present invention is fundamentally applicable when it is a matter of reducing a supply voltage to another supply voltage.
- the reduction in the supply voltage can be a factor of 2 or more, depending on how high the output supply voltage value is.
- the doping of the substrate should advantageously have a concentration below the surface of 7.5x10 15 to 4x10 16 cm -3 , preferably 2.5x10 16 cm -3 , so that the transistors at any desired supply voltage in the range around 3.6 V and 1 , 2 V and the corresponding threshold voltage can work stably.
- the data processing system such as Personal computer (PC) and in particular portable PC, has at least one integrated semiconductor circuit with the properties described above so that in addition to those already in the stand measures known in the art of energy can be saved can what is happening with the portable PCs in a pays significantly longer grid independence, however also beneficial for the operator and in network operation the environment is because the data processing system only then works with high voltage if it is due to the operations to be performed immediately is required.
- the generation of the input signal can on the semiconductor integrated circuit or also by other elements of the data processing system respectively. For example, a voltage detector on the semiconductor integrated circuit provided directly or in another system unit be.
- the control can also be dependent on the duration of the non-use of the associated input unit done what in combination with the controller depending on the utilization of the integrated Semiconductor circuit even more energy savings brings.
- the integrated semiconductor circuit according to the invention is provided by providing your own Power supply for setting the threshold voltage in addition to the circuit supply voltage created an easy way one Data processing system to create that with a very low voltage for most applications is fully functional without the user noticing Reduced performance, and on the other hand can also be operated at full capacity.
- the portable PCs too think that disconnected from the supply network with a Battery voltage can be operated from 1.1 to 1.2 V. can, then the battery has a long service life allowed, or with a battery voltage of approx. 3.3 to 3.6 V, which is a relatively short operating time only enables (parallel or series connection of individual Battery cells).
- the well-known structure is one CMOS transistor pair on ap substrate 2 and one n-well 4, as well as the n-doped drain and source regions 6, 8 in the p-substrate 2 and the p-doped Drain and source regions 12, 14 in the n-well 4 shown. In between are the corresponding ones Gate connections 10 and 16. substrate and well also have electrical connections 18 and 20, respectively.
- n-well process In which the n-transistor in a p-well and the p-transistor are arranged in the substrate, and for the twin-tub process, in which the p-transistor in an n-well and n-transistor are arranged in a p-well.
- the measure according to the invention contributes to the Voltage reduction from 3.6 V to 1.2 V with one Factor 9 only to reduce the power loss.
- FIG. 2 shows schematically an example in a block diagram the voltage detector 22, which on the respective semiconductor chip or also removed therefrom can be provided and depending on each supply voltage an input signal for outputs the bias generators 24 and 26.
- the Well bias generator 24 gives a corresponding one Output voltage Vw for the tub and the Substrate bias generator 26 a corresponding Voltage Vs for the substrate.
- the provision These voltages can be taken for granted on a PC once for all affected semiconductor chips correspondingly provided voltage distribution systems and doped CMOS transistor pairs.
- FIG 3 is an example of a circuit for the Bias generators 24 and 26 in CMOS technology shown.
- the pan bias generator circuit are the complementary transistors T1 and T2 in series between the supply voltage Vdd and Gnd, where the p-transistor T1 with Vdd and the n-transistor T2 is connected to Gnd.
- the two Control electrodes of the transistors are connected to a ring oscillator 28 connected, the impulses in one wide frequency range according to the dimensioning the circuits deliver (preferred range 1 MHz ... 100 MHz).
- the circuit for the substrate bias generator 26 is constructed in a similar way.
- the transistors T1 and T2 corresponding transistors T3 and T4, whose Control electrodes connected to the ring oscillator 28 are connected in series between Vdd and Gnd.
- a capacitor C2n is connected in series between Vdd and Gnd and two p-transistors D3 and D4 connected, the control electrodes with the node K5 connected between the two transistors or Gnd are.
- the node K4 between the transistors T3 and T4 is connected to node K5 via capacitor Cln.
- the node K6 is between the Capacitor C2n and transistor D3 via a as Diode connected p-transistor D6 connected to Gnd, whose control electrode is also at the potential of the Node K6 lies.
- the potential of the node K6 represents represents the substrate bias Vs.
- the circuit for the pan bias generator 24 works in such a way that via the ring oscillator 28 a sequence of rectangular pulses to the control electrodes of the transistors T1 and T2.
- the transistor T2 switches with the positive edge by and the supply voltage Vdd is reduced the voltage drops across transistor T2 and D1, applied to the capacitor Clp.
- With the transistor T1 switches through on the negative edge and the charge of the capacitor Clp flows partially on the capacitor C2p.
- the voltage at node K2 (VK2) and thus the voltage across C2p can Reach values that are above Vdd (theoretically: VK2 ⁇ 2 Vdd).
- the capacitor must be used first Clp be reloaded, so that the tension on Capacitor C2p around the voltage drops at the Transistors T1 and D2 reduced. With every impulse capacitor C2p is charged higher, however through the transistor D5 connected as a diode Voltage across capacitor C2p and thus the output voltage is limited to a voltage for the tub, which is increased by the diode forward voltage.
- the circuit for the substrate bias works accordingly. With the positive edge, the Transistor T4 through and capacitor C2n turns on a voltage corresponding to the capacities of the from the Capacitors Cln and C2n formed voltage divider minus the voltage drops across the transistors T4 and D3 charged. After switching through the Transistor T3 through the negative edge of the rectangular pulse the capacitor is at a maximum of around the Voltage drops across transistors T3 and D4 reduced supply voltage Vdd reloaded. With the The next positive pulse is again the transistor T4 switched through and thus the node K4 and simultaneously the electrode of the capacitor C1n to Gnd potential placed.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
- Fig. 1
- die schematische Struktur eines CMOS-Transistorpaares;
- Fig. 2
- ein Blockschaltbild für die Bereitstellung der Vorspannungen; und
- Fig. 3
- die Vorspannungsgeneratorsschaltungen zur Erzeugung der jeweiligen Vorspannung.
- Vdd =
- positive Versorgungsspannung,
- Vss =
- negative Versorgungsspannung,
- VthN =
- Schwellwertspannung am n-Transistor,
- VthP =
- Schwellwertspannung am p-Transistor,
- Vs =
- Substratvorspannung,
- Vw =
- Wannenvorspannung
- Vdd = 3,6 V : VthN = 0,55 V, VthP = -0,55 V
- Vdd = 1,2 V : VthN = 0,3 V, VthP = -0,3 V
- Vss = GND
Vdd = 3,6 V | Vdd = 1,2 V |
Vss = 0 V | Vss = 0 V |
n-Wanne | 4,3 V | 1,2 V |
Source (P) | 3,6 V | 1,2 V |
Source (N) | 0,0 V | 0,0 V |
p-Substrat | -0,7 V | 0,0 V. |
- C1p =
- 5pF,
- C2p =
- 5nF,
- C1n =
- 5pF, und
- C2n =
- 5nF.
Claims (8)
- Integrierter Halbleiterschaltkreis in CMOS-Technik der mit verschiedenen Versorgungsspannungen (Vdd) stabil betreibbar ist, indem die Schwellwertspannung der beteiligten CMOS-Transistorpaare entsprechend der jeweils anliegenden Versorgungsspannung über die Wannen- und die Substratvorspannung (Vw, Vs) einstellbar ist, wobei das Substrat (2) des CMOS-Transistorpaares mit einer Substratvorspannungsgeneratorschaltung (SVG) und die Wanne mit einer Wannenvorspannungsgeneratorschaltung (WVG) verbunden ist, die in Abhängigkeit von einem Eingangssignal, das die Höhe der Versorgungsspannung repräsentiert, die jeweilige, der Höhe der Versorgungsspannung entsprechende Vorspannung einstellt, um die Schwellwertspannung derart an die jeweilige Versorgungsspannung anzupassen, daß immer ein stabiler Betrieb des Transistorpaares gewährleistet ist, wobei die Versorgungsspannung in Abhängigkeit von der Taktfrequenz einstellbar ist und bei höherer Taktfrequenz eine höhere Versorgungsspannung anliegt und bei reduzierter Taktfrequenz eine geringere Versorgungsspannung anliegt.
- Integrierter Halbleiterschaltkreis nach Anspruch 1 bei dem ein Spannungsdetektor (SD) das Eingangssignal für die Vorspannungsgeneratorschaltungen erzeugt.
- Integrierter Halbleiterschaltkreis nach Anspruch 1 oder 2 bei dem ein stabiler Betrieb bei einer Versorgungsspannung (Vdd) von ungefähr 3,6 V und ungefähr 1,2 V erfolgt.
- Integrierter Halbleiterschaltkreis nach Anspruch 3 bei dem das Substrat (2) unterhalb der Oberfläche mit einer ungefähren Konzentration von 7,5x1015 cm-3 bis 4x1016 cm-3, vorzugsweise 2,5x1016 cm-3 dotiert ist.
- Integrierter Halbleitschaltkreis nach einem der vorangegangenen Ansprüche 1 bis 4 der mit einer Versorgungsspannung (Vd) von ungefähr 3,6 V bei maximaler Taktfrequenz und mit einer Versorgungsspannung von ungefähr 1,2 V bei reduzierter Taktfrequenz betrieben wird.
- Integrierter Halbschalterkreis nach einem der vorangegangen Ansprüche 1 bis 5 bei dem die Versorgungsspannung (Vd) und damit auch das Eingangssignal für die Vorspannungsgeneratorschaltungen in Abhängigkeit von der Auslastung des integrierten Halbleiterschaltkreises steuerbar ist.
- Integrierter Halbleiterschaltkreis nach einem der vorangegangen Ansprüche 1 bis 5 bei dem die Versorgungsspannung (Vd) und das Eingangssignal von der Dauer der Nichtbenutzung der zugehörigen Eingabeeinheit abhängig ist.
- Datenverarbeitungssystem, mit wenigstens einem integrierten Halbleiterschaltkreis in CMOS-Technik nach einem der vorangegangenen Ansprüche 1-7.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4221575 | 1992-07-01 | ||
DE4221575A DE4221575C2 (de) | 1992-07-01 | 1992-07-01 | Integrierter CMOS-Halbleiterschaltkreis und Datenverarbeitungssystem mit integriertem CMOS-Halbleiterschaltkreis |
PCT/DE1993/000443 WO1994001890A1 (de) | 1992-07-01 | 1993-05-21 | Integrierter cmos-halbleiterschaltkreis |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0602197A1 EP0602197A1 (de) | 1994-06-22 |
EP0602197B1 true EP0602197B1 (de) | 1999-04-28 |
Family
ID=6462228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93909782A Expired - Lifetime EP0602197B1 (de) | 1992-07-01 | 1993-05-21 | Integrierter cmos-halbleiterschaltkreis |
Country Status (4)
Country | Link |
---|---|
US (1) | US5744996A (de) |
EP (1) | EP0602197B1 (de) |
DE (2) | DE4221575C2 (de) |
WO (1) | WO1994001890A1 (de) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2717918B1 (fr) * | 1994-03-25 | 1996-05-24 | Suisse Electronique Microtech | Circuit pour contrôler les tensions entre caisson et sources des transistors mos et système d'asservissement du rapport entre les courants dynamique et statique d'un circuit logique mos. |
US5907255A (en) * | 1997-03-25 | 1999-05-25 | Cypress Semiconductor | Dynamic voltage reference which compensates for process variations |
JP3802239B2 (ja) * | 1998-08-17 | 2006-07-26 | 株式会社東芝 | 半導体集積回路 |
US6362687B2 (en) | 1999-05-24 | 2002-03-26 | Science & Technology Corporation | Apparatus for and method of controlling amplifier output offset using body biasing in MOS transistors |
US6633197B1 (en) | 2000-10-27 | 2003-10-14 | Marvell International, Ltd. | Gate capacitor stress reduction in CMOS/BICMOS circuit |
CN1286269C (zh) * | 2002-01-23 | 2006-11-22 | 皇家飞利浦电子股份有限公司 | 集成电路和电池供电的电子设备 |
US7941675B2 (en) * | 2002-12-31 | 2011-05-10 | Burr James B | Adaptive power control |
US7180322B1 (en) | 2002-04-16 | 2007-02-20 | Transmeta Corporation | Closed loop feedback control of integrated circuits |
US6731158B1 (en) | 2002-06-13 | 2004-05-04 | University Of New Mexico | Self regulating body bias generator |
US7949864B1 (en) * | 2002-12-31 | 2011-05-24 | Vjekoslav Svilan | Balanced adaptive body bias control |
US7228242B2 (en) | 2002-12-31 | 2007-06-05 | Transmeta Corporation | Adaptive power control based on pre package characterization of integrated circuits |
US7953990B2 (en) * | 2002-12-31 | 2011-05-31 | Stewart Thomas E | Adaptive power control based on post package characterization of integrated circuits |
US7085942B2 (en) * | 2003-05-21 | 2006-08-01 | Agilent Technologies, Inc. | Method and apparatus for defining an input state vector that achieves low power consumption in a digital circuit in an idle state |
US7129771B1 (en) * | 2003-12-23 | 2006-10-31 | Transmeta Corporation | Servo loop for well bias voltage source |
US7012461B1 (en) | 2003-12-23 | 2006-03-14 | Transmeta Corporation | Stabilization component for a substrate potential regulation circuit |
US7649402B1 (en) * | 2003-12-23 | 2010-01-19 | Tien-Min Chen | Feedback-controlled body-bias voltage source |
US7692477B1 (en) | 2003-12-23 | 2010-04-06 | Tien-Min Chen | Precise control component for a substrate potential regulation circuit |
US7129745B2 (en) * | 2004-05-19 | 2006-10-31 | Altera Corporation | Apparatus and methods for adjusting performance of integrated circuits |
US7348827B2 (en) * | 2004-05-19 | 2008-03-25 | Altera Corporation | Apparatus and methods for adjusting performance of programmable logic devices |
US7562233B1 (en) | 2004-06-22 | 2009-07-14 | Transmeta Corporation | Adaptive control of operating and body bias voltages |
US7774625B1 (en) | 2004-06-22 | 2010-08-10 | Eric Chien-Li Sheng | Adaptive voltage control by accessing information stored within and specific to a microprocessor |
US20060119382A1 (en) * | 2004-12-07 | 2006-06-08 | Shumarayev Sergey Y | Apparatus and methods for adjusting performance characteristics of programmable logic devices |
US7495471B2 (en) * | 2006-03-06 | 2009-02-24 | Altera Corporation | Adjustable transistor body bias circuitry |
US7355437B2 (en) | 2006-03-06 | 2008-04-08 | Altera Corporation | Latch-up prevention circuitry for integrated circuits with transistor body biasing |
US7330049B2 (en) * | 2006-03-06 | 2008-02-12 | Altera Corporation | Adjustable transistor body bias generation circuitry with latch-up prevention |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4115710A (en) * | 1976-12-27 | 1978-09-19 | Texas Instruments Incorporated | Substrate bias for MOS integrated circuit |
US4142114A (en) * | 1977-07-18 | 1979-02-27 | Mostek Corporation | Integrated circuit with threshold regulation |
US4229667A (en) * | 1978-08-23 | 1980-10-21 | Rockwell International Corporation | Voltage boosting substrate bias generator |
JPS6159688A (ja) * | 1984-08-31 | 1986-03-27 | Hitachi Ltd | 半導体集積回路装置 |
NL8402764A (nl) * | 1984-09-11 | 1986-04-01 | Philips Nv | Schakeling voor het opwekken van een substraatvoorspanning. |
JPS6442850A (en) * | 1987-08-10 | 1989-02-15 | Nec Corp | On-chip substrate voltage generating circuit |
US4794278A (en) * | 1987-12-30 | 1988-12-27 | Intel Corporation | Stable substrate bias generator for MOS circuits |
JPH01253264A (ja) * | 1988-03-31 | 1989-10-09 | Sharp Corp | 半導体集積回路 |
JP3105512B2 (ja) * | 1989-08-25 | 2000-11-06 | 日本電気株式会社 | Mos型半導体集積回路 |
JP2557271B2 (ja) * | 1990-04-06 | 1996-11-27 | 三菱電機株式会社 | 内部降圧電源電圧を有する半導体装置における基板電圧発生回路 |
-
1992
- 1992-07-01 DE DE4221575A patent/DE4221575C2/de not_active Expired - Fee Related
-
1993
- 1993-05-21 US US08/387,705 patent/US5744996A/en not_active Expired - Lifetime
- 1993-05-21 WO PCT/DE1993/000443 patent/WO1994001890A1/de active IP Right Grant
- 1993-05-21 DE DE59309544T patent/DE59309544D1/de not_active Expired - Fee Related
- 1993-05-21 EP EP93909782A patent/EP0602197B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE4221575C2 (de) | 1995-02-09 |
DE59309544D1 (de) | 1999-06-02 |
US5744996A (en) | 1998-04-28 |
WO1994001890A1 (de) | 1994-01-20 |
EP0602197A1 (de) | 1994-06-22 |
DE4221575A1 (de) | 1994-01-05 |
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