JPS6442850A - On-chip substrate voltage generating circuit - Google Patents

On-chip substrate voltage generating circuit

Info

Publication number
JPS6442850A
JPS6442850A JP62200207A JP20020787A JPS6442850A JP S6442850 A JPS6442850 A JP S6442850A JP 62200207 A JP62200207 A JP 62200207A JP 20020787 A JP20020787 A JP 20020787A JP S6442850 A JPS6442850 A JP S6442850A
Authority
JP
Japan
Prior art keywords
voltage generating
generating circuit
clock
circuits
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62200207A
Other languages
Japanese (ja)
Inventor
Toshio Takeshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62200207A priority Critical patent/JPS6442850A/en
Publication of JPS6442850A publication Critical patent/JPS6442850A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To prevent the extreme increase in power supply current as well as the decline in the operational margin from occurring even in high operational frequency by a method wherein clock frequency detecting circuits and negative voltage generating circuits are combined with one another to be used in multiple pairs. CONSTITUTION:The title voltage generating circuit is composed of two clock frequency detecting circuits D1 and D2, and three negative voltage generating circuits G0, G1 and G2. In such a constitution, the clock frequency detecting circuits D1 and D2 perform the function to output '1' level to their output terminals whenever the frequency f of chip driving signal CE respectively exceed f1 and f2. Furthermore, when a control terminal ai (i=0-2) in a negative generating circuit Gi (i=0-2) is impressed with '1' level (power supply level), a clock generated by a clock generator 21 is impressed on a voltage generator 22 to generate a negative voltage at the output terminal bi (i=0-2) thereof. Through these procedures, the substrate voltage Vsub can be generated stably up to high operational frequency f.
JP62200207A 1987-08-10 1987-08-10 On-chip substrate voltage generating circuit Pending JPS6442850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62200207A JPS6442850A (en) 1987-08-10 1987-08-10 On-chip substrate voltage generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62200207A JPS6442850A (en) 1987-08-10 1987-08-10 On-chip substrate voltage generating circuit

Publications (1)

Publication Number Publication Date
JPS6442850A true JPS6442850A (en) 1989-02-15

Family

ID=16420587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62200207A Pending JPS6442850A (en) 1987-08-10 1987-08-10 On-chip substrate voltage generating circuit

Country Status (1)

Country Link
JP (1) JPS6442850A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744996A (en) * 1992-07-01 1998-04-28 International Business Machines Corporation CMOS integrated semiconductor circuit
JP2009181638A (en) * 2008-01-30 2009-08-13 Elpida Memory Inc Semiconductor storage device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105563A (en) * 1981-12-17 1983-06-23 Mitsubishi Electric Corp Substrate bias generating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105563A (en) * 1981-12-17 1983-06-23 Mitsubishi Electric Corp Substrate bias generating circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744996A (en) * 1992-07-01 1998-04-28 International Business Machines Corporation CMOS integrated semiconductor circuit
JP2009181638A (en) * 2008-01-30 2009-08-13 Elpida Memory Inc Semiconductor storage device
US7974140B2 (en) 2008-01-30 2011-07-05 Elpida Memory, Inc. Semiconductor device having a mode register and a plurality of voltage generators

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