Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/40—Materials therefor
  • H01L33/42—Transparent materials
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
  • C25D11/02—Anodisation
  • C25D11/32—Anodisation of semiconducting materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0054—Processes for devices with an active region comprising only group IV elements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/26—Materials of the light emitting region
  • H01L33/34—Materials of the light emitting region containing only elements of Group IV of the Periodic Table
  • H01L33/346—Materials of the light emitting region containing only elements of Group IV of the Periodic Table containing porous silicon
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/96—Porous semiconductor

Definitions

• the present invention relates to a method for producing electroluminescent silicon structures.
• a band gap of a semiconductor material is understood to mean the difference between the energy levels of the valence band and the conduction band, which is occupied by electrons.
• the highest energetic state lies in the valence band directly below the lowest energetic state of the conduction band. This causes a direct transition of electrons into the valence band to result in their recombination with holes (positive charge carriers), which leads to the generation of photons whose energy corresponds to the bandgap of the semiconductor material.
• Typical materials with such a direct band transition are, for example, GaAs compound semiconductors, which for this reason are frequently used for the production of light-emitting elements.
• silicon is a semiconductor material with an indirect band transition.
• the highest energetic state in the valence band is offset from the lowest energetic state in the conduction band, so that there is no direct drop from Electrons can take place in the valence band.
• the electrons of such materials with an indirect band transition must combine both with holes and with phonons. The likelihood of this process is extremely low, since three particles are involved.
• porous silicon layers which are produced by anodizing in a hydrofluoric acid electrolyte, two-dimensional quantum bundles or quantum wires or quantum conductors are formed, which result in a change in the energy band gap of microporous silicon structures compared to single-crystal silicon.
• the present invention is based on the object of specifying a method for producing electroluminescent silicon structures.
• the invention is based on the knowledge that the method known in the prior art for producing photoluminescent silicon structures, in which a silicon wafer is introduced into an acid bath and anodized therein in order to produce a microporous silicon layer, for the production of electroluminescent silicon structures It can be further developed by illuminating the silicon wafer on its anodic side at least for a part of the time during which it is introduced into the acid bath and anodized, whereupon two contacts are generated with which a voltage is applied to the microporous silicon layer can be applied.
• FIG. 1 is a cross-sectional view of a production method according to the invention produced electroluminescent silicon structure
• FIG. 2 shows a device for carrying out essential method steps in the production method according to the invention.
• the silicon component shown in FIG. 1, which is designated in its entirety by reference number 1, is obtained in a manner known per se by separating a multiplicity of identical silicon components which are formed on a common silicon wafer.
• the silicon component 1 comprises a p-type substrate 2, on which an oxide layer 3 is arranged with a central recess 4, which in turn is covered by a nitride layer 5.
• a nitride layer 5 On the nitride layer 5 there is, for example, a ring-shaped metallization 6 in the form of a chrome-gold alloy running around the recess 4.
• the p-substrate 2 is followed by a p + doping region 7 which, like a trough, has an n + doping region lying directly below the recess 4 to form a pn junction
• the silicon within the n + doping region 8 and within a part of the p + doping region 7 is a microporous silicon layer 10.
• the pn junction 9 lies within the microporous silicon layer 10.
• a further nitride layer 11 covers the front of the component 1 with the exception of the recess 4 in the area of the microporous silicon layer
• first electrode 13 which can be formed, for example, by a 120 nm thick gold contact layer or by an approximately 200 nm thick indium tin oxide layer.
• the p-substrate 2 is provided with a second electrode 14 in the form of an ohmic contact.
• the manufacturing process of this silicon component 1 comprises the following process steps:
• the silicon oxide layer 2 serving as an implantation mask is applied to a silicon wafer, for example by thermal oxidation. Then this is structured using known photolithographic measures.
• a first doping step for p + doping of the lower doping region then takes place using this implantation mask, whereupon n + doping of an overlying doping region takes place with reduced implantation energy, whereupon a driving-in diffusion process for driving in the doping substances is carried out.
• This is followed by a process step of depositing the nitride layer 5 over the entire surface, onto which a chromium-gold metallization 6 is applied over the entire surface, which is then structured using known measures for producing the ring-shaped contact zone 6 .
• nitride layer 11 is then deposited over the entire surface, whereupon a photoresist (not shown) is applied and structured. After suitable photolithographic steps, the nitride layer 5, 11 is etched away in the region of the central recess 4 and in the region of the further recess 12 above the metallization, whereupon the photoresist is removed.
• the anodization area of the silicon wafer 20 can be limited laterally by an acid-resistant masking layer, the acid-resistant masking layer being preferred. is opaque.
• a silicon wafer 20 with a plurality of the silicon components 1 structured by the process steps just explained is now further treated in a manufacturing device 21 for carrying out the essential steps of the manufacturing method according to the invention to be explained below.
• the manufacturing device 21 comprises an acid basin 22, in which an acid bath 23 is contained, which contains two to fifty percent by weight of hydrofluoric acid and the rest of ethanol and water.
• An anode 24 and a cathode 25 are provided in the acid bath 23 in an opposing, spaced-apart arrangement.
• a holding device 26 is designed on its periphery in such a way that it lies sealingly against the walls of the acid basin 22 when it is inserted into the acid basin 22 from above.
• the holding device 26 has a central recess 27, at the location of which the silicon wafer 20 is held in a manner sealed at its edge regions.
• the arrangement of the holding device is thus such that a current flow between the anode 24 and the cathode 25 must pass through the silicon wafer 20 vertically to the main surfaces thereof.
• a lighting device 28 in the form of a mercury lamp or halogen lamp is arranged above the acid bath 23 or, in the case of an acid-proof design of the lighting device 28, within the acid bath 23 such that the silicon wafer 20 is illuminated from its anodic side. If the lighting device 28 is arranged outside the acid basin 22, it is preferred to use a (not shown) window to provide for the passage of light. If the lighting device 28 is arranged above the acid basin 22 in the acid bath 23, a mirror can also be provided for deflecting the rays toward the wafer.
• the lighting device can also be a laser.
• an argon ion laser with a wavelength of 488 nm and a surface power density of 5 W / cm 2 is preferred. In this case, it is possible to selectively create luminescent areas by selective anodizing.
• the silicon wafer 20 After the silicon wafer 20 has been inserted into the holding device 26, it is pushed into the acid basin 22 from above. Now the silicon wafer is anodized by applying a corresponding direct current to the anode 24 and the cathode 25 with a current density of 2 to 500 mA / cm 2 , the silicon wafer 20 converting the one in the area of the recesses 4 of the silicon components 1 ⁇ experiences crystalline silicon in a microporous, electroluminescent silicon layer 10. The process of anodizing in the acid bath and the illumination by the lighting device 28 is carried out with a time period such that the microporous silicon layer 10 extends beyond the pn junction 9 into the substrate 2. Typical anodizing and lighting times are between 10 s and 20 min.
• the silicon component After the silicon component has been rinsed, it is provided with the rear ohmic contact 14 and with the transparent electrode 13 on the front.
• the front electrode can be realized by applying a gold cone with a thickness of 120 nm or by applying an indium tin oxide layer with a thickness of 200 nm. After separating the silicon components 1 by appropriately dividing the silicon wafer, the element is finished, apart from a housing.
• the silicon component 1 produced by the method according to the invention has a pn junction within the porous silicon layer 10.
• a pn junction is considered to be preferred for increasing the quantum yield.
• the pn junction is not necessary for the basic functionality of the element, so that the n + doping region 8 can be omitted.
• opposite doping polarities can be used compared to the exemplary embodiment.
• the second electrode 14 it is not necessary for the second electrode 14 to be in the form of a back ohmic contact on the back of the substrate 2. Any type of contacting to the substrate 2, which can also be implemented on the front side, is possible.
• contacts can also be formed in an interdigital structure on the microporous layer by the upper metallization.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Electrochemistry (AREA)
• Materials Engineering (AREA)
• Metallurgy (AREA)
• Organic Chemistry (AREA)
• Led Devices (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=6438333

Family Applications (1)

Country Status (5)

Families Citing this family (22)

Family Cites Families (14)

• 1991
  • 1991-08-14 DE DE4126955A patent/DE4126955C2/de not_active Expired - Fee Related
• 1992
  • 1992-07-20 EP EP92915971A patent/EP0598755A1/de not_active Withdrawn
  • 1992-07-20 US US08/193,085 patent/US5458735A/en not_active Expired - Fee Related
  • 1992-07-20 WO PCT/DE1992/000598 patent/WO1993004503A1/de not_active Application Discontinuation
  • 1992-07-20 JP JP5504006A patent/JP2663048B2/ja not_active Expired - Lifetime

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events