EP0514095A2 - Integrierte Schaltung bestehend aus SRAM-Zellen - Google Patents

Integrierte Schaltung bestehend aus SRAM-Zellen Download PDF

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Publication number
EP0514095A2
EP0514095A2 EP92304178A EP92304178A EP0514095A2 EP 0514095 A2 EP0514095 A2 EP 0514095A2 EP 92304178 A EP92304178 A EP 92304178A EP 92304178 A EP92304178 A EP 92304178A EP 0514095 A2 EP0514095 A2 EP 0514095A2
Authority
EP
European Patent Office
Prior art keywords
polysilicon
gate
layer
circuit
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92304178A
Other languages
English (en)
French (fr)
Other versions
EP0514095B1 (de
EP0514095A3 (en
Inventor
Kuo-Hua Lee
William John Nagy
Janmye Sung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0514095A2 publication Critical patent/EP0514095A2/de
Publication of EP0514095A3 publication Critical patent/EP0514095A3/en
Application granted granted Critical
Publication of EP0514095B1 publication Critical patent/EP0514095B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor integrated circuits and methods for their manufacture.
  • Static semiconductor memories are often referred to as SRAMs ("static random access memory") because (unlike DRAMs or dynamic random access memories) they do not require periodic refresh signals to retain their stored data.
  • SRAMs static random access memory
  • the bit state in an SRAM is stored in a pair of cross-coupled inverters which form a circuit termed a "flip-flop. " The voltage on each of the two outputs of a flip-flop circuit is stable at only one of two possible voltage levels because the operation of the circuit forces one output to a high potential and the other to a low potential.
  • Flip-flops maintain a given state for as long as the circuit receives power, but they can be made to undergo a change in state (i.e., to flip) upon the application of a trigger voltage of sufficient magnitude and duration to the appropriate input.
  • Typical SRAM cells utilize gates formed by the above-mentioned lithographic processes.
  • the above-mentioned variation in linewidth affects gate size, and thus device performance, and ultimately cell performance.
  • the invention includes an interconnection between an access transistor and a pull-down transistor.
  • the embodiment includes: a gate structure; a source or drain proximate the gate; a first dielectric covering the gate; a first material layer covering the first dielectric; a second dielectric at least partially covering the first material layer, the first and second dielectrics have first and second openings respectively which together expose the source or drain region; and a second material layer partially covering the second dielectric and contacting the source or drain region and the first material layer.
  • both the first and second material layers are polysilicon.
  • the first layer contacts the gate of one pull-down transistor and shields the gate of the other pull-down transistor during subsequent etching.
  • the second layer contacts the first layer and the drain of one access transistor, thus forming a node, e.g., reference numeral 15 in FIG. 1.
  • FIG. 1 is a circuit diagram indicating a typical SRAM cell.
  • the operation of the SRAM cell depicted in FIG. 1 essentially involves two inverters and behaves as a flip-flog.
  • Transistors having gates 19 and 21 serve as access transistors. For example, when transistor 19 is turned on, a logic one appearing at node 17 is transmitted to node 15. Node 15 is connected to the gate of pull-down transistor 23. The pull-down transistor 23 begins to conduct, causing a logic low to appear at node 13. The low condition at node 13 turns off the pull-down transistor 25. Consequently, a logic one is observed at node 15 through load 27. Thus, interlocked transistors 23 and 25 serve as a latch circuit. Once a logic low (0) or logic high (1) is entered at node 15 or node 13 it remains dynamically amplified by the circuit.
  • FIG. 1 While there are many implementations of the circuit shown in FIG. 1, applicants desire to implement FIG. 1 circuit in a cell which has a small size and yet exhibits high performance.
  • FIG. 2 there is depicted a diagram illustrating the polysilicon gates and thinox regions (in a top down view) of an illustrarive embodiment of the present invention. Beneath each thinox region is an appropriate semiconductor junction. Consequently, for simplicity in the discussion which follows, various thinox regions will be associated with nodes in FIG. 1.
  • the gates and thinox regions in FIGs. 2-5 are generally drawn to scale. (Those versed in the art will realize that the diagrams of FIGs. 2-5 omit interlevel oxide layers and gate oxides.) Furthermore, enlarged polysilicon landing pads have also been omitted from FIG. 2. It will be noted in reviewing FIG. 2, that polysilicon stripe 20 constitutes both gates 19 and 21 in the circuit diagram of FIG. 1.
  • Nodes 17 and 11 from the circuit diagram of FIG. 1 are indicated as corresponding thinox regions in FIG. 2.
  • nodes 15 and 13 of FIG. 1 are indicated in FIG. 2 as corresponding thinox regions.
  • Polysilicon stripe 25 is the gate of the left hand pull-down transistor 25 in FIG. 1. It will be noted that polysilicon stripe 25 is parallel to polysilicon stripe 20.
  • polysilicon stripe 23 in FIG. 2 corresponds to the gate 23 of the right hand pull-down transistor in the circuit of FIG. 1. It will be noted that polysilicon stripe 23 is parallel to stripes 25 and 20. Thus, it will be noted that all of the gates are laid out in a parallel manner. It will be noted from both figures that gate 25 is between node 15 and the VSS region and gate 23 is between node 13 and VSS.
  • the gates are laid out in whatever direction is astigmatically preferable.
  • the astigmatism of the lens may be evaluated by various techniques including the patterning of test pattern lines and subsequent SEM analyses to determine in which direction the stepper astigmatism is most tolerable.
  • an evaluation of latent images in photoresist as taught in the aforementioned U.S. patent application serial no. 664,187 may be performed.
  • cell layout in accordance with FIG. 2 may be performed.
  • FIG. 3 is similar to FIG. 2 in that it shows three parallel polysilicon stripes 20, 25, and 23. However, FIG. 3 also includes additional polysilicon pads 26 and 28. For simplicity, of course, polysilicon pads 26 and 28 are formed at the same time that polysilicon stripes 20, 25, and 23 are formed. Although pads 26 and 28 are somewhat different in dimension and orientation than polysilicon stripes 20, 25, and 23, their presence and orientation does not affect the performance of the transistors of the SRAM cell. Serifs of various types may be employed in the layout of the polysilicon lines. (For simplicity serifs have been omitted.)
  • FIGs. 4 and 5 illustrate additional layers of the cell and serve to demonstrate the feasibility of the cell layout with parallel gates.
  • FIG. 4 is another top down view of the cell depicted in FIG. 3 with an additional layer of polysilicon deposited. This layer is conventionally referred to as "poly 2.” (It is understood by those skilled in the art that a layer of oxide has been deposited over the gate level poly 1 of FIG. 2 and an appropriate opening made at landing pad 28 in the overlying oxide for contact between the poly 2 layer and landing pad 28.
  • patterned polysilicon pads 31, 33, and 35 have been deposited and formed. Polysilicon pads 31 and 33 serve to provide an enlarged landing pad area for subsequent bit line connection. Polysilicon layer 35 connects to polysilicon pad 28 through a window.
  • Polysilicon layer 35 does not make any direct electrical connection to gate 25. As will be subsequently explained, polysilicon layer 35 serves to protect gate 25 from subsequent etching. Polysilicon layer 35 also partially covers thinox region 15. However, because of the presence of an interlevel oxide (e.g., reference numeral 51 in FIG. 6), at this point in the fabrication process, there is no electrical contact between polysilicon layer 35 and thinox region 15. The presence of polysilicon layer 35 means that it is not necessary that gate 25 be covered by a protective material such as nitride.
  • a protective material such as nitride.
  • FIG. 6 illustrates in cross-sectional detail how polysilicon layer 35 covers gate 25 and partially covers thinox region 15.
  • oxide layer 51 (which is, of course, not shown in FIGs. 2-5) prevents polysilicon layer 35 from making contact with the junction near thinox region 15.
  • another oxide layer 53 has been deposited over polysilicon layer 35.
  • FIG. 5 it is understood by those stilled in the art that after the structure depicted in FIG. 4 has been fabricated, another layer of oxide (e.g., 53 in FIGs. 6-7) is deposited, windows opened where appropriate and, finally, a third layer of polysilicon 60 depicted in FIG. 5 is deposited and patterned. Specifically, two windows are opened, one window over thinox region 13 and the other over thinox region 15. A third layer of polysilicon 60 is deposited and patterned as shown in FIG. 5. Portion 41 of polysilicon layer 60, when deposited over thinox region 13, serves to provide electrical connection via polysilicon pad 26 between polysilicon gate 25 and thinox region 13. Thus, referring to FIG. 1, polysilicon pad 41 provides the cross-connection between the left hand pull-down transistor and node 13.
  • oxide e.g., 53 in FIGs. 6-7
  • Portion 43 of polysilicon layer 60 serves to provide electrical contact between node (thinox 15) to which a window 100 has been opened, as will be recalled, and gate 23 via its connection with polysilicon layer 35 and polysilicon pad 28.
  • FIG. 7 illustrates how polysilicon layer 43 serves to create electrical contact between thinox region 15 and gate 23.
  • FIG. 7 illustrates the structure depicted in FIG. 6 after a window has been opened in oxide layer 53 and polysilicon portion 43 of layer 60 has been deposited therein.
  • Polysilicon layer 35 protects gate 25 from etching during the process of opening the window.
  • the window 100 opened in oxide layer 53 need not be very precisely positioned, i.e., the window dimensions may exceed size of thinox region 15 and may extend over gate 25.
  • there is no risk of damage to gate 25 because of protective polysilicon layer 35.
  • polysilicon portion 43 contacts polysilicon layer 35 and junction 15.
  • polysilicon layer 43 provides the necessary interconnection between gate 23 and node 15 of FIG. 1.
  • polysilicon portion 45 of polysilicon layer 60 is formed over VSS region 46 to create the VCC line. (Of course, polysilicon portions 41, 43, and 45 are all formed at the same time as part of layer 60. They are merely denominated separately for convenience in discussion.)
  • loads 27 and 29 are formed in polysilicon portions 43 and 41, respectively, by selectively doping the pads, leaving an undoped region in the general area of the reference numerals to constitute a resistive load.
  • the doping is accomplished by use of a mask.
  • Metal bit lines are attached to landing pads in the vicinity of polysilicon landing pads 31 and 33.
  • the landing pads advantageously provide for substantial amount of misalignment for the mask for the bit line.

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP92304178A 1991-05-16 1992-05-08 Integrierte Schaltung bestehend aus SRAM-Zellen Expired - Lifetime EP0514095B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/701,270 US5128738A (en) 1991-05-16 1991-05-16 Integrated circuit
US701270 1996-08-22

Publications (3)

Publication Number Publication Date
EP0514095A2 true EP0514095A2 (de) 1992-11-19
EP0514095A3 EP0514095A3 (en) 1992-12-30
EP0514095B1 EP0514095B1 (de) 1997-11-05

Family

ID=24816679

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92304178A Expired - Lifetime EP0514095B1 (de) 1991-05-16 1992-05-08 Integrierte Schaltung bestehend aus SRAM-Zellen

Country Status (7)

Country Link
US (1) US5128738A (de)
EP (1) EP0514095B1 (de)
JP (1) JP2662144B2 (de)
KR (1) KR100257953B1 (de)
DE (1) DE69222973T2 (de)
ES (1) ES2109311T3 (de)
TW (1) TW198131B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213990A (en) * 1992-04-01 1993-05-25 Texas Instruments, Incorporated Method for forming a stacked semiconductor structure
JPH05283654A (ja) * 1992-04-03 1993-10-29 Toshiba Corp マスクｒｏｍとその製造方法
US5721445A (en) * 1995-03-02 1998-02-24 Lucent Technologies Inc. Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity
US5631112A (en) * 1995-11-16 1997-05-20 Vanguard International Semiconductor Corporation Multiple exposure method for photo-exposing photosensitive layers upon high step height topography substrate layers
US5707765A (en) * 1996-05-28 1998-01-13 Microunity Systems Engineering, Inc. Photolithography mask using serifs and method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0124115A2 (de) * 1983-04-28 1984-11-07 Kabushiki Kaisha Toshiba Halbleiter-ROM-Anordnung und Herstellungsverfahren
EP0365690A1 (de) * 1988-05-07 1990-05-02 Seiko Epson Corporation Halbleiteranordnung und halbleiter-speicheranordnung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS59231851A (ja) * 1983-06-14 1984-12-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリセル
JPH0628302B2 (ja) * 1984-02-28 1994-04-13 富士通株式会社 半導体記憶装置
JPS63126270A (ja) * 1986-11-14 1988-05-30 Mitsubishi Electric Corp 半導体記憶装置
JPH0831533B2 (ja) * 1988-10-21 1996-03-27 セイコーエプソン株式会社 半導体記憶装置
JPH0735399Y2 (ja) * 1989-05-12 1995-08-09 ソニー株式会社 半導体メモリ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0124115A2 (de) * 1983-04-28 1984-11-07 Kabushiki Kaisha Toshiba Halbleiter-ROM-Anordnung und Herstellungsverfahren
EP0365690A1 (de) * 1988-05-07 1990-05-02 Seiko Epson Corporation Halbleiteranordnung und halbleiter-speicheranordnung

Also Published As

Publication number Publication date
TW198131B (de) 1993-01-11
EP0514095B1 (de) 1997-11-05
US5128738A (en) 1992-07-07
JP2662144B2 (ja) 1997-10-08
EP0514095A3 (en) 1992-12-30
DE69222973D1 (de) 1997-12-11
KR920022535A (ko) 1992-12-19
JPH05160369A (ja) 1993-06-25
DE69222973T2 (de) 1998-03-05
KR100257953B1 (ko) 2000-06-01
ES2109311T3 (es) 1998-01-16

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