EP0484423B1 - Digitales signalverarbeitungssystem - Google Patents

Digitales signalverarbeitungssystem Download PDF

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Publication number
EP0484423B1
EP0484423B1 EP90911932A EP90911932A EP0484423B1 EP 0484423 B1 EP0484423 B1 EP 0484423B1 EP 90911932 A EP90911932 A EP 90911932A EP 90911932 A EP90911932 A EP 90911932A EP 0484423 B1 EP0484423 B1 EP 0484423B1
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EP
European Patent Office
Prior art keywords
components
segments
circuit
signal
important
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP90911932A
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German (de)
English (en)
French (fr)
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EP0484423A1 (de
Inventor
Heinz-Werner Keesen
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Deutsche Thomson Brandt GmbH
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Deutsche Thomson Brandt GmbH
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
    • G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
    • G11B15/1808—Driving of both record carrier and head
    • G11B15/1875—Driving of both record carrier and head adaptations for special effects or editing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/005—Reproducing at a different information rate from the information rate of recording
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/005—Reproducing at a different information rate from the information rate of recording
    • G11B27/007—Reproducing at a different information rate from the information rate of recording reproducing continuously a part of the information, i.e. repeating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
    • G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
    • G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/92—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N5/926—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation
    • H04N5/9261—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation involving data reduction
    • H04N5/9264—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback by pulse code modulation involving data reduction using transform coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
    • H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction
    • H04N9/8047—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction using transform coding
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/90—Tape-like record carriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/78—Television signal recording using magnetic recording
    • H04N5/782—Television signal recording using magnetic recording on tape
    • H04N5/783—Adaptations for reproducing at a rate different from the recording rate

Definitions

  • the invention relates to a digital signal processing system for sectionally coded signals.
  • the information density is often subject to temporal fluctuations. This can apply both to untreated signals and, for example, to those video signals that were treated with a source encoder to reduce irrelevance and redundancy.
  • Designing the transmission path or the recording medium for the maximum information density is technically complex and uneconomical. If the transmission or recording capacity is limited to an average information density by temporal compression and subsequent expansion, that is to say by different word lengths of the data sections depending on the information density, the problem arises of recognizing the differently long data sections for the blocks after the transmission or recording and assign the blocks the correct location for the original image. This recognition is particularly difficult when faults remove the recognition criteria. It can then occur that a correct one even after the disorder has subsided Evaluation of the subsequent data sections is not possible.
  • the invention has for its object to improve a method for digital signal recording and playback so that even when playing back sections of coded signals with increased speed (search), the signal, e.g. an image that can be decoded with sufficient quality.
  • the data to be recorded can consist, for example, of coefficients of a DCT transformation.
  • DCT means: discrete cosine transform.
  • the direct component and one or more important alternating component (s) and a final end-of-block identifier are recorded per block. If the data section length of the coded block is smaller is as an average block data section length, the remaining available space is filled with alternating parts of a block which requires a larger than the average data section length and, if appropriate, with the corresponding end of block identifier.
  • the beginning of the block can be found at regular intervals in the event of read errors during playback.
  • the read heads move, for example in the case of a conventional helical scan recording method (helical track), at an angle changed over the recorded tracks compared to normal playback mode. Even with a certain read head tracking, e.g. with actuators, the tracks can only be read in sections. The question then is which spatial position in the entire decoded signal the section of blocks that is read should have.
  • the solution is that position information is inserted at certain points in the signal to be recorded and the signal parts belonging to these points are arranged in the decoded signal in accordance with the position information.
  • the end-of-block identifier is suitable for this. However, if position information is added to each end of block identifier, the amount of data to be recorded can increase significantly.
  • Another possibility is to combine several blocks, for example eight, into a larger block, hereinafter referred to as super block, and to provide an address for the position in the picture at the beginning or end.
  • super block By recording an address for only one super block each, the data rate is increased only slightly and the overall coding efficiency is increased. From approximately the same time intervals decoded super blocks, the output signal is then composed. It is segmented according to the superblock size and can have an unchanged spatial resolution.
  • Another possibility is to change the recording sequence of the DC and AC components of the transformation coefficients known from DE-A-37 02 490.
  • Such a track section of the signal can e.g. represent a segment or two segments, i.e. in the case of an image signal, an image can e.g. consist of two segments or only one segment.
  • Figure 1 shows a video signal processing system, e.g. the video signal part of a digital video recorder, with a circuit 11 which separates an incoming analog CVBS signal into a luminance component and a chrominance component.
  • the luminance signal is fed to the A / D converter 12, in a circuit 13 e.g. two-dimensionally DCT transformed, modulated in a circuit 14 with a channel coding, in a memory 15, e.g. a magnetic tape, stored, demodulated in a circuit 16 according to the channel coding, in a circuit 17 e.g. two-dimensionally inversely DCT-transformed and combined via a D / A converter 18 with the corresponding chrominance signal from the D / A converter 181 in a circuit 19 to form an analog CVBS signal.
  • a circuit 13 e.g. two-dimensionally DCT transformed, modulated in a circuit 14 with a channel coding, in a memory 15, e.g. a magnetic tape, stored, demodulated in a circuit 16 according to the channel coding, in a circuit 17 e.g. two-dimensionally inversely DCT-transformed and combined via a D / A converter 18 with the corresponding chrominance signal from the D /
  • the chrominance signal is processed in circuits 121-181 in accordance with the luminance signal in corresponding circuits 12-18.
  • the circuits 12 to 18 can be used for a sound channel, for example, and the circuits 11, 19 and 121 to 181 are omitted.
  • FIG. 2 shows a magnetic tape 20 with recorded oblique tracks 21.
  • the general direction of a video head movement on the magnetic tape 20 in the search run is indicated by the dashed line 22.
  • the video heads which are not shown here, are arranged, for example, on actuators, they can be piece by piece 23 follow a track 21 and read digital data. Between these data sections 23, the video heads jump 24 to the next or further away track 21.
  • FIG. 3 shows the arrangement of portions of video signals coded in blocks on tracks of a magnetic tape.
  • a magnetic tape track section 31 is shown with three data blocks A, B, C of the same length with the respective block end identification A4, B4, C4.
  • a track section 32 with three data blocks a, b, c of different lengths is also shown.
  • the respective lengths correspond to the number of data which, for example, a DCT encoder delivers for each of the blocks a, b, c.
  • a1, b1 and c1 are equal components
  • a2, b2 and c2 are important alternating components
  • a3, b3 and c3 are less important alternating components
  • a4, b4 and c4 are end-of-block markings.
  • Data recording as on track section 32 leads to an uneven block length, which makes it difficult to find the beginning of a block when reading errors occur during playback.
  • a uniform block length as on track section 31 is advantageous.
  • a portion of the less important alternating portions c3F from a block c with a larger than the average amount of data b is appended to a block a with a smaller than the average amount of data b, if possible with the corresponding end of block identifier signal c4, as shown on track section 33.
  • This method is known (DE-A-37 02 490), but is not sufficient to provide information as to where the read and decoded data are in a "search mode", in which the helical tracks 21 of the magnetic tape 20 can only be read partially of the track sections 23 in the output image of a VCR are to be arranged because, for example, only the first block of an entire image is marked as such.
  • This information could be given by adding appropriate data to the block end identifiers a4, b4, c4. For example, with an image size of 540 x 576 pixels with a block size of 8 x 8 pixels and a coding data rate of approximately 1 bit / pixel, approximately 77 bits would then be necessary for each block instead of approximately 64 bits.
  • the track sections 23 comprise a corresponding number of blocks, several, e.g. eight, combine blocks into a "super block" and only add address information 401 or 402 per super block.
  • a coder must be controlled so that the data for the last block in the superblock can still be stored in the memory space for this track block. Free spaces can be filled with the value "zero".
  • FIG. 4 shows a track of the magnetic tape with such a super block 40, which consists of blocks 41 to 48, which correspond to blocks such as A, B, C of 31 and 33, respectively, and an address 401 or 402.
  • FIG. 5 shows the position of superblocks 51 to 54 in the output image 50 of a video recorder in the search mode.
  • Good spatial resolution can be achieved.
  • the image is strongly segmented and therefore has a reduced temporal resolution.
  • FIG. 6 shows a lower segmentation by a further method.
  • the entire image 60 can also consist of a segment 60.
  • Fig. 7 shows the corresponding form of storage of the coding signal components on a track of the magnetic tape.
  • the constant components a1, b1 and n1 are written to the beginning of the storage space for the segment 61, 62 and 60, respectively.
  • an identifier 701 or 702 for the position of the segment 61, 62 or 60 can be inserted in the image 60.
  • a coder is to be regulated in such a way that the data n1 to n6 for the last block in the segment (e.g. 61, 62 or 60) can still be stored in the storage space provided for the segment. Free spaces can be filled with the value "zero".
  • a segment-free display in the search run is achieved, for example, when the equal parts of all blocks of an image or several images are stored in one track of the magnetic tape and the video heads can only scan a corresponding area of the track during the search run at high speed. Even with this high search speed, it is then possible to decode an image with reduced spatial resolution.
  • FIG. 8 shows the block diagram of a coder for the method according to FIGS. 3 to 5, which contains the circuits 811, 821, 823, 831, 833, 841 and 851, a transmission path or a storage medium 86 and the block diagram of a decoder which includes circuits 812, 822, 824, 830, 832, 842 and 852.
  • the coder can e.g. be included in circuit 14 and 141 and the decoder in circuit 16 and 161.
  • Block-by-block DCT-encoded image signals are supplied to circuit 811, which includes a quantizer and which encodes the variable word length signals.
  • Corresponding output signals a1 to a3, b1 to b3, c1 to c3 are supplied to the circuit 821, which essentially contains a multiplexer, in which it e.g. into constant components a1, b1, c1, important alternating components a2, b2, c2 and less important alternating components a3, b3, c3 are split.
  • DC components a1, b1, c1 are loaded into a first FIFO memory 831 and AC components a2, a3, b2, b3, c2, c3 are loaded into a second FIFO memory 833.
  • FIFO means: first in, first out.
  • the fill level of the first FIFO memory 831 or the fill level of the second FIFO memory 833 or a combination, e.g. the sum of the two fill levels can advantageously be used as a control variable for the quantizer characteristic of the circuit 811.
  • the quantizer characteristic of the circuit 811 and the size of the FIFO memories 831 and 833 must be dimensioned such that no overflow or underflow occurs in the FIFO memories 831 and 833.
  • circuit 823 direct and alternating components a1 to a3, b1 to b3, c1 to c3 from the two FIFO memories 831 and 833 are combined in one according to the arrangement on track section 33 Demultiplexer assembled and block end markings a4, b4, c4 added and in circuit 851, several blocks A, B, C are combined to form a super block 40 and provided with super block address information 401 and 402 and, for example, with channel modulation and error protection.
  • the control circuit 841 receives signals from the circuit 821 which indicate the respective processing of signal components a1 to c1 or a2 to c2 or a3 to c3 or c3F and from the input 803 signals which indicate the position of the current block in the signal before coding or after decoding.
  • the control circuit 841 provides the respective read and write addressing for the FIFO memories 831 and 833, controls the circuit 823 with the demultiplexer and the insertion of end-of-block markings a4, b4, c4 and the circuit 851 during the combination and addressing 401 and 402 of super blocks 40.
  • the output signal of the circuit 851 is then transmitted 86 or stored 86 and fed to the decoder when the circuit 852 is reproduced.
  • Superblock addresses 401 and 402 are available at output 804 of the decoder.
  • a circuit 824 which essentially contains a multiplexer and an end-of-block marker decoder, direct components a1, b1, c1 or alternating components a2, a3, b2, b3, c2, c3, c3F are separated from the data stream and into a third FIFO memory 830 or a fourth FIFO memory 832 loaded.
  • circuit 822 which essentially contains a demultiplexer, in a form, such as shown on track section 32, arranged and decoded in circuit 812 according to its variable word length.
  • Signal blocks with a constant word length and their associated address 804 are then again available at the output 802 of the decoder, jumping superblock by block in the "search mode".
  • the control circuit 842 receives block addresses from circuit 852, for example, and thus supplies the read and write addressing for direct components a1, b1, c1 or alternating components a2, a3, b2, b3, c2, c3, c3F in the FIFO memories 830 and 832, and also controls the multiplexer in circuit 824 and the demultiplexer in circuit 822.
  • FIG. 9 shows the block diagram of a coder which contains the circuits 911, 921, 923, 931, 933, 935, 937, 939, 941 and 951, a transmission path or a storage medium 96 and the block diagram of a decoder which contains the circuits 912, 922, 924, 930, 932, 934, 936, 938, 942 and 952.
  • the coder can e.g. be included in circuit 14 and 141 and the decoder in circuit 16 and 161.
  • block-by-block DCT-coded image signals are fed to the circuit 911 containing a quantizer, which encodes the signals with variable word length.
  • Corresponding output signals a1 to a3, b1 to b3, c1 to c3 are fed to the circuit 821, which essentially contains a multiplexer, in which they contain, for example, DC components a1, b1, c1, important AC components a2, b2, c2 and less important AC components a3, b3 , c3 are split.
  • DC components a1, b1 to n1 of a segment are loaded into a first FIFO memory 931, important AC components a2, b2 to n2 of the segment or image are loaded into a second FIFO memory 933 and less important AC components a3, b3 to n3 of the segment or image in a third FIFO memory 935.
  • the addresses a5, b5 to n5 of the important alternating components a2, b2 to n2 of the segment or image are loaded into a fourth FIFO memory 937 and the addresses a6, b6 to n6 of the less important alternating components a3, b3 to n3 of the segment or image in a fifth FIFO memory 939.
  • the fill level or the fill levels of a FIFO memory or several FIFO memories 931, 933, 935, 937, 939 or the sum of the fill levels can or can advantageously be used as a control variable for the quantization characteristic of the circuit 911.
  • the quantization characteristic of the circuit 911 and the size of the FIFO memories 931, 933, 935, 937, 939 must be dimensioned such that no overflow or underflow occurs in the FIFO memories 931, 933, 935, 937, 939.
  • DC and AC components a1, b1 to n1, a2, b2 to n2, a3, b3 to n3 and their addresses a5, b5 to n5, a6, b6 to n6 are generated from the five FIFO memories 931, 933, 935, 937, 939 compiled in a demultiplexer according to the arrangement on the track section in FIG. 7.
  • segments 61, 62 are identified with their addresses 701 and 702 in image 60 and images 60 with their image number 701 and 702, and e.g. provided with channel modulation and error protection.
  • the control circuit 941 receives from the circuit 921 signals which indicate the respective processing of signal components a1, b1 to n1, a2, b2 to n2 or a3, b3 to n3 and from the input 903 signals which indicate the position of the current block in the signal after coding or after decoding.
  • the control circuit 941 supplies the respective read and write addressing for the FIFO memories 931, 933, 935, 937, 939, controls the circuit 923 with the demultiplexer and the circuit 951 with the addressing 701 and 702 respectively Segments 61, 62 or when assigning picture numbers 701 or 702 of pictures 60.
  • the output signal of the circuit 951 is then transmitted 96 or stored 96 and fed to the decoder when the circuit 952 is reproduced.
  • the segment addresses or the picture numbers 701, 702 are available at the output 904 of the decoder.
  • a circuit 924 which essentially contains a multiplexer and an address decoder, direct components a1, b1 to n1, important alternating components a2, b2 to n2 and their addresses a5, b5 to n5, less important alternating components a3, b3 to n3 and their addresses a6, b6 to n6 separated from the data stream and loaded into a sixth 930 or seventh 932 or ninth 936 or eighth 934 or tenth 938 FIFO memory.
  • circuit 922 which essentially contains a demultiplexer, in a form, for example as shown on track section 32, and decoded in circuit 912 according to its variable word length.
  • signal blocks with a constant word length and their associated address 904 in the picture or picture number 904 are again available, in the "search run" operating mode segment or picture by e.g. before decoding, zeros filled in less important alternating components a3, b3 to n3.
  • the control circuit 942 receives block addresses from circuit 952, for example, and thus supplies the read and write addresses for direct components a1, b1 to n1 or important alternating components a2, b2 to n2 or less important alternating components a3, b3 to n3 and their addressing in the FIFO memories 930, 932, 934, 936, 938, and also controls the multiplexer in circuit 924 and the demultiplexer in circuit 922.
  • a device e.g. a video recorder, a coder and a decoder
  • circuits of the encoder e.g. the FIFO memories 831 and 833 or 931, 933, 935, 937, 939 are advantageously used by the decoder and thereby corresponding circuits of the decoder, e.g. the FIFO memories 830 and 832 and 930, 932, 934, 936, 938 are omitted.

Landscapes

  • Signal Processing (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Communication Control (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Color Television Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Semiconductor Memories (AREA)
  • Steroid Compounds (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
EP90911932A 1989-08-03 1990-08-01 Digitales signalverarbeitungssystem Expired - Lifetime EP0484423B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3925663 1989-08-03
DE3925663A DE3925663A1 (de) 1989-08-03 1989-08-03 Digitales signalverarbeitungssystem
PCT/EP1990/001258 WO1991002430A1 (de) 1989-08-03 1990-08-01 Digitales signalverarbeitungssystem

Publications (2)

Publication Number Publication Date
EP0484423A1 EP0484423A1 (de) 1992-05-13
EP0484423B1 true EP0484423B1 (de) 1994-12-21

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EP90911932A Expired - Lifetime EP0484423B1 (de) 1989-08-03 1990-08-01 Digitales signalverarbeitungssystem

Country Status (15)

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US (3) US5239308A (fi)
EP (1) EP0484423B1 (fi)
JP (3) JP3037407B2 (fi)
KR (1) KR100189228B1 (fi)
CN (1) CN1022782C (fi)
AT (1) ATE116088T1 (fi)
AU (1) AU6150790A (fi)
DD (1) DD298980A5 (fi)
DE (2) DE3925663A1 (fi)
ES (1) ES2067753T3 (fi)
FI (1) FI104777B (fi)
HK (1) HK50696A (fi)
HU (1) HUT63529A (fi)
MY (1) MY106829A (fi)
WO (1) WO1991002430A1 (fi)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3925663A1 (de) * 1989-08-03 1991-02-07 Thomson Brandt Gmbh Digitales signalverarbeitungssystem
JP2650472B2 (ja) * 1990-07-30 1997-09-03 松下電器産業株式会社 ディジタル信号記録装置およびディジタル信号記録方法
US5253275A (en) 1991-01-07 1993-10-12 H. Lee Browne Audio and video transmission and receiving system
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CN1022782C (zh) 1993-11-17
JP3037407B2 (ja) 2000-04-24
JPH04507484A (ja) 1992-12-24
HUT63529A (en) 1993-08-30
JP3242906B2 (ja) 2001-12-25
DE3925663A1 (de) 1991-02-07
JP2000201326A (ja) 2000-07-18
JP3171336B2 (ja) 2001-05-28
DE59008094D1 (de) 1995-02-02
MY106829A (en) 1995-07-31
FI920448A0 (fi) 1992-01-31
HU9200264D0 (en) 1992-04-28
WO1991002430A1 (de) 1991-02-21
FI104777B (fi) 2000-03-31
HK50696A (en) 1996-03-29
US6101314A (en) 2000-08-08
EP0484423A1 (de) 1992-05-13
US5239308A (en) 1993-08-24
JP2000201325A (ja) 2000-07-18
KR100189228B1 (ko) 1999-06-01
ATE116088T1 (de) 1995-01-15
ES2067753T3 (es) 1995-04-01
AU6150790A (en) 1991-03-11
US5758012A (en) 1998-05-26
DD298980A5 (de) 1992-03-19

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